JP2012023517A - Voltage output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage output circuit which can minimize a ground fault current after a ground fault is detected and before an output transistor is turned off.SOLUTION: In a voltage output circuit 10, a first conductivity type first insulated gate field effect transistor 13 is connected between a voltage input terminal 11 and a voltage output terminal 12. Gate electrode of the first insulated gate field effect transistor 13 is connected to a first node N1. In response to an input signal supplied to an input node Nin, a drive circuit 17 outputs a control signal for controlling conduction of the first insulated gate field effect transistor 13 to the first node N1. Current limit means 22 is connected between the voltage input terminal 11 and the voltage output terminal 12. The current limit means 22 controls the potential Vn1 of the first node N1 to reduce a current Idr flowing through the first insulated gate field effect transistor 13 when the potential difference ΔV between the voltage input terminal 11 and the voltage output terminal 12 is larger than a reference value.

Description

  Embodiments described herein relate generally to a voltage output circuit.

  2. Description of the Related Art Conventionally, a voltage output circuit that supplies a relatively large amount of power incorporates a protection circuit against a short circuit between a voltage output terminal and a ground terminal, that is, a so-called ground fault (for example, see Patent Document 1).

  The ground fault protection circuit monitors the source-drain voltage or drain current of the output transistor that constitutes the output stage of the voltage output circuit, and when the source-drain voltage or drain current exceeds the allowable range, the output transistor is turned off. Configured to turn off. Thereby, destruction of the output transistor due to the ground fault current is prevented.

  The shorter the time from when the ground fault occurs until the output transistor is turned off, the better. This is because an output transistor having a small drain current capacity, that is, a small element size can be used.

  On the other hand, regarding the load connected to the voltage output circuit, it may not be preferable if the current is immediately cut off when a ground fault occurs. This is because a device that becomes a load may malfunction. For example, if the load includes a storage element and current is interrupted while data is being written to the storage element, the stored data may be lost.

  For this reason, some ground fault protection circuits are configured to intentionally have a delay time and turn off the output transistor when a ground fault occurs.

  In this case, it is necessary to use an output transistor having a large element size so that the output transistor is not destroyed after the ground fault is detected until the output transistor is turned off. As a result, there is a problem that the chip size increases and the manufacturing cost increases.

  Accordingly, there has been a demand for a voltage output circuit that can secure a delay time from when a ground fault is detected until the output transistor is turned off, and can suppress an increase in the element size of the output transistor.

JP 2005-252663 A

  The present invention provides a voltage output circuit capable of suppressing a ground fault current from when a ground fault is detected until the output transistor is turned off.

  According to one embodiment, in the voltage output circuit, the first conductivity type first insulated gate field effect transistor is connected between the voltage input terminal and the voltage output terminal. The gate electrode of the first insulated gate field effect transistor is connected to the first node. The drive circuit outputs a control signal for controlling conduction of the first insulated gate field effect transistor to the first node according to an input signal supplied to the input node. A current limiting means is connected between the voltage input terminal and the voltage output terminal. The current limiting unit controls the potential of the first node so as to reduce a current flowing through the first insulated gate field effect transistor when a potential difference between the voltage input terminal and the voltage output terminal is larger than a reference value. To do.

1 is a circuit diagram showing a voltage output circuit according to Embodiment 1 of the present invention. 3 is a timing chart illustrating the operation of the voltage output circuit according to the first embodiment of the invention. The circuit diagram which shows the voltage output circuit of the comparative example which concerns on Example 1 of this invention. 4 is a timing chart showing the operation of the voltage output circuit of the comparative example according to the first embodiment of the present invention. The circuit diagram which shows the voltage output circuit which concerns on Example 2 of this invention. The circuit diagram which shows the principal part of the voltage output circuit which concerns on Example 3 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  The voltage output circuit according to this embodiment will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a voltage output circuit of this embodiment, and FIG. 2 is a timing chart showing the operation of the voltage output circuit. In this embodiment, the voltage output circuit is a switching regulator based on PWM control.

  As shown in FIG. 1, the voltage output circuit 10 of this embodiment includes a P-channel (first conductivity type) output MOS transistor (first insulated gate field effect transistor) between a voltage input terminal 11 and a voltage output terminal 12. 13 is connected. The gate electrode of the output MOS transistor 13 is connected to the first node N1.

  The voltage input terminal 11 is connected to a power source (not shown) having an input voltage Vin of 36V, for example. The voltage output terminal 12 is connected to a load (not shown) through a smoothing circuit (not shown) having an inductor and a capacitor.

  The output MOS transistor 13 is a high breakdown voltage DMOS transistor (Double-Diffused MOSFET) formed by, for example, a double diffusion method. The source of the output MOS transistor 13 is connected to the high potential line 14, and the high potential line 14 is connected to the voltage input terminal 11. The drain of the output MOS transistor 11 is connected to the low potential line 15, and the low potential line 15 is connected to the voltage output terminal 12.

  The output control circuit 16 outputs an output control signal, such as a PWM (Pulse Width Modulation) signal having a repetition frequency of about 20 kHz to 200 KHz, to the input node Nin so that the output voltage Vout of the voltage output terminal 12 becomes a target voltage. . The drive circuit 17 drives the output MOS transistor 13 on and off based on the PWM signal.

  The drive circuit 17 includes a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) 18 having gate electrodes connected to each other, an N-channel (second conductivity type) MOS transistor (hereinafter referred to as an NMOS transistor) 19, and a PMOS. This is a CMOS inverter composed of a resistor R 1 connected between a transistor 18 and an NMOS transistor 19. The PMOS transistor 18 and the NMOS transistor 19 are high breakdown voltage DMOS transistors like the output MOS transistor 13.

  The drive circuit 17 is connected between the voltage input terminal 11 and a power source (not shown) having an intermediate voltage Vm of 31V, for example. As a result, the operating voltage of the drive circuit 17 becomes a voltage 5V which is the difference between the input voltage Vin and the intermediate voltage Vm, and therefore, a control signal of approximately Vin and approximately Vin-5V is output to the first node N1. The resistor R1 is connected to further lower the gate voltage of the output MOS transistor 13 when a ground fault is detected as will be described later.

  When the potential of the input node Nin is low level, the PMOS transistor 18 is turned on, the NMOS transistor 19 is turned off, and the potential Vn1 of the first node N1 becomes high level (≈Vin). As a result, the gate voltage Vgs1 of the output MOS transistor 13 becomes 0, and the output MOS transistor 13 is turned off.

  When the potential of the input node Nin is at a high level, the PMOS transistor 18 is turned off and the NMOS transistor 19 is turned on, so that the potential of the first node N1 is at a low level (≈Vin−5V). As a result, the gate voltage Vgs1 of the output MOS transistor 13 becomes 5V, and the output MOS transistor 13 is turned on.

  In the voltage output circuit 10, the ground fault protection circuit includes a first comparator 20, a first voltage source 21, and an output control circuit 16. A ground fault is detected by the first comparator 20 and the first voltage source 21.

  When a ground fault is detected, the output control circuit 16 holds the PWM signal at a low level after providing a delay time via an internal logic circuit. As a result, the output MOS transistor 13 is turned off, and the ground fault current Idr flowing through the output MOS transistor 13 is cut off.

  In the first comparator 20, a negative input terminal (first input terminal) 20a is connected to the voltage input terminal 11 via a first voltage source 21 that generates the first reference voltage Vref1, and a positive input terminal (second input terminal). 20 b is connected to the voltage output terminal 12.

  The first comparator 20 compares the potential difference ΔV = Vin−Vout between the voltage input terminal 11 and the voltage output terminal 12, that is, the source-drain voltage Vds1 of the output transistor 13 and the first reference voltage Vref1, and outputs the comparison result. Input to the output control circuit 16 from the terminal 20c. The first comparator 20 determines that a ground fault has occurred when the potential difference ΔV (Vds1) is greater than the first reference voltage Vref1.

  The current limiting means 22 is connected between the voltage input terminal 11 and the voltage output terminal 12, and when a ground fault occurs, the potential of the first node N1 is reduced so as to reduce the ground fault current Idr flowing through the output MOS transistor 13. It is configured to control Vn1.

  The current limiting means 22 includes a second comparator 23, a second voltage source 24, and a PMOS transistor (second insulated gate field effect transistor) 25.

  The second comparator 23 has a negative input terminal (first input terminal) 23a connected to the voltage input terminal 11 via a second voltage source 24 that generates the second reference voltage Vref2, and a positive input terminal (second input terminal). 23 b is connected to the voltage output terminal 12.

  The PMOS transistor 25 is connected between the voltage input terminal 11 and the first node N 1, and the gate electrode is connected to the output terminal 23 c of the second comparator 23.

  The second comparator 23 compares the potential difference ΔV (Vds1) with the second reference voltage Vref2, and inputs the comparison result from the output terminal 23c to the gate electrode of the PMOS transistor 25. The second comparator 23 determines that a ground fault has occurred when the potential difference ΔV (Vds1) is greater than the second reference voltage Vref2.

  When a ground fault is detected, the output of the second comparator 23 goes low, so the gate voltage Vgs2 of the PMOS transistor 25 is raised and the PMOS transistor 25 is turned on.

  When the PMOS transistor 25 is turned on, the potential (Vin−Vds2) of the difference between the input voltage Vin and the source-drain voltage Vds2 of the PMOS transistor 25 is applied to the first node N1.

  If the source-drain voltage Vds2 of the PMOS transistor 25 is 3V, for example, the potential of the first node N1 is raised from Vin-5V to Vin-3V. Accordingly, since the gate voltage Vgs1 of the output MOS transistor 13 is lowered from 5V to 3V, the ground fault current Idr of the output MOS transistor 13 can be suppressed.

  In other words, the gate voltage Vgs1 of the output MOS transistor 13 is the sum of the on-resistance Ron25 of the PMOS transistor 25, the on-resistance Ron19 of the NMOS transistor 19, and the resistance R1 as a difference (Vin−Vm) between the input voltage Vin and the intermediate voltage Vm. The value divided by the resistance is Vgs1 = (Vin−Vm) × Ron25 / (Ron25 + R1 + Ron19).

  For example, when Ron25 = Ron19 = 20Ω and R1 = 50Ω, Vin−Vm = 5V, so Vgs1 = 1.11V. On the other hand, when the resistor R is not provided, Vgs1 = 2.5V because R = 0.

  Next, the operation of the voltage output circuit 10 will be described in detail. FIG. 2 is a timing chart showing the operation of the voltage output circuit 10.

  As shown in FIG. 2, it is assumed that the output of the output control circuit 16 is at a high level as an initial state. As a result, the potential of the input node Nin is at a high level, and the potential Vn1 of the first node N1 is at a low level (≈Vin−5V), so that the gate voltage Vgs1 of the output MOS transistor 13 becomes 5V, and the output MOS transistor 13 It is on. However, since there is no load, the drain current Idr is 0, and the output voltage Vout of the voltage output terminal 12 is equal to the input voltage Vin.

  Since the potential difference ΔV (Vds1) between the voltage input terminal 11 and the voltage output terminal 12 is 0 and smaller than the first reference voltage Vref1, the output of the first comparator 20 is at a high level. The same applies to the second comparator 23, and the description thereof is omitted.

  Assume that at time t1, the voltage output terminal 12 contacts the GND terminal and a ground fault occurs. Due to the ground fault, the potential Vout of the voltage output terminal 12 is changed from Vin to 0. The potential Vn1 of the first node N1 remains Vin-5V, and the output MOS transistor 13 remains on.

  As a result, the ground fault current Idr flows through the output MOS transistor 13. The ground fault current Idr rises with a delay time τ 0 corresponding to the response speed of the output MOS transistor 13.

  Since the potential difference ΔV (Vds1) between the voltage input terminal 11 and the voltage output terminal 12 is larger than the first reference voltage Vref1, the output of the first comparator 20 has a delay time τ1 corresponding to the response speed of the first comparator 20, Invert from High level to Low level. The same applies to the second comparator 23, and the description thereof is omitted.

  When the output of the first comparator 20 becomes low level at time t2, the output of the output control circuit 16 changes from high level to low level with a delay time τ2 provided intentionally. At this point, the ground fault protection circuit is not yet functioning.

  On the other hand, when the output of the second comparator 23 becomes low level, the PMOS transistor 25 is immediately turned on by raising the gate voltage Vgs2, so that the potential Vn1 of the first node N1 is raised. As a result, the gate voltage Vgs1 of the output MOS transistor 13 is lowered from 5V to 3V.

  As a result, the rise of the ground fault current Idr of the output MOS transistor 13 is suppressed, and the ground fault current Idr1 can be suppressed to be smaller than the final ground fault current Idr2. Therefore, there is no possibility that the output MOS transistor 13 is damaged and destroyed.

  When the output of the output control circuit 16 becomes low level at time t3, the potential of the input node Nin also becomes low level, and the output (control signal) of the drive circuit 17 is the response speed of the drive circuit 17 (inverter operation delay). It becomes a High level with a delay time τ3 corresponding to.

  At time t4, the potential Vn1 of the first node N1 becomes Vin. The gate voltage Vgs1 of the output MOS transistor 13 is lowered to zero. As a result, the output MOS transistor 13 is turned off, and the ground fault current Idr can be made zero. At this point, the ground fault protection circuit has finally worked.

  FIG. 3 is a diagram showing a voltage output circuit of a comparative example, and FIG. 4 is a timing chart showing the operation of the voltage output circuit of the comparative example. As shown in FIG. 3, the voltage output circuit 30 of the comparative example is a voltage output circuit that does not have the current limiting means 22.

  As shown in FIG. 4, in the voltage output circuit 30 of the comparative example, the operation up to the time t2 is the same as that of the voltage output circuit 10 of the present embodiment. On the other hand, the ground fault current Idr continues to rise even when the time t2 is exceeded. The output MOS transistor 13 is turned off at time t4 and the ground fault current Idr is changed from Idr2 to 0 as in the voltage output circuit 10 of this embodiment.

  Therefore, in the voltage output circuit 30 of the comparative example, it is necessary to prevent the output MOS transistor 13 from being damaged and destroyed by the heat generated by the ground fault current Idr2 between time t2 and time t4. Therefore, the chip size of the output MOS transistor 13 becomes larger.

  On the other hand, in the voltage output circuit 10 of the present embodiment, the ground fault current Idr is suppressed to Idr1 smaller than Idr2, so that the chip size of the output MOS transistor 13 can be further reduced.

  As described above, the voltage output circuit 10 of this embodiment reduces the current flowing through the output MOS transistor 13 when the potential difference ΔV (Vds1) between the voltage input terminal 12 and the voltage output terminal 11 is larger than the reference value. Thus, the current limiting means 22 for controlling the potential Vn1 of the first node is provided.

  As a result, it is possible to suppress the ground fault current Idr by applying local feedback during the period from when the ground fault occurs until the output MOS transistor 13 is turned off. Therefore, it is possible to obtain a voltage output circuit capable of suppressing the ground fault current from when the ground fault is detected until the output transistor is turned off.

  Here, the case where the voltage output circuit is a PWM control switching regulator has been described, but other voltage output circuits having an output MOS transistor, for example, a series regulator, can be similarly implemented.

  Although the case where the first and second conductivity types are P-type and N-type has been described, it may be N-type and P-type, respectively.

  Although the case where the first and second reference voltages Vref1 and Vref2 are equal has been described, it may not be particularly equal. When the first and second reference voltages Vref1 and Vref2 are not equal, there is a shift in the timing at which the first and second comparators 20 and 23 are inverted. However, the ground fault is an instantaneous phenomenon, and this timing shift does not cause any trouble in the operation of the voltage output circuit 10.

  Since the first and second comparators 20 and 23 basically operate at the same timing, they can be combined into one comparator. The output control circuit 16 and the PMOS transistor 25 may be commonly connected to the comparator output terminal directly or via a buffer or the like.

  A voltage output circuit according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 5 is a circuit diagram showing the voltage output circuit of this embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The present embodiment is different from the first embodiment in that ground fault detection is performed with current.

  That is, as shown in FIG. 5, in the voltage output circuit 40 of this embodiment, when the current limiting means 41 detects the current Idr flowing through the output MOS transistor 13, and the current Idr is larger than the reference value, the first node The current Idr flowing in the output MOS transistor 13 is reduced by controlling the potential Vn1 of N1.

  The current limiting means 41 is connected between the voltage input terminal 11 and the voltage output terminal 12. The current limiting means 41 includes a current mirror circuit 42, a PMOS transistor (third insulated gate field effect transistor) 43, a resistor R2, and a PMOS transistor (fourth insulated gate field effect transistor) 44.

  The current mirror circuit 42 includes a pair of N-channel (second conductivity type) MOS transistors 45 and 46 whose gate electrodes are connected to each other. The gate electrode of the NMOS transistor 45 is connected to the drain electrode.

  The PMOS transistor 43 is connected between the voltage input terminal 12 and the current input terminal 42a of the current mirror circuit 42, and has a gate electrode connected to the first node N1. The threshold value of the PMOS transistor 43 is set equal to the threshold value of the output MOS transistor 13.

  The ratio (W / L) between the gate width W and the gate length L of the PMOS transistor 43 is smaller than the ratio (W / L) between the gate width W and the gate length L of the output MOS transistor 13, and is set to, for example, 1: 1000. Yes.

  The resistor R2 is connected between the voltage input terminal 11 and the second node N2. The PMOS transistor 44 is connected between the voltage input terminal 12 and the first node N1, and has a gate electrode connected to the second node N2.

  The current mirror circuit 42 is turned off when the potential difference ΔV (Vds1) is smaller than the sum of the operating voltage of the PMOS transistor 43 and the operating voltage of the NMOS transistor 45, and is turned on when it is larger. have.

  This is to reduce the power consumed by the voltage limiting circuit 41 by turning off the current mirror circuit 42 when the voltage output circuit 40 is in a normal operation.

  When the current mirror circuit 42 is on, a current I1 proportional to the current Idr flowing through the output MOS transistor 13 flows through the PMOS transistor 43. The current ratio is 1: 1000 as described above. The PMOS transistor 43 detects the current Idr flowing through the output MOS transistor 13. The PMOS transistor 43 functions as a so-called current detection transistor.

  A current I2 equal to the current I1 flowing through the NMOS transistor 45 flows through the NMOS transistor 46 of the current mirror circuit 42. Due to the voltage drop (I2 × R2) due to the current I2 flowing through the resistor R2, the potential Vn2 of the second node N2 drops from Vin to Vin−I2 × R2. As a result, the gate voltage Vgs2 of the PMOS transistor 44 is raised from 0 to I2 × R2.

  When a ground fault occurs, the current mirror circuit 42 is on. When the current I2 increases in proportion to the rise of the ground fault current Idr and the gate voltage Vgs2 becomes larger than the threshold value of the PMOS transistor 44, the PMOS transistor 44 is turned on. The PMOS transistor 44 functions as a so-called output transistor.

  When the operating voltage Vds2 of the PMOS transistor 44 is set to a value smaller than 5V, for example, 3V, the potential Vn1 of the first node N1 is raised from Vin-5V to Vin-3V. As a result, the gate voltage Vgs1 of the output MOS transistor 13 is lowered from 5V to 3V, so that the ground fault current Idr can be suppressed.

  The operation of the voltage output circuit 40 is basically the same as the timing chart shown in FIG.

  As described above, the current limiting means 41 in the voltage output circuit 40 of this embodiment detects the current Idr flowing through the output MOS transistor 13, and when the current Idr is larger than the reference value, the potential of the first node N1. The current Idr flowing through the output MOS transistor 13 is reduced by controlling Vn1.

  Since the circuit configuration of the current limiting unit 41 is simpler than that of the second comparator 23, an advantage that it can be easily implemented is obtained.

  A voltage output circuit according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 6 is a circuit diagram showing the main part of the voltage output circuit of this embodiment. In the present embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. This embodiment is different from the second embodiment in that damage to the output transistor in the current limiting circuit is prevented.

  That is, as shown in FIG. 6, in the current limiting circuit 51 in the voltage output circuit 50 of this embodiment, the Zener diode 52 is connected in the reverse direction between the voltage input terminal 11 and the second node N2. In other words, the Zener diode 52 is connected in parallel to the resistor R2.

  When the voltage drop amount I2 × R2 of the resistor R2 becomes larger than the Zener voltage Vz of the Zener diode 52, the Zener diode 52 breaks down, and the potential Vn2 of the second node N2 is clamped to Vin−Vz by the Zener diode 52.

  As a result, the gate voltage Vgs2 of the PMOS transistor 44 is suppressed to the Zener voltage Vz at the maximum. Therefore, even if the voltage drop amount I2 × R2 of the resistor R2 becomes excessive due to the ground fault current Idr, the PMOS transistor 44 can be prevented from being damaged.

  As described above, in the current limiting circuit 51 in the voltage output circuit 50 of the present embodiment, the Zener diode 52 is connected in parallel to the resistor R2, so that the output MOS transistor 13 is turned off by the ground fault current Idr. There is an advantage that the PMOS transistor 44 can be prevented from being damaged.

  The above-described embodiments are merely exemplary and are not intended to limit the scope of the invention. Indeed, the novel voltage output circuit described herein may be embodied in various other forms, and further in the form of the voltage output circuit described herein without departing from the spirit or spirit of the invention. Various omissions, substitutions and changes may be made. The appended claims and their equivalents are intended to include such forms or modifications as would fall within the scope and spirit or spirit of the present invention.

The present invention can be configured as described in the following supplementary notes.
(Appendix 1)
The drive circuit is
An insulated gate field effect transistor of a first conductivity type connected between the voltage input terminal and the first node and having a gate electrode connected to the input node;
An insulated gate field effect transistor of a second conductivity type, connected via a resistor between the first node and a power supply having a potential lower than that of the voltage input terminal, and having a gate electrode connected to the input node;
The voltage output circuit according to claim 1, comprising:

(Supplementary note 2) The voltage output circuit according to supplementary note 1, wherein a potential difference between the voltage input terminal and the intermediate voltage source is larger than a threshold value of the first insulated gate field effect transistor.

10, 30, 40, 50 Voltage output circuit 11 Voltage input terminal 12 Voltage output terminal 13 Output MOS transistor 14 High potential line 15 Low potential line 16 Output control circuit 17 Drive circuits 18, 25, 43, 44 PMOS transistors 19, 45, 46 NMOS transistor 20 first comparator 21 first voltage source 22, 41, 51 current limiting means 23 second comparator 24 second voltage source 42 current mirror circuit 42a current input terminal 42b current output terminal 42c common terminal 52 Zener diode N1 first Node N2 Second node Nin Input node R1, R2 Resistance I1 Input current I2 Output current Vref1 First reference voltage Vref2 Second reference voltage

Claims (5)

A first insulated gate field effect transistor of a first conductivity type connected between the voltage input terminal and the voltage output terminal and having a gate electrode connected to the first node;
A drive circuit that outputs to the first node a control signal that controls conduction of the first insulated gate field effect transistor in response to an input signal supplied to the input node;
The current flowing through the first insulated gate field effect transistor is reduced when the potential difference between the voltage input terminal and the voltage output terminal is greater than a reference value, and is connected between the voltage input terminal and the voltage output terminal. Current limiting means for controlling the potential of the first node;
A voltage output circuit comprising: A first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is connected to the voltage input terminal via a first voltage source that generates a first reference voltage according to the reference value; A first comparator that connects the second input terminal to the voltage output terminal, compares a potential difference between the voltage input terminal and the voltage output terminal with the first reference voltage, and outputs a comparison result to the output terminal;
An output control circuit which is connected between the output terminal and the input node and outputs a signal for turning off the first insulated gate field effect transistor as the input signal to the input node according to a comparison result of the comparator When,
The voltage output circuit according to claim 1, further comprising: The current limiting means includes
A first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is connected to the voltage input terminal via a second voltage source that generates a second reference voltage according to the reference value; A second comparator connected to the voltage output terminal, comparing a potential difference between the voltage input terminal and the voltage output terminal with the second reference voltage, and outputting a comparison result to the output terminal;
A second insulated gate field effect transistor of a first conductivity type connected between the voltage input terminal and the first node and having a gate electrode connected to the output terminal;
The voltage output circuit according to claim 1, further comprising: The current limiting means includes
A second input type having a current input terminal, a current output terminal, and a common terminal, wherein the current output terminal is connected to a second node, the common terminal is connected to the voltage output terminal, and gate electrodes are connected to each other; A current mirror circuit composed of third and fourth insulated gate field effect transistors;
A resistor connected between the voltage input terminal and the second node;
A fifth insulated gate field effect transistor of a first conductivity type connected between the voltage input terminal and the current input terminal and having a gate electrode connected to the first node;
A sixth insulated gate field effect transistor of a first conductivity type connected between the voltage input terminal and the first node and having a gate electrode connected to the second node;
The voltage output circuit according to claim 1, further comprising:   The voltage output circuit according to claim 4, wherein a Zener diode is connected between the voltage input terminal and the second node.

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