JP2012015158A - Wiring board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board whose front and back faces are easy to be discriminated from each other.SOLUTION: The wiring board comprises a first insulation layer 20 formed on one face side as an outermost layer, a first connection pad P1 formed to expose from the first insulation layer 20, a second insulation layer 26 formed on another face side as an uppermost layer and having a color different from that of the first insulation layer 20, and a second connection pad P2 formed to expose from the second insulation layer 26. One of the first insulation layer 20 and the second insulation layer 26 is see-through and the other is non-see-through. Preferably, the wiring board is a coreless type, an outer face of the first connection pad P1 exposes from an outer face of the first insulation layer 20, side faces and an opposite face of the outer face are in contact with the first insulation layer 20, and a semiconductor chip 50 is mounted on the first connection pad P1.

Description

  The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board including a connection pad and an insulating layer provided so as to expose the connection pads on both sides, and a manufacturing method thereof.

  Conventionally, there are multilayer wiring boards for mounting semiconductor chips. In the multilayer wiring board, a chip connection pad for mounting a semiconductor chip is provided on one surface, and an external connection pad for connecting an external connection terminal is provided on the other surface.

  In Patent Document 1, a conductor wiring and an insulating layer are sequentially formed on a metal plate from the semiconductor element mounting surface side to the external connection terminal mounting surface, and then the metal plate is removed without using a core substrate. It describes that a multilayer wiring is formed to obtain a flat semiconductor element mounting surface.

JP 2000-323613 A

  As will be described later, in the related art wiring board, when there is no large difference in diameter and arrangement pitch between the chip connection pad on one surface side and the external connection pad on the other surface side, the pattern on the front and back surfaces Since the difference in pattern is not clear, it is difficult for a human to distinguish between the chip mounting surface and the external connection surface by visual observation.

  Also, in recognition by an image recognition device, problems such as a decrease in recognition speed and a decrease in recognition accuracy tend to occur.

  The present invention has been created in view of the above problems, and an object of the present invention is to provide a wiring board capable of easily identifying the front and back surfaces and a manufacturing method thereof.

  In order to solve the above problems, the present invention relates to a wiring board, a first insulating layer formed as an outermost layer on one surface side, a first connection pad formed exposed from the first insulating layer, A second insulating layer formed as an outermost layer on the other surface side and exhibiting a color different from the color of the first insulating layer; and a second connection pad formed exposed from the second insulating layer, One of the first insulating layer and the second insulating layer is transparent, and the other is opaque.

  In the wiring board of the present invention, one of the first and second insulating layers formed on the outermost surfaces on both sides is opaque, the other is transparent, and the first insulating layer and the second insulating layer The insulating layers have different colors. For this reason, it is possible to easily recognize and identify the front and back surfaces by visualizing the colors of the front and back surfaces of the wiring board in advance.

  In one preferred aspect of the present invention, the wiring board is a coreless wiring board having no core board, the outer surface of the first connection pad is exposed from the outer surface of the first insulating layer, and the side surface of the first connection pad. And a surface opposite to the outer surface are in contact with the first insulating layer, a connection hole is formed in the second insulating layer, and the second connection pad is exposed at the bottom of the connection hole.

  In order to manufacture such a coreless wiring substrate, first, a first connection pad is formed on a support, and a first insulating layer covering the first connection pad is formed. Further, the first insulating layer is processed to form a via hole reaching the first connection pad. Next, a predetermined build-up wiring connected to the first connection pad through the via hole and including the second connection pad as the uppermost layer is formed on the first wiring layer.

  Further, a second insulating layer having a color different from that of the first insulating layer is formed on the second connection pad. Thereafter, a connection hole is formed in the second insulating layer on the second connection pad by photolithography or laser. When the first insulating layer is made opaque and the second insulating layer is made transparent, since the second insulating layer has transparency, the alignment mark therebelow can be recognized stably, so that the second connection The connection holes are accurately aligned on the pads.

  Next, the support is removed to expose the first connection pads. When a semiconductor chip is mounted on the first connection pad, an opaque first insulating layer is disposed around an alignment mark formed from the same layer as the first connection pad. For this reason, since the image of the alignment mark can be recognized with a good contrast, the semiconductor chip can be accurately aligned with the wiring board and mounted.

  In addition to the above-described structure, the insulating layer on the surface side where adhesion of foreign matters is a problem may be made transparent, and the insulating layer on the opposite surface may be made opaque. In this aspect, since the foreign matter (dark color or black color) attached on the transparent insulating layer can be easily detected and removed by the image recognition apparatus, the semiconductor chip or the external connection terminal can be reliably connected to the connection pad. it can.

  As described above, by applying the present invention to the coreless wiring board in particular, not only the front and back surfaces can be easily identified, but also a structure convenient for the manufacturing process, when mounting the semiconductor chip, or for detecting foreign matter.

  As described above, the wiring board of the present invention can easily identify the front and back surfaces without providing a special recognition pattern.

FIGS. 1A to 1C are cross-sectional views for explaining problems of the related art wiring board. 2A to 2D are sectional views (No. 1) showing the method for manufacturing the wiring board according to the first embodiment of the present invention. FIGS. 3A to 3D are sectional views (No. 2) showing the method for manufacturing the wiring board according to the first embodiment of the present invention. 4A to 4C are cross-sectional views (part 3) illustrating the method for manufacturing the wiring board according to the first embodiment of the present invention. 5A to 5C are cross-sectional views (part 4) showing the method for manufacturing the wiring board according to the first embodiment of the present invention. FIG. 6 is a sectional view (No. 5) showing the method for manufacturing the wiring board according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the wiring board according to the first embodiment of the present invention. 8A to 8C are cross-sectional views showing a method of mounting a semiconductor chip on the wiring board of FIG. FIG. 9 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of FIG. FIG. 10 is a sectional view showing a wiring board according to the second embodiment of the present invention. 11 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of FIG. 12A and 12B are cross-sectional views illustrating a method for manufacturing a wiring board according to a third embodiment of the present invention. FIG. 13 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of FIG. FIG. 14 is a sectional view showing a wiring board according to a fourth embodiment of the present invention. 15 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(Related technology)
Prior to describing embodiments of the present invention, related techniques related to the present invention will be described. FIG. 1 is a cross-sectional view showing a wiring board according to related art.

  As shown in FIG. 1A, in the related art wiring board, the chip mounting surface A on the upper surface side of the multilayer wiring portion 200 is provided with a chip connection pad P1 and an opening 300a for exposing the chip connecting pad P1. A resist 300 is formed. Further, the external connection surface B on the lower surface side of the multilayer wiring part 200 is formed with an external connection pad P2 and a solder resist 300 provided with an opening 300a exposing the pad.

  The chip connection pad P1 is an electrode for connecting a semiconductor chip, and the external connection pad P2 is an electrode for connecting an external connection terminal.

  When the semiconductor chip is flip-chip connected to the chip connection pad P1 of the wiring board, it is necessary for a human to identify and specify the chip mounting surface A of the wiring board by visual inspection.

  When the diameter and arrangement pitch of the external connection pads P1 are considerably larger than the chip connection pads P1 as in the wiring board of FIG. 1A, a human can easily identify the chip mounting surface A by visual inspection. Can be identified.

  As shown in FIG. 1B, in recent years, the density of wiring boards has been further increased, and there is no significant difference in diameter and arrangement pitch between the chip connection pads P1 and the external connection pads P1. is there. In such a wiring board, the difference between the pattern patterns on the front and back surfaces is not clear, so that it is difficult for a human to distinguish between the chip mounting surface A and the external connection surface B by visual observation.

  Also, in recognition by an image recognition device, problems such as a decrease in recognition speed and a decrease in recognition accuracy are likely to occur.

  As a countermeasure against this, as shown in FIG. 1C, the front and back identification pattern DP is specially arranged on the chip mounting surface A of the wiring board, so that the surface side where the front and back identification pattern DP exists is the chip mounting surface A. It makes it possible to identify something.

  In this case, since it is necessary to additionally lay out the front / back identification pattern DP, there may be a burden on the design of the wiring board, which may increase the cost. For this reason, the technique which can identify the front and back of a wiring board easily, without using the pattern DP for front and back identification is desired.

  As a result of earnest research on the above problems, the inventor of the present application uses a color insulating layer having characteristics suitable for each surface on the chip mounting surface and the external connection surface of the wiring board, and identifies the front and back surfaces by the difference in color. A circuit board with a new structure was devised.

(First embodiment)
2 to 6 are cross-sectional views showing a method for manufacturing a wiring board according to the first embodiment of the present invention, and FIG. 7 is a cross-sectional view showing the wiring board according to the first embodiment.

  In the first embodiment, an embodiment in which the colors of the protective insulating layers (solder resists) on both sides of the coreless wiring substrate having no core substrate are set to different colors will be described with reference to the manufacturing method.

  As shown in FIG. 2A, first, a support 5 made of a metal plate or metal foil such as copper (Cu) is prepared. The support 5 is a temporary substrate and is removed after the build-up wiring is formed on the support 5.

  Next, as shown in FIG. 2 (b), a plating resist 6 having an opening 6 a provided in a portion where the chip connection pad is disposed is formed on the support 5. Further, as shown in FIG. 2C, the gold (Au) layer 10a and the nickel (Au) are formed on the support 5 in the opening 6a of the plating resist 6 by electrolytic plating using the support 5 as a plating power feeding path. The Ni) layer 10b is formed in order. Thereafter, the plating resist 6 is removed.

  Thereby, as shown in FIG. 2D, a chip connection pad P1 (first connection pad) composed of the Au layer 10a and the Ni layer 10b is formed on the support 5. The chip connection pad P1 is an electrode to which a semiconductor chip is connected.

  Alternatively, a gold (Au) layer / nickel (Ni) layer / copper (Cu) layer, gold (Au) layer / palladium (Pa) layer / nickel (Ni) layer, or gold (in order from the bottom on the support 5) Various laminated films such as Au) layer / palladium (Pa) layer / nickel (Ni) layer / copper (Cu) layer may be formed as the chip connection pad P1.

  Alternatively, a nickel (Ni) layer (sacrificial layer) / copper (Cu) layer may be formed on the support 5 in order from the bottom as the chip connection pad P1. In this case, as described later, after the support 5 is removed, the nickel (Ni) layer (sacrificial layer) is removed with an etching solution capable of selectively etching nickel, and the chip connection pad P1 is a copper (Cu) layer. Formed only from.

  Next, as shown in FIG. 3A, the first protective insulating layer 20 is formed on the chip connection pad P1. As will be described later, the support 5 is removed after the build-up wiring is formed thereon. As a result, the chip connection pad P1 and the first protective insulating layer 20 are exposed on the chip mounting surface, and the first protective insulating layer 20 functions as a solder resist.

  Then, based on the image recognition of the alignment mark formed from the same layer as the chip connection pad P1, the semiconductor chip is aligned with the wiring substrate and is flip-chip connected to the chip connection pad P1. At this time, in a state in which the lower wiring layer can be seen through from the outer surface side through the first protective insulating layer 20, the image tends to become unclear, and it may be difficult to perform highly accurate alignment.

  As a countermeasure against this, the first protective insulating layer 20 is formed of an insulating layer having an opaqueness. As the non-transparent insulating layer, an insulating layer exhibiting purple (wavelength of reflected visible light: 380 to 450 nm), blue (wavelength of reflected visible light: 450 to 495 nm), black, or gray is used.

  In the case where an insulating layer exhibiting black or gray is used as the first protective insulating layer 20, one having a light absorption rate of visible light having a wavelength of 380 to 780 nm of 60% or more (preferably 70% or more) to 100%. used. When the light absorption rate is 60% or more and less than 70%, it is visually recognized as gray (or dark gray), and when the light absorption rate is 70% or more, it is visually recognized as black.

  The first protective insulating layer 20 having an opaqueness is formed by laminating a resin film containing the above-described opaque pigments on a thermosetting resin such as epoxy or polyimide, and heating and applying with a vacuum press device or the like. Obtained by pressing. Alternatively, a liquid thermosetting resin such as epoxy or polyimide containing a pigment of each color may be applied and cured by heating.

  The content of the pigment in the resin is 0.01 to 20% by mass, preferably 0.1 to 10% by mass.

  The insulating layer having non-permeability means a layer that cannot be seen through by a general image recognition apparatus or a normal human eye in a bright environment and cannot recognize the underlying layer.

  Specifically, this means that the color of the underlying wiring layer cannot be seen through through the first protective insulating layer 20 having transparency. The underlying wiring layer is made of copper or a copper alloy, and exhibits a color with a wavelength of visible light reflected from 580 to 800 nm.

  The image recognition apparatus described above is an apparatus that performs image recognition by imaging light beams having a wavelength in the visible light region with various image pickup devices such as a CCD camera.

  Subsequently, as shown in FIG. 3B, the first protective insulating layer 20 is processed with a laser to form a first via hole VH1 reaching the chip connection pad P1. Further, as shown in FIG. 3C, a first wiring layer 30 connected to the chip connection pad P1 through the first via hole VH1 (via conductor) is formed.

  The first wiring layer 30 is formed by, for example, a semi-additive method. More specifically, first, a seed layer (not shown) made of copper or the like is formed on the first protective insulating layer 20 and in the first via hole VH1 by electroless plating or sputtering. Subsequently, a plating resist (not shown) in which an opening is provided in a portion where the first wiring layer 30 is disposed is formed on the seed layer.

  Further, a metal pattern layer (not shown) such as copper is formed in the opening of the plating resist by electrolytic plating using the seed layer as a plating power feeding path. Next, after removing the plating resist, the first wiring layer 30 including the seed layer and the metal pattern layer is obtained by etching the seed layer using the metal pattern layer as a mask.

  Next, as shown in FIG. 3D, the first interlayer insulating layer 22 is formed on the first wiring layer 30. The first interlayer insulating layer 22 does not need to be formed from an opaque color insulating layer, and is formed from a normal epoxy resin or polyimide resin. The first interlayer insulating layer 22 is formed by laminating resin films and heating and pressing with a vacuum press apparatus or the like.

  After that, the second via hole VH2 reaching the first wiring layer 30 is formed by processing the first interlayer insulating layer 22 with a laser.

  Subsequently, as shown in FIG. 4A, the second wiring connected to the first wiring layer 30 through the second via hole VH2 (via conductor) by the same method as the method of forming the first wiring layer 30. A layer 32 is formed on the first interlayer insulating layer 22.

  Further, as shown in FIG. 4B, by repeating the same process, the second interlayer insulating layer 24 provided with the third via hole VH3 reaching the second wiring layer 32 is formed on the first interlayer insulating layer 22. Form on top. Similar to the first interlayer insulating layer 22, the second interlayer insulating layer 24 does not need to be formed from an opaque color insulating layer, and is formed from a normal epoxy resin or polyimide resin.

  Thereafter, the external connection pad P2 (second connection pad) connected to the second wiring layer 32 through the third via hole VH3 (via conductor) is formed by the same method as the method for forming the first wiring layer 30. Three wiring layers are formed on the second interlayer insulating layer 24. The external connection pad P2 may be arranged in an island shape on the third via hole VH3, or may be connected to one end of a wiring extending outward from the third via hole VH3.

  As a result, three layers of build-up wiring (first wiring layer 30, second wiring layer 32 and external connection pad P2) connected to the chip connection pad P1 through the first via hole VH1 (via conductor) are formed. Is done.

  Next, as shown in FIG. 4C, a photosensitive resin layer 26a is formed on the external connection pad P2. The photosensitive resin layer 26a is a resin material that is patterned by photolithography.

  Then, as shown in FIG. 5A, a photomask 40 for forming connection holes in the photosensitive resin layer 26a on the external connection pads P2 is prepared. The photomask 40 includes a light transmitting portion 40a and a light shielding pattern 40b. Further, the photomask 40 is arranged and aligned above the structure shown in FIG.

  At this time, as shown in the partially enlarged cross-sectional view of FIG. 5B, when the alignment of the photomask 40 is performed, the alignment mark M existing under the photosensitive resin layer 26a is image-recognized. Based on. The alignment marks M are formed from the same layer as the external connection pads P2. For example, when a plurality of chip mounting areas are defined, they are respectively arranged at the four corners.

  Thus, in order to align the photomask 40 when patterning the photosensitive resin layer 26a by photolithography, it is necessary to see through the photosensitive resin layer 26a and to recognize an image of the alignment mark M below it. There is. The alignment mark M is formed simultaneously with the external connection pad P2 and is made of copper or a copper alloy.

  For this reason, a transparent insulating layer is used as the photosensitive resin layer 26a. As the transparent insulating layer, green (wavelength of reflected visible light: 495-570 nm), yellow (wavelength of reflected visible light: 570-590 nm), orange (wavelength of reflected visible light: 590-620 nm), An insulating layer exhibiting red (wavelength of reflected visible light: 620 to 750 nm) or white is used.

  The insulating layer having transparency means a layer that can be seen through by a general image recognition device or a normal human eye in a bright environment and can clearly recognize the underlying layer. Specifically, the base layer is a wiring layer (external connection pad P2) or alignment mark M made of copper or a copper alloy whose reflected visible light has a wavelength of 580 to 800 nm.

  The transparent photosensitive resin layer 26a is obtained by applying a resin film containing the above-described transparent pigments to a photosensitive thermosetting resin such as epoxy or polyimide, or applying a liquid resin. It is formed.

  Since the photosensitive resin layer 26a is transparent, the photosensitive resin layer 26a can be seen through and the alignment mark M below it can be clearly recognized, so that highly accurate alignment can be performed stably. it can. Then, after the photosensitive resin layer 26a is exposed through the photomask 40, development is performed. Thereafter, the photosensitive resin layer 26a is cured by heat treatment.

  Thereby, as shown in FIG. 6, the second protective insulating layer 26 in which the connection hole CH is provided on the external connection pad P <b> 2 is formed on the second interlayer insulating layer 24. The second protective insulating layer 26 functions as a solder resist.

  In addition, although the negative photosensitive resin layer 26a was illustrated, a positive photosensitive resin layer may be used. Specifically, it is formed by attaching a resin film containing a pigment to an epoxy resin or polyimide resin having the same composition as the interlayer insulating layer, or by applying a liquid resin. In this case, the black and white (the translucent portion 40a and the light shielding pattern 40b) of the photomask 40 are arranged in reverse.

  Alternatively, as shown in FIG. 5 (c), a non-photosensitive resin layer 26b is formed on the external connection pad P2, and the non-photosensitive resin layer 26b is processed with a laser, thereby forming the external connection pad P2. A connection hole CH (FIG. 6) may be formed thereon.

  Similarly, when using a laser, alignment is performed on the basis of the fact that the non-photosensitive resin layer 26b is seen through and the alignment mark M described with reference to FIG. Therefore, as in the case of using photolithography, the above-described non-photosensitive resin having a color having transparency is used.

  Further, the connection hole CH may be formed in the second protective insulating layer 26 by blasting. In this case, a resist having an opening pattern is formed on the non-photosensitive resin layer 26b in FIG. 5C, and the non-photosensitive resin layer 26b is ground by blasting through the opening pattern to connect the connection hole CH. Form. Thereafter, the resist is removed.

  In blasting, grinding is performed by dispersing a polishing agent made of alumina abrasive grains or silica abrasive grains in a solvent such as water and injecting the non-photosensitive resin layer 26b at a high pressure.

  Thereafter, in FIG. 6, as necessary, a contact layer (not shown) is formed on the external connection pad P1 by, for example, sequentially forming a nickel (Ni) layer / gold (Au) layer by electroless plating. As the contact layer, a nickel (Ni) layer / palladium (Pa) layer / gold (Au layer) may be laminated in order from the bottom, or various laminated films formed by plating may be employed. .

  At this time, the first protective insulating layer 20 and the second protective insulating layer 26 described above exhibit different colors.

  Next, the support 5 is removed from the structure of FIG. 6 by wet etching, so that the chip connection pads P1 and the first protective insulating layer 20 are exposed. When the support 5 is made of copper, a copper etchant such as a cupric chloride aqueous solution is used. The support 5 is removed by being selectively etched with respect to the chip connection pad P1 (the lowermost layer is the Au layer 10a) and the first protective insulating layer 20.

  As described above, the wiring board 1 of the first embodiment is obtained as shown in FIG.

  As shown in FIG. 7, the wiring board 1 of the first embodiment is a coreless wiring board having no core board, and three layers of build-up wiring (first and second wiring layers 30) are provided on the chip connection pad P1. 32, external connection pads P2). A first protective insulating layer 20 and a second protective insulating layer 26 are formed as solder resists on the outermost sides of both sides.

  The chip connection pad P <b> 1 (first connection pad) is exposed from the first protective insulating layer 20 because its outer surface forms the same surface as the outer surface of the first protective insulating layer 20. That is, the side surface of the chip connection pad P1 and the via connection surface (the surface on the first via hole VH1 side) are in contact with the first protective insulating layer 20, and the outer surface (the surface opposite to the via connection surface) is from the first protective insulating layer 20. Exposed.

  Alternatively, as described above, after the nickel (Ni) layer (sacrificial layer) / copper (Cu) layer is formed as the chip connection pad P1 and the support 5 is removed in the step of FIG. When the layer (sacrificial layer) is removed, the chip connection pad P1 is formed only from the copper layer.

  In this case, the outer surface of the chip connection pad P <b> 1 is disposed at a position recessed inward from the outer surface of the first protective insulating layer 20 and is exposed from the first protective insulating layer 20.

  A connection hole CH formed in the second protective insulating layer 26 is disposed on the external connection pad P2 (second connection pad). The peripheral edge of the external connection pad P2 is covered with the second protective insulating layer 26, and the central part of the external connection pad P2 is exposed from the connection hole CH.

  The first to third via holes VH1, VH2, and VH3 formed in the first protective insulating layer 20 and the first and second interlayer insulating layers 22 and 24 are opened to the second protective insulating layer 26 side.

  In addition, the first to third via holes VH1, VH2, and VH3 have bottom surfaces formed by the chip connection pads P1 (first connection pads) and the surfaces of the first and second wiring layers 30 and 32. The opening area is formed as a frustoconical recess that is larger than the bottom area. A via conductor is formed (filled) in the first to third via holes VH1, VH2, and VH3.

  Note that the connection pads (chip connection pad P1 and external connection pad P2) are exposed from the protective insulating layers 20 and 26. That is, the surface of each connection pad is not covered with the protective insulating layers 20 and 26. Means. Therefore, a structure in which the connection pads (chip connection pads P1 and external connection pads P2) are covered with a semiconductor chip or external connection terminals is also included.

  The surface of the wiring board 1 on which the chip connection pads P1 are provided is a chip mounting surface A. Further, the surface of the wiring board 1 on which the external connection pads P2 are provided is an external connection surface B.

  Further, the first protective insulating layer 20 provided on the chip mounting surface A is formed of an insulating layer having an opaqueness. As described above, an insulating layer exhibiting purple, blue, black, or gray is used as the insulating layer having non-permeability.

  The second protective insulating layer 26 provided on the external connection surface B is formed of a transparent insulating layer. As described above, an insulating layer exhibiting green, yellow, orange, red, or white is used as the transparent insulating layer.

  As described above, the first protective insulating layer 20 on the chip mounting surface A and the second protective insulating layer 26 on the external connection surface B exhibit different colors, and the first protective insulating layer 20 is opaque. And the second protective insulating layer 26 has transparency.

  In the wiring substrate 1 of the first embodiment, the diameter and arrangement pitch of the chip connection pads P1 are not significantly different from the external connection pads P2, and therefore the pattern pattern is similar between the chip mounting surface A and the external connection surface B. is doing.

  In the present embodiment, even in such a wiring board 1, by arranging the colors of the chip mounting surface A and the external connection surface B in different colors in advance, a semiconductor chip is placed on the chip mounting surface A of the wiring board 1. At the time of mounting, the chip mounting surface A can be easily specified by the human visually identifying the color.

  For example, when the first protective insulating layer 20 on the chip mounting surface A is set to blue and the second protective insulating layer 26 on the external connection surface B is set to red, the chip mounting surface A is connected between the chip mounting surface A and the external connection surface B. Even if the pattern patterns are similar, it can be easily seen that the blue surface is the chip mounting surface A.

  Furthermore, since the front and back surfaces of the wiring substrate 1 of the first embodiment exhibit different colors, even when the front and back surfaces are identified by the image recognition device, complicated image processing is not required, and accurate front and back recognition is possible. And recognition speed can be improved.

  Next, a method for mounting a semiconductor chip on the wiring board 1 of the first embodiment will be described.

  As shown in FIG. 8A, the chip mounting surface A of the wiring board 1 of FIG. 7 is specified by the above-described method, and the wiring board 1 is turned upside down so that the chip connection pad P1 faces upward.

  Next, as shown in FIG. 8B, a semiconductor chip 50 provided with connection electrodes 50 a is prepared, and solder (not shown) is applied onto the chip connection pads P <b> 1 of the wiring substrate 1.

  Subsequently, as shown in FIG. 8C, the semiconductor chip 50 is aligned with the wiring substrate 1 based on the image recognition of the alignment mark M formed from the same layer as the chip connection pad P1. At this time, as described above, since the first protective insulating layer 20 has non-permeability, the first wiring layer 30 below the chip connection pad P1 is not seen through and image recognition is not performed. The image of the alignment mark M has a good contrast, and the semiconductor chip 50 can be aligned with the wiring substrate 1 with high accuracy.

  In this way, as shown in FIG. 8B, the connection electrodes 50a of the semiconductor chip 50 are arranged in alignment with the solder on the chip connection pads P1 of the wiring board 1, and are soldered by heat treatment. . As a result, as shown in FIG. 9, the semiconductor chip 50 is flip-chip connected to the chip connection pads P <b> 1 of the wiring substrate 1 by the bump electrodes 52. Thereafter, the underfill resin 54 is filled in the lower gap of the semiconductor chip 50.

  Further, external connection terminals 60 are provided by mounting solder balls on the external connection pads P2 on the lower surface side of the wiring board 1. Thereby, a semiconductor package is configured.

  Although a BGA type semiconductor package is illustrated in FIG. 9, a connection pin may be connected to the external connection pad P2 as an external connection terminal to form a PGA type package. Alternatively, when configuring an LGA type package, the external connection pad P2 itself is used as an external connection terminal.

  As described above, in the wiring substrate 1 of the first embodiment, the first protective insulating layer 20 on the chip mounting surface A has a non-transparent property, and the second protective insulating layer 26 on the external connection surface B has a transparent property. The first protective insulating layer 20 and the second protective insulating layer 26 have different colors. Since the colors are clearly different on both sides of the wiring substrate 1, the chip mounting surface A of the wiring substrate 1 can be easily identified and identified visually.

  Moreover, as described above, the first protective insulating layer 20 is made opaque and the second protective insulating layer 26 is made transparent when the coreless type wiring substrate 1 is manufactured and the semiconductor chip 50 is mounted. This is a convenient structure.

  That is, when the connection hole CH is formed in the second protective insulating layer 26 on the external connection pad P2 by photolithography or laser, the alignment mark M below the second protective insulating layer 26 can be easily seen through. Image recognition is possible. Thereby, the connection hole CH can be accurately aligned and formed on the external connection pad P2.

  Further, when the semiconductor chip 50 is mounted on the chip connection pad P1, the opaque first protective insulating layer 20 exists around the alignment mark M. Thereby, since the contrast of the image of the alignment mark M becomes favorable, the semiconductor chip 50 can be aligned and mounted on the wiring substrate 1 with high accuracy and stability.

(Second Embodiment)
FIG. 10 is a cross-sectional view showing a wiring board according to a second embodiment of the present invention, and FIG. 11 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of FIG.

  In the first embodiment described above, the first protective insulating layer 20 on the chip mounting surface A is made opaque so that it is convenient when manufacturing the coreless type wiring substrate 1 and mounting the semiconductor chip 50. The second protective insulating layer 26 on the external connection surface B is made transparent so that the colors are different from each other.

  Without being limited to this form, as shown in FIG. 10, in the wiring board 1a of the second embodiment, the arrangement of the chip connection pads P1 and the external connection pads P2 in FIG. The upper side is the chip mounting surface A and the lower side is the external connection surface B.

  That is, the external connection pad P2 (first connection pad) is exposed from the first non-transparent protective insulating layer 20 on the lower surface side, and the chip connection pad P1 (first connection pad P1) is exposed from the second transparent protective insulating layer 26 on the upper surface side. The second connection pad) is exposed.

  The side surface of the external connection pad P2 and the via connection surface (the surface on the first via hole VH1 side) are in contact with the opaque first protective insulating layer 20, and the outer surface (the surface opposite to the via connection surface) is the first protective insulating layer. 20 is exposed. The transparent second protective insulating layer 26 is provided with a connection hole CH, and the center portion of the chip connection pad P1 is exposed from the connection hole CH.

  The first to third via holes VH1, VH2, and VH3 formed in the first protective insulating layer 20 and the first and second interlayer insulating layers 22 and 24 are opened to the second protective insulating layer 26 side.

  In addition, the bottom surfaces of the first to third via holes VH1, VH2, and VH3 are configured by the external connection pads P2 (first connection pads) and the surfaces of the first and second wiring layers 30 and 32, and The opening area is formed as a frustoconical recess that is larger than the bottom area. A via conductor is formed (filled) in the first to third via holes VH1, VH2, and VH3.

  The second embodiment has an advantage that foreign matter detection is facilitated when a connection failure due to foreign matter adhesion becomes a problem when a semiconductor chip is connected to the chip connection pad P1. Most of the fine foreign matters (particles) are dark or black, and when the foreign matter adheres to the transparent second protective insulating layer 26, there is a difference in light reflectance between the foreign matters and the second protective insulating layer 26. Become prominent. Therefore, the foreign object can be easily detected by the image recognition apparatus, and the foreign object can be reliably detected and removed.

  As shown in FIG. 11, the semiconductor chip 50 is flip-chip connected to the chip connection pad P <b> 1 (second connection pad) by the bump electrode 52. At this time, since the foreign substance is removed on the chip mounting surface A and the surface is clean, the reliability of the connection between the semiconductor chip 50 and the wiring board 1a can be improved.

  Thereafter, the underfill resin 54 is filled in the lower gap of the semiconductor chip 50. Further, the external connection terminals 60 are provided by mounting solder balls on the external connection pads P2 on the lower surface side. Since the external connection terminal 60 is provided on the opaque first protective insulating layer 20 side, positioning is easy. Thereby, a semiconductor package is configured.

  In the second embodiment, the chip connection pad P1 and the external connection pad P2 are arranged upside down in FIG. 7 of the first embodiment, and the other configurations are the same.

  As described above, in the second embodiment, when the foreign matter detection is prioritized over the alignment accuracy when mounting the semiconductor chip, the second protective insulating layer 26 on the chip connection pad P1 side has transparency. To.

(Third embodiment)
FIG. 12 is a cross-sectional view showing a method for manufacturing a wiring board according to a third embodiment of the present invention, and FIG. 13 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of FIG.

  In the third embodiment, as shown in FIG. 12A, the same steps as those in FIGS. 2 to 6 of the first embodiment are performed. However, the first protective insulating layer 20 having transparency is formed in the process of FIG. 3A described above, and the second protective insulating layer 26 having opaqueness is formed in the processes of FIGS. 4C and 5. .

  That is, in FIG. 12A, the first protective insulating layer 20 and the second protective insulating layer 26 have opposite color characteristics in FIG. 6 of the first embodiment, and the first protective insulating layer 20 is transparent. The second protective insulating layer 26 is opaque.

  And as shown in FIG.12 (b), the support plate 5 is removed similarly to 1st Embodiment, and the wiring board 1b of 3rd Embodiment is obtained. In the wiring substrate 1b of the third embodiment, the chip connection pad P1 (first connection pad) is exposed from the transparent first protective insulating layer 20 on the lower surface side, and the non-transparent second protective insulating layer on the upper surface side. 26, the external connection pad P2 (second connection pad) is exposed.

  The side surface of the chip connection pad P1 and the via connection surface (the surface on the first via hole VH1 side) are in contact with the transparent first protective insulating layer 20, and the outer surface (the surface opposite to the via connection surface) is the first protective insulating layer 20. Is exposed from. Further, the non-transparent second protective insulating layer 26 is provided with a connection hole CH, and the central portion of the external connection pad P2 is exposed from the connection hole CH.

  The first to third via holes VH1, VH2, and VH3 formed in the first protective insulating layer 20 and the first and second interlayer insulating layers 22 and 24 are opened to the second protective insulating layer 26 side.

  In addition, the first to third via holes VH1, VH2, and VH3 have bottom surfaces formed by the chip connection pads P1 (first connection pads) and the surfaces of the first and second wiring layers 30 and 32. The opening area is formed as a frustoconical recess that is larger than the bottom area. A via conductor is formed (filled) in the first to third via holes VH1, VH2, and VH3.

  Then, as shown in FIG. 13, the wiring substrate 1 b in FIG. 12B is turned upside down, and the semiconductor chip 50 is flip-chip connected to the chip connection pads P <b> 1 by the bump electrodes 52. Thereafter, the underfill resin 54 is filled in the lower gap of the semiconductor chip 50. Further, the external connection terminals 60 are provided by mounting solder balls on the external connection pads P2 on the lower surface side. Thereby, a semiconductor package is configured.

  In the third embodiment, as in the second embodiment (FIG. 10), the foreign matter (dark color or black) attached to the transparent first protective insulating layer 20 when the semiconductor chip 50 is connected to the chip connection pad P1. Can be easily detected by the image recognition apparatus, and foreign object detection and removal can be performed reliably.

  Thereby, the reliability of the connection between the semiconductor chip 50 and the wiring board 1b can be improved as in the second embodiment.

  Further, since the external connection terminal 60 is provided on the non-transparent second protective insulating layer 26 side, positioning is easy.

(Fourth embodiment)
FIG. 14 is a cross-sectional view showing a wiring board according to a fourth embodiment of the present invention, and FIG. 15 is a cross-sectional view showing a state where a semiconductor chip of the wiring board of FIG. 14 is mounted.

  As shown in FIG. 14, in the wiring board 1c of the fourth embodiment, the arrangement of the chip connection pads P1 and the external connection pads P2 is upside down in FIG. 12B of the third embodiment described above. The upper surface side is a chip mounting surface A and the lower surface side is an external connection surface B.

  That is, the external connection pad P2 (first connection pad) is exposed from the transparent first protective insulating layer 20 on the lower surface side, and the chip connection pad P1 (first contact) from the non-transparent second protective insulating layer 26 on the upper surface side. 2 connection pads) are exposed.

  The side surface of the external connection pad P2 and the via connection surface (the surface on the first via hole VH1 side) are in contact with the transparent first protective insulating layer 20, and the outer surface (the surface opposite to the via connection surface) is the first protective insulating layer 20. Is exposed from. Further, the non-transparent second protective insulating layer 26 is provided with a connection hole CH, and the center portion of the chip connection pad P1 is exposed from the connection hole CH.

  The first to third via holes VH1, VH2, and VH3 formed in the first protective insulating layer 20 and the first and second interlayer insulating layers 22 and 24 are opened to the second protective insulating layer 26 side.

  In addition, the bottom surfaces of the first to third via holes VH1, VH2, and VH3 are configured by the external connection pads P2 (first connection pads) and the surfaces of the first and second wiring layers 30 and 32, and The opening area is formed as a frustoconical recess that is larger than the bottom area. A via conductor is formed (filled) in the first to third via holes VH1, VH2, and VH3.

  In the fourth embodiment, when the external connection terminal is mounted on the external connection pad P2, foreign matters (dark color or black color) that adhere to the transparent first protective insulating layer 20 for the same reason as in the second embodiment. Can be easily detected by the image recognition apparatus, and foreign object detection and removal can be performed reliably.

  Then, as shown in FIG. 15, after the semiconductor chip 50 is flip-chip connected to the chip connection pad P <b> 1 by the bump electrode 52, an underfill resin 54 is filled in the lower gap. Further, the external connection terminals 60 are provided by mounting solder balls on the external connection pads P2 on the lower surface side. Thereby, a semiconductor package is configured.

  At this time, since the external connection surface B is a clean surface from which foreign substances are removed, the external connection terminal 60 can be reliably connected to the wiring board 1c.

  As described above, the fourth embodiment is employed when the highest priority is given to the yield when the external connection terminal 60 is mounted.

  As explained in the first to fourth embodiments described above, on the transparent protective insulating layer side, positioning when forming the connection hole is facilitated, and foreign matter detection on the surface of the wiring board is facilitated. On the non-transparent protective insulating layer side, positioning of various components such as semiconductor chips and external connection terminals and the wiring board is facilitated.

(Other forms)
The present invention may be applied not only to a coreless wiring substrate but also to a cored wiring substrate in which build-up wirings are formed on both sides of the core substrate. In this case, a connection hole that exposes the connection pad is formed in the outermost opaque insulating layer on the one surface side, and the connection pad is exposed in the outermost transparent insulating layer on the other surface side. Holes may be formed so that the colors are different between the insulating layers on both sides.

1, 1a, 1b, 1c ... wiring board, 5 ... support, 6 ... plating resist, 6a ... opening, 10a ... gold (Au layer), 10b ... nickel (Ni) layer, 20 ... first protective insulating layer, 22 ... first interlayer insulating layer, 24 ... second interlayer insulating layer, 26 ... second protective insulating layer, 26a ... photosensitive resin layer, 26b ... non-photosensitive resin layer, 30 ... first wiring layer, 32 ... second Wiring layer, 40 ... Photomask, 40a ... Translucent portion, 40b ... Light-shielding pattern, 50 ... Semiconductor chip, 50a ... Connection electrode, 52 ... Bump electrode, 54 ... Underfill resin, 60 ... External connection terminal, A ... Mounted on chip Surface, B: External connection surface, M: Position alignment mark, VH1: First via hole, VH2: Second via hole, VH3: Third via hole, P1: Chip connection pad, P2: External connection pad

Claims (16)

A first insulating layer formed as an outermost layer on one surface side;
A first connection pad formed exposed from the first insulating layer;
A second insulating layer formed as an outermost layer on the other surface side and exhibiting a color different from the color of the first insulating layer;
A second connection pad formed exposed from the second insulating layer,
One of the first insulating layer and the second insulating layer is transparent, and the other is opaque. The wiring board is a coreless wiring board having no core board,
The outer surface of the first connection pad is exposed from the outer surface of the first insulating layer, the side surface of the first connection pad and the opposite surface of the outer surface are in contact with the first insulating layer, and
2. The wiring board according to claim 1, wherein a connection hole is formed in the second insulating layer, and the second connection pad is exposed at the bottom of the connection hole. The first insulating layer is opaque, the second insulating layer is transparent, and
The wiring board according to claim 2, wherein the first connection pad is a chip connection pad, and the second connection pad is an external connection pad. The first insulating layer is opaque, the second insulating layer is transparent, and
The wiring board according to claim 2, wherein the first connection pad is an external connection pad, and the second connection pad is a chip connection pad. The first insulating layer is transparent, the second insulating layer is opaque, and
The wiring board according to claim 2, wherein the first connection pad is a chip connection pad, and the second connection pad is an external connection pad. The first insulating layer is transparent, the second insulating layer is opaque, and
The wiring board according to claim 2, wherein the first connection pad is an external connection pad, and the second connection pad is a chip connection pad. The color of the insulating layer having the opaqueness is purple or blue, or black or gray, in which the wavelength of visible light to be reflected is 380 to 495 nm,
The color of the insulating layer having the transparency is green, yellow, orange, red, or white whose reflected visible light wavelength is 495 to 750 nm. Wiring board as described in. Forming a first connection pad on the support;
Forming a first insulating layer on the support and the first connection pad;
Forming a via hole reaching the first connection pad by processing the first insulating layer;
Forming an n-layer (n is an integer of 1 or more) wiring layer connected to the first connection pad through the via hole and including the second connection pad as the uppermost layer on the first insulating layer;
Forming a second insulating layer having a connection hole on the second connection pad and exhibiting a color different from the color of the first insulating layer;
Exposing the first connection pad and the first insulating layer by removing the support, and
One of the first insulating layer and the second insulating layer is transparent, and the other is non-transparent. The first insulating layer is opaque, the second insulating layer is transparent, and
9. The method of manufacturing a wiring board according to claim 8, wherein the first connection pad is a chip connection pad, and the second connection pad is an external connection pad. The first insulating layer is opaque, the second insulating layer is transparent, and
9. The method of manufacturing a wiring board according to claim 8, wherein the first connection pad is an external connection pad, and the second connection pad is a chip connection pad. The first insulating layer is transparent, the second insulating layer is opaque, and
9. The method of manufacturing a wiring board according to claim 8, wherein the first connection pad is a chip connection pad, and the second connection pad is an external connection pad. The first insulating layer is transparent, the second insulating layer is opaque, and
9. The method of manufacturing a wiring board according to claim 8, wherein the first connection pad is an external connection pad, and the second connection pad is a chip connection pad. The color of the insulating layer having the opaqueness is purple or blue, or black or gray, in which the wavelength of visible light to be reflected is 380 to 495 nm,
13. The color of the insulating layer having the transparency is green, yellow, orange, red, or white whose reflected light has a wavelength of 495 to 750 nm. 13. The manufacturing method of the wiring board as described in 2 .. The step of forming the second insulating layer includes:
The method for manufacturing a wiring board according to claim 9, comprising forming the connection hole by patterning a photosensitive resin layer by photolithography. The step of forming the second insulating layer includes:
The method for manufacturing a wiring board according to claim 9, further comprising forming the connection hole by laser processing or blasting the resin layer. After the step of removing the support,
13. The method of manufacturing a wiring board according to claim 9, wherein a semiconductor chip is connected to the chip connection pad.

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