JP2012004440A5 - - Google Patents
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- JP2012004440A5 JP2012004440A5 JP2010139664A JP2010139664A JP2012004440A5 JP 2012004440 A5 JP2012004440 A5 JP 2012004440A5 JP 2010139664 A JP2010139664 A JP 2010139664A JP 2010139664 A JP2010139664 A JP 2010139664A JP 2012004440 A5 JP2012004440 A5 JP 2012004440A5
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- insulating layer
- wiring
- main surface
- insulating
- wiring board
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- 229920005989 resin Polymers 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 26
- 239000000203 mixture Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 8
- 230000003014 reinforcing effect Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000000945 filler Substances 0.000 claims description 5
- 230000003746 surface roughness Effects 0.000 claims 2
- 239000000835 fiber Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 18
- 239000003822 epoxy resin Substances 0.000 description 9
- 229920000647 polyepoxide Polymers 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000007864 aqueous solution Substances 0.000 description 6
- 238000005422 blasting Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 150000003949 imides Chemical class 0.000 description 5
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 239000011342 resin composition Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Description
本配線基板の一形態は、複数の配線層と、同一組成の絶縁性樹脂から構成された複数の絶縁層とが交互に積層され、第１の主面及びその反対面である第２の主面を有する配線基板であって、前記第１の主面を形成する第１の絶縁層から露出する第１のピッチで配置された第１の電極パッドと、前記第２の主面を形成する第２の絶縁層に隣接する第３の絶縁層上に設けられ、前記第２の絶縁層の開口部から露出する、前記第１のピッチよりも広い第２のピッチで配置された第２の電極パッドと、前記第３の絶縁層に設けられ、前記第２の電極パッドと前記第３の絶縁層が被覆する配線層とを電気的に接続する導体が形成された貫通孔と、を有し、前記貫通孔の前記第２の電極パッド側の径は、前記貫通孔の前記第３の絶縁層が被覆する配線層側の径よりも大きく、前記第２の絶縁層は、補強部材を備えていることを要件とする。 In one form of the present wiring board, a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately stacked, and the second main surface is the first main surface and the opposite surface. A wiring board having a first surface , the first electrode pads arranged at a first pitch exposed from the first insulating layer forming the first main surface, and the second main surface . A second insulating layer provided on a third insulating layer adjacent to the second insulating layer and exposed from an opening of the second insulating layer and disposed at a second pitch wider than the first pitch; An electrode pad; and a through hole provided with a conductor provided in the third insulating layer and electrically connecting the second electrode pad and the wiring layer covered by the third insulating layer. The diameter of the through hole on the second electrode pad side is the wiring layer side covered by the third insulating layer of the through hole. Greater than the diameter, the second insulating layer is a requirement that it comprises a reinforcing member.
本配線基板の他の形態は、複数の配線層と、同一組成の絶縁性樹脂から構成された複数の絶縁層とが交互に積層され、第１の主面及びその反対面である第２の主面を有する配線基板であって、前記第１の主面を形成する第１の絶縁層から露出する第１のピッチで配置された第１の電極パッドと、前記第２の主面を形成する第２の絶縁層に隣接する第３の絶縁層上に設けられ、前記第２の絶縁層の開口部から露出する、前記第１のピッチよりも広い第２のピッチで配置された第２の電極パッドと、前記第３の絶縁層に設けられ、前記第２の電極パッドと前記第３の絶縁層が被覆する配線層とを電気的に接続する導体が形成された貫通孔と、を有し、前記貫通孔の前記第２の電極パッド側の径は、前記貫通孔の前記第３の絶縁層が被覆する配線層側の径よりも大きく、前記第３の絶縁層は、補強部材を備えていることを要件とする。 In another embodiment of the present wiring board, a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately stacked, and the second main surface and the opposite surface are the second main surface. A wiring board having a main surface , the first electrode pads disposed at a first pitch exposed from the first insulating layer forming the first main surface, and the second main surface formed A second insulating layer disposed on a third insulating layer adjacent to the second insulating layer and exposed from an opening of the second insulating layer and disposed at a second pitch wider than the first pitch. And a through-hole in which a conductor provided in the third insulating layer and electrically connecting the second electrode pad and the wiring layer covered by the third insulating layer is formed. And the diameter of the through hole on the second electrode pad side is a wiring layer covered by the third insulating layer of the through hole Greater than the diameter, the third insulating layer is a requirement that it comprises a reinforcing member.
本配線基板の更に他の形態は、複数の配線層と、複数の絶縁層とが交互に積層され、第１の主面及びその反対面である第２の主面を有する配線基板であって、前記第１の主面を形成する第１の絶縁層から露出する第１のピッチで配置された第１の電極パッドと、前記第２の主面を形成する第２の絶縁層に隣接する第３の絶縁層上に設けられ、前記第２の絶縁層の開口部から露出する、前記第１のピッチよりも広い第２のピッチで配置された第２の電極パッドと、前記第３の絶縁層に設けられ、前記第２の電極パッドと前記第３の絶縁層が被覆する配線層とを電気的に接続する導体が形成された貫通孔と、を有し、前記貫通孔の前記第２の電極パッド側の径は、前記貫通孔の前記第３の絶縁層が被覆する配線層側の径よりも大きく、前記第２の絶縁層は感光性の絶縁性樹脂から構成され、その他の絶縁層は非感光性の同一組成の絶縁性樹脂から構成され、前記第３の絶縁層のみが補強部材を備えていることを要件とする。 Still another embodiment of the present wiring board is a wiring board in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked and have a first main surface and a second main surface opposite to the first main surface. The first electrode pads disposed at a first pitch exposed from the first insulating layer forming the first main surface and the second insulating layer forming the second main surface are adjacent to each other. A second electrode pad provided on a third insulating layer and exposed from an opening of the second insulating layer and disposed at a second pitch wider than the first pitch; and A through hole provided in an insulating layer and formed with a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer; 2 is larger than the diameter of the wiring layer side covered by the third insulating layer of the through-hole, Enso is composed of a photosensitive insulating resin, other insulating layer is composed of non-photosensitive insulating resin of the same composition, and requirements that only the third insulating layer is provided with a reinforcing member To do.
［第１の実施の形態に係る配線基板の製造方法］
続いて、第１の実施の形態に係る配線基板の製造方法について説明する。図９〜図１６は、第１の実施の形態に係る配線基板の製造工程を例示する図である。
[Method for Manufacturing Wiring Board According to First Embodiment]
Next, a method for manufacturing a wiring board according to the first embodiment will be described. 9 to 16 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment.
始めに、図９に示す工程では、支持体２１を準備する。支持体２１としては、シリコン板、ガラス板、金属箔等を用いることができるが、本実施の形態では、支持体２１として銅箔を用いる。後述する図１１に示す工程等において電解めっきを行う際の給電層として利用でき、後述する図１６に示す工程の後に容易にエッチングで除去可能だからである。支持体２１の厚さは、例えば３５〜１００μｍ程度とすることができる。 First, in the step shown in FIG. 9 , a support 21 is prepared. As the support 21, a silicon plate, a glass plate, a metal foil, or the like can be used. In the present embodiment, a copper foil is used as the support 21. This is because it can be used as a power supply layer when performing electrolytic plating in the process shown in FIG. 11 described later, and can be easily removed by etching after the process shown in FIG. 16 described later. The thickness of the support body 21 can be about 35-100 micrometers, for example.
次いで、図１０に示す工程では、支持体２１の一方の面に、第１配線層１１に対応する開口部２２ｘを有するレジスト層２２を形成する。具体的には、支持体２１の一方の面に、例えばエポキシ系樹脂やイミド系樹脂等を含む感光性樹脂組成物からなる液状又はペースト状のレジストを塗布する。或いは、支持体２１の一方の面に、例えばエポキシ系樹脂やイミド系樹脂等を含む感光性樹脂組成物からなるフィルム状のレジスト（例えば、ドライフィルムレジスト等）をラミネートする。そして、塗布又はラミネートしたレジストを露光、現像することで開口部２２ｘを形成する。これにより、開口部２２ｘを有するレジスト層２２が形成される。なお、予め開口部２２ｘを形成したフィルム状のレジストを支持体２１の一方の面にラミネートしても構わない。 Next, in a step shown in FIG. 10 , a resist layer 22 having an opening 22 x corresponding to the first wiring layer 11 is formed on one surface of the support 21. Specifically, a liquid or paste resist made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is applied to one surface of the support 21. Alternatively, a film-like resist (for example, a dry film resist) made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is laminated on one surface of the support 21. Then, the opening 22x is formed by exposing and developing the coated or laminated resist. Thereby, the resist layer 22 having the opening 22x is formed. Note that a film-like resist in which the opening 22x is formed in advance may be laminated on one surface of the support 21.
開口部２２ｘは、後述の図１１に示す工程で形成される第１配線層１１に対応する位置に形成されるが、その配設ピッチは、例えば１００〜２００μｍ程度とすることができる。開口部２２ｘの平面形状は、例えば円形であり、その直径は例えば４０〜１２０μｍ程度とすることができる。 The opening 22x is formed at a position corresponding to the first wiring layer 11 formed in the process shown in FIG. 11 to be described later, and the arrangement pitch can be, for example, about 100 to 200 μm. The planar shape of the opening 22x is, for example, a circle, and the diameter can be, for example, about 40 to 120 μm.
次いで、図１１に示す工程では、支持体２１をめっき給電層に利用する電解めっき法等により、支持体２１の一方の面の開口部２２ｘ内に、第１層１１ａ及び第２層１１ｂから構成される第１配線層１１を形成する。 Next, in the process shown in FIG. 11 , the first layer 11 a and the second layer 11 b are formed in the opening 22 x on one surface of the support 21 by an electrolytic plating method using the support 21 as a plating power feeding layer. The first wiring layer 11 to be formed is formed.
次いで、図１２に示す工程では、図１１に示すレジスト層２２を除去した後、第１配線層１１を覆うように支持体２１の一方の面に第１絶縁層１２を形成する。第１絶縁層１２の材料としては、例えばエポキシ系樹脂を主成分とする非感光性の絶縁性樹脂等を用いることができる。第１絶縁層１２の厚さは、例えば１５〜３５μｍ程度とすることができる。第１絶縁層１２は、シリカ（ＳｉＯ２）等のフィラーを含有している。フィラーの含有量や含有する目的は、前述の通りである。 Next, in the step shown in FIG. 12 , after removing the resist layer 22 shown in FIG. 11 , the first insulating layer 12 is formed on one surface of the support 21 so as to cover the first wiring layer 11. As a material of the first insulating layer 12, for example, a non-photosensitive insulating resin mainly containing an epoxy resin can be used. The thickness of the 1st insulating layer 12 can be about 15-35 micrometers, for example. The first insulating layer 12 contains a filler such as silica (SiO 2 ). The content and purpose of the filler are as described above.
次いで、図１３に示す工程では、第１絶縁層１２に、第１絶縁層１２を貫通し第１配線層１１の上面を露出させる第１ビアホール１２ｘを形成する。第１ビアホール１２ｘは、例えばＣＯ２レーザ等を用いたレーザ加工法により形成できる。レーザ加工法により形成した第１ビアホール１２ｘは、第２絶縁層１４が形成される側に開口されていると共に、第１配線層１１の上面によって底面が形成された、開口部の面積が底面の面積よりも大となる円錐台状の凹部となる。なお、他のビアホールもレーザ加工法により形成すると同様の形状となる。第１ビアホール１２ｘをレーザ加工法により形成した場合には、デスミア処理を行い、第１ビアホール１２ｘの底部に露出する第１配線層１１の上面に付着した第１絶縁層１２の樹脂残渣を除去する。 Next, in a step shown in FIG. 13 , a first via hole 12 x that penetrates the first insulating layer 12 and exposes the upper surface of the first wiring layer 11 is formed in the first insulating layer 12. The first via hole 12x can be formed by a laser processing method using, for example, a CO 2 laser. The first via hole 12x formed by the laser processing method is opened on the side where the second insulating layer 14 is formed, and the bottom surface is formed by the top surface of the first wiring layer 11, and the area of the opening is the bottom surface. It becomes a truncated-cone-shaped recessed part which becomes larger than an area. Other via holes are formed in the same shape when formed by laser processing. When the first via hole 12x is formed by a laser processing method, a desmear process is performed to remove the resin residue of the first insulating layer 12 attached to the upper surface of the first wiring layer 11 exposed at the bottom of the first via hole 12x. .
次いで、図１４に示す工程では、第１絶縁層１２上に第２配線層１３を形成する。第２配線層１３は、第１ビアホール１２ｘ内に充填されたビア配線、及び第１絶縁層１２上に形成された配線パターンを含んで構成される。第２配線層１３は、第１ビアホール１２ｘの底部に露出した第１配線層１１と電気的に接続される。第２配線層１３の材料としては、例えば銅（Ｃｕ）等を用いることができる。 Next, in the step shown in FIG. 14 , the second wiring layer 13 is formed on the first insulating layer 12. The second wiring layer 13 includes a via wiring filled in the first via hole 12 x and a wiring pattern formed on the first insulating layer 12. The second wiring layer 13 is electrically connected to the first wiring layer 11 exposed at the bottom of the first via hole 12x. As a material of the second wiring layer 13, for example, copper (Cu) or the like can be used.
次いで、図１５に示す工程では、上記と同様な工程を繰り返すことにより、第１絶縁層１２上に、第２絶縁層１４、第３配線層１５、第３絶縁層１６、及び第４配線層１７を積層する。すなわち、第１絶縁層１２上に第２配線層１３を被覆する第２絶縁層１４を形成した後に、第２絶縁層１４を貫通し第２配線層１３の上面を露出する第２ビアホール１４ｘを形成する。第２ビアホール１４ｘは、必要に応じて、第１ビアホール１２ｘの垂直方向に積み重ねて相互接続する所謂スタックビア構造とすることができる。第２絶縁層１４の材料としては、第１絶縁層１２と同一組成の非感光性の絶縁性樹脂を用いることが好ましい。又、第２絶縁層１４は、第１絶縁層１２が含有するフィラーと同一組成のフィラーを略同一量だけ含有することが好ましい。配線基板１０に生ずる反りを低減するためである。第２絶縁層１４の厚さは、例えば１５〜３５μｍ程度とすることができる。 Next, in the process shown in FIG. 15 , by repeating the same process as described above, the second insulating layer 14, the third wiring layer 15, the third insulating layer 16, and the fourth wiring layer are formed on the first insulating layer 12. 17 is laminated. That is, after forming the second insulating layer 14 covering the second wiring layer 13 on the first insulating layer 12, the second via hole 14 x penetrating the second insulating layer 14 and exposing the upper surface of the second wiring layer 13 is formed. Form. The second via hole 14x may have a so-called stacked via structure in which the first via holes 12x are stacked and interconnected in the vertical direction as necessary. As a material for the second insulating layer 14, it is preferable to use a non-photosensitive insulating resin having the same composition as the first insulating layer 12. The second insulating layer 14 preferably contains substantially the same amount of filler having the same composition as the filler contained in the first insulating layer 12. This is for reducing the warpage generated in the wiring board 10. The thickness of the second insulating layer 14 can be about 15 to 35 μm, for example.
次いで、図１６に示す工程では、第３絶縁層１６上に開口部１８ｘを有する第４絶縁層１８を形成する。具体的には、例えば、第４配線層１７を覆うように、第３絶縁層１６上に液状又はペースト状のエポキシ系樹脂やイミド系樹脂等を含む感光性の絶縁性樹脂を塗布する。そして、塗布した感光性の絶縁性樹脂を露光及び現像することで開口部１８ｘを形成する。これにより、凹部１７ｘを含む第４配線層１７の一部は、第４絶縁層１８の開口部１８ｘの底部に露出する。第４絶縁層１８の厚さは、例えば１５〜３５μｍ程度とすることができる。なお、第４絶縁層１８をエポキシ系樹脂を主成分とする非感光性の絶縁性樹脂等（第１絶縁層１２と同一組成の非感光性の絶縁性樹脂）を用いて形成し、開口部１８ｘをレーザ加工法等により形成しても構わない。 Next, in a step shown in FIG. 16 , a fourth insulating layer 18 having an opening 18 x is formed on the third insulating layer 16. Specifically, for example, a photosensitive insulating resin containing a liquid or paste-like epoxy resin or imide resin is applied on the third insulating layer 16 so as to cover the fourth wiring layer 17. Then, the opening 18x is formed by exposing and developing the applied photosensitive insulating resin. Thereby, a part of the fourth wiring layer 17 including the recess 17 x is exposed at the bottom of the opening 18 x of the fourth insulating layer 18. The thickness of the fourth insulating layer 18 can be about 15 to 35 μm, for example. The fourth insulating layer 18 is formed using a non-photosensitive insulating resin or the like whose main component is an epoxy resin (non-photosensitive insulating resin having the same composition as the first insulating layer 12), and an opening portion. 18x may be formed by a laser processing method or the like.
次いで、図１６に示す工程の後、図１６に示す支持体２１を除去することにより、図５に示す配線基板１０が完成する。銅箔から構成されている支持体２１は、例えば塩化第二鉄水溶液や塩化第二銅水溶液、過硫酸アンモニウム水溶液等を用いたウェットエッチングにより除去できる。この際、第１絶縁層１２から露出する第１配線層１１の最表層は金（Ａｕ）膜等であるため、銅箔から構成されている支持体２１のみを選択的にエッチングできる。但し、第４配線層１７が銅（Ｃｕ）から構成されている場合には、開口部１８ｘの底部に露出する凹部１７ｘを含む第４配線層１７が支持体２１とともにエッチングされることを防止するため、第４配線層１７をマスクする必要がある。 Then, after the step shown in FIG. 16, by removing the supporting member 21 shown in FIG. 16, the wiring substrate 10 shown in FIG. 5 is completed. The support 21 made of copper foil can be removed by wet etching using, for example, a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, since the outermost layer of the first wiring layer 11 exposed from the first insulating layer 12 is a gold (Au) film or the like, only the support 21 made of copper foil can be selectively etched. However, when the fourth wiring layer 17 is made of copper (Cu), the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x is prevented from being etched together with the support 21. Therefore, it is necessary to mask the fourth wiring layer 17.
なお、図９〜図１６では、支持体２１上に１個の配線基板１０を作製する例を示したが、支持体２１上に複数の配線基板１０となる部材を作製し、それを個片化して複数の配線基板１０を得るような工程としても構わない。 Although FIGS. 9 to 16 show an example in which one wiring board 10 is manufactured on the support body 21, a member to be a plurality of wiring boards 10 is manufactured on the support body 21, and the individual pieces are separated. It does not matter as a process of obtaining a plurality of wiring boards 10 by making them.
［第２の実施の形態に係る配線基板の構造］
始めに、第２の実施の形態に係る配線基板の構造について説明する。図１７は、第２の実施の形態に係る配線基板を例示する断面図である。図１７を参照するに、第２の実施の形態に係る配線基板５０は、第３絶縁層１６、第４配線層１７、及び第４絶縁層１８が、それぞれ第３絶縁層５６、第４配線層５７、及び第４絶縁層５８に置換されている点が、第１の実施の形態に係る配線基板１０（図５参照）と相違する。
[Structure of Wiring Board According to Second Embodiment]
First, the structure of the wiring board according to the second embodiment will be described. FIG. 17 is a cross-sectional view illustrating a wiring board according to the second embodiment. Referring to FIG. 17 , the wiring substrate 50 according to the second embodiment includes a third insulating layer 16, a fourth wiring layer 17, and a fourth insulating layer 18, and a third insulating layer 56 and a fourth wiring, respectively. The point that the layer 57 and the fourth insulating layer 58 are replaced is different from the wiring board 10 (see FIG. 5) according to the first embodiment.
図１８は、図１７の開口部近傍を拡大して例示する断面図である。図１８を参照するに、開口部５８ｘは、第４配線層５７側から開口端に向って末広がりとなっており、側壁の断面は凹型Ｒ形状である。言い換えれば、開口部５８ｘは、第２の電極パッド５７ｘの外周方向に突出又は湾曲する曲面状の側壁を有し、かつ、第４絶縁層５８外面に開口する部分の面積が、底面部分の断面積よりも大きい。開口部５８ｘは、例えば半球状に形成することができる。開口部５８ｘの平面形状は例えば円形であり、その直径（開口端の直径）は例えば２２０〜１１００μｍ程度とすることができる。 Figure 18 is a cross-sectional view illustrating an enlarged vicinity of the opening of FIG. 17. Referring to FIG. 18 , the opening 58x extends from the fourth wiring layer 57 side toward the opening end, and the side wall has a concave R shape. In other words, the opening 58x has a curved side wall that protrudes or curves in the outer peripheral direction of the second electrode pad 57x, and the area of the portion that opens to the outer surface of the fourth insulating layer 58 is a portion of the bottom portion. Greater than area. The opening 58x can be formed in a hemispherical shape, for example. The planar shape of the opening 58x is, for example, a circle, and the diameter (diameter of the opening end) can be, for example, about 220 to 1100 μm.
［第２の実施の形態に係る配線基板の製造方法］
続いて、第２の実施の形態に係る配線基板の製造方法について説明する。図１９〜図２１は、第２の実施の形態に係る配線基板の製造工程を例示する図である。
[Manufacturing Method of Wiring Board According to Second Embodiment]
Then, the manufacturing method of the wiring board based on 2nd Embodiment is demonstrated. 19 to 21 are diagrams illustrating a manufacturing process of the wiring board according to the second embodiment.
始めに、図１９に示す工程では、図９〜図１５と同様の工程を実施し、第１絶縁層１２上に、第２絶縁層１４、第３配線層１５、第３絶縁層５６、及び第４配線層５７を積層する。そして、第３絶縁層５６上に、第４配線層５７を覆うように、ガラスクロス１９に例えばエポキシ系樹脂を主成分とする非感光性の絶縁性樹脂等を含浸させた第４絶縁層５８を形成する。第４絶縁層５８は、ガラスクロス１９に例えばエポキシ系樹脂を主成分とする非感光性の絶縁性樹脂等を含浸させた樹脂フィルム（プリプレグ）を第３絶縁層５６上に積層し、加圧及び加熱して樹脂を硬化させることにより形成できる。 First, in the process shown in FIG. 19 , the same processes as in FIGS. 9 to 15 are performed, and the second insulating layer 14, the third wiring layer 15, the third insulating layer 56, and the like are formed on the first insulating layer 12. A fourth wiring layer 57 is laminated. Then, a fourth insulating layer 58 obtained by impregnating the glass cloth 19 with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin so as to cover the fourth wiring layer 57 on the third insulating layer 56. Form. The fourth insulating layer 58 is formed by laminating a resin film (prepreg) in which a glass cloth 19 is impregnated with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin on the third insulating layer 56, and pressurizing. And it can form by heating and hardening resin.
次いで、図２０に示す工程では、第４絶縁層５８上に、開口部２３ｘを有するレジスト層２３を形成する。具体的には、第４絶縁層５８上に、例えばエポキシ系樹脂やイミド系樹脂等を含む感光性樹脂組成物からなる液状又はペースト状のレジストを塗布する。或いは、第４絶縁層５８上に、例えばエポキシ系樹脂やイミド系樹脂等を含む感光性樹脂組成物からなるフィルム状のレジスト（例えば、ドライフィルムレジスト等）をラミネートする。そして、塗布又はラミネートしたレジストを露光、現像することで開口部２３ｘを形成する。これにより、開口部２３ｘを有するレジスト層２３が形成される。なお、予め開口部２３ｘを形成したフィルム状のレジストを第４絶縁層５８上にラミネートしても構わない。 Next, in a step shown in FIG. 20 , a resist layer 23 having an opening 23 x is formed on the fourth insulating layer 58. Specifically, a liquid or paste resist made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is applied on the fourth insulating layer 58. Alternatively, a film resist (eg, a dry film resist) made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is laminated on the fourth insulating layer 58. Then, the opening 23x is formed by exposing and developing the coated or laminated resist. Thereby, the resist layer 23 having the opening 23x is formed. Note that a film-like resist in which the opening 23x is formed in advance may be laminated on the fourth insulating layer 58.
開口部２３ｘは、後述の図２１に示す工程で形成される開口部５８ｘに対応する位置に形成されるが、その配設ピッチは、例えば５００〜１２００μｍ程度とすることができる。開口部２３ｘの平面形状は例えば円形であり、その直径は例えば２２０〜１１００μｍ程度とすることができる。 The opening 23x is formed at a position corresponding to the opening 58x formed in the process shown in FIG. 21 to be described later, and the arrangement pitch can be set to, for example, about 500 to 1200 μm. The planar shape of the opening 23x is, for example, a circle, and the diameter can be, for example, about 220 to 1100 μm.
なお、レジスト層２３は、後述する図２１に示す工程におけるブラスト処理のマスクとして機能するが、レジスト層２３の表面の一部もブラスト処理により削れる。そこで、レジスト層２３は、表面の一部がブラスト処理により削れてもマスクとしての機能を維持できる程度の厚さに形成する必要がある。レジスト層２３の厚さは、例えば５０μｍ程度とすることができる。 The resist layer 23 functions as a mask for blasting in a process shown in FIG. 21 to be described later, but part of the surface of the resist layer 23 is also removed by blasting. Therefore, the resist layer 23 needs to be formed to a thickness that can maintain the function as a mask even if a part of the surface is shaved by blasting. The thickness of the resist layer 23 can be about 50 μm, for example.
次いで、図２１に示す工程では、レジスト層２３をマスクとして矢印方向からブラスト処理を行い、第４絶縁層５８に開口部５８ｘを形成し第４配線層５７の上面を露出させる。そして、更にブラスト処理を継続し第４配線層５７の開口部５８ｘの底部に露出する部分に凹部５７ｘを形成する。このように、第４配線層５７の上面を露出させた後、更にブラスト処理を継続し凹部５７ｘを形成することにより、開口部５８ｘ内に第４絶縁層５８の材料の残渣が残存しないようにできる。 Next, in the step shown in FIG. 21 , blasting is performed from the direction of the arrow using the resist layer 23 as a mask to form an opening 58 x in the fourth insulating layer 58 to expose the upper surface of the fourth wiring layer 57. Then, the blasting process is further continued to form a recess 57x in a portion exposed at the bottom of the opening 58x of the fourth wiring layer 57. As described above, after the upper surface of the fourth wiring layer 57 is exposed, the blast process is continued to form the recess 57x so that the residue of the material of the fourth insulating layer 58 does not remain in the opening 58x. it can.
ブラスト処理により形成された開口部５８ｘ及び凹部５７ｘは、前述の図１８で説明した形状となる。これにより、開口部５８ｘを有する第４絶縁層５８が形成され、開口部５８ｘの底部に露出する第４配線層５７の凹部５７ｘは、マザーボード等の実装基板（図示せず）と電気的に接続される電極パッドとして機能する。 Blasting openings 58x and the concave portion 57x formed by has a shape described in FIG. 18 described above. As a result, a fourth insulating layer 58 having an opening 58x is formed, and the recess 57x of the fourth wiring layer 57 exposed at the bottom of the opening 58x is electrically connected to a mounting substrate (not shown) such as a motherboard. It functions as an electrode pad.
次いで、図２１に示す工程の後、図２１に示すレジスト層２３を除去し、更に図２１に示す支持体２１を除去することにより、図１７及び図１８に示す配線基板５０が完成する。銅箔から構成されている支持体２１は、例えば塩化第二鉄水溶液や塩化第二銅水溶液、過硫酸アンモニウム水溶液等を用いたウェットエッチングにより除去できる。この際、第１絶縁層１２から露出する第１配線層１１の最表層は金（Ａｕ）膜等であるため、銅箔から構成されている支持体２１のみを選択的にエッチングできる。但し、第４配線層５７が銅（Ｃｕ）から構成されている場合には、開口部５８ｘの底部に露出する凹部５７ｘが支持体２１とともにエッチングされることを防止するため、凹部５７ｘをマスクする必要がある。 Then, after the step shown in FIG. 21, removing the resist layer 23 shown in FIG. 21, by removing the supporting member 21 is further illustrated in FIG. 21, the wiring substrate 50 shown in FIGS. 17 and 18 is completed. The support 21 made of copper foil can be removed by wet etching using, for example, a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, since the outermost layer of the first wiring layer 11 exposed from the first insulating layer 12 is a gold (Au) film or the like, only the support 21 made of copper foil can be selectively etched. However, when the fourth wiring layer 57 is made of copper (Cu), the recess 57x is masked to prevent the recess 57x exposed at the bottom of the opening 58x from being etched together with the support 21. There is a need.
なお、図１９〜図２１では、支持体２１上に１個の配線基板５０を作製する例を示したが、支持体２１上に複数の配線基板５０となる部材を作製し、それを個片化して複数の配線基板５０を得るような工程としても構わない。又、支持体２１を除去する前や除去した後に、はんだボールやリードピン等の外部接続端子を形成しても構わない。 In FIGS. 19 to 21 , an example in which one wiring board 50 is manufactured on the support 21 is shown. However, a member to be a plurality of wiring boards 50 is manufactured on the support 21, and the individual pieces are separated. It may be a process of obtaining a plurality of wiring boards 50. Also, external connection terminals such as solder balls and lead pins may be formed before or after the support 21 is removed.
図２２は、第３の実施の形態に係る半導体パッケージを例示する断面図である。図２２を参照するに、半導体パッケージ７０は、図５に示す配線基板１０と、半導体チップ７１と、バンプ７４と、アンダーフィル樹脂７５とを有する。なお、図２２において、配線基板１０は、図５とは上下を反転して描かれている。 FIG. 22 is a cross-sectional view illustrating a semiconductor package according to the third embodiment. Referring to FIG. 22 , the semiconductor package 70 includes the wiring substrate 10 shown in FIG. 5, a semiconductor chip 71, bumps 74, and underfill resin 75. In FIG. 22 , the wiring board 10 is drawn upside down from FIG.
このように、第３の実施の形態によれば、第１の実施の形態に係る配線基板に半導体チップを搭載した半導体パッケージを実現できる。すなわち、反りが少なく高密度化にも対応できる半導体パッケージを実現できる。なお、第２の実施の形態に係る配線基板（図１７参照）を用いても同様の半導体パッケージを実現できることは言うまでもない。 Thus, according to the third embodiment, it is possible to realize a semiconductor package in which a semiconductor chip is mounted on the wiring board according to the first embodiment. In other words, it is possible to realize a semiconductor package that is less warped and can cope with higher density. It goes without saying that a similar semiconductor package can be realized even if the wiring substrate according to the second embodiment (see FIG. 17 ) is used.
図２３は、配線基板Ａのシミュレーション結果を模式的に示した図である。図２４は、配線基板Ｂのシミュレーション結果を模式的に示した図である。図２３及び図２４に示したように、配線基板Ａ及びＢは何れも半導体チップ搭載面となる第１配線層１１側が凸状に反った形状となった。配線基板全体の反りＴ１及びＴ３、半導体チップ搭載領域の反りＴ２及びＴ４を表１に示す。
FIG. 23 is a diagram schematically showing a simulation result of the wiring board A. FIG. 24 is a diagram schematically showing a simulation result of the wiring board B. As shown in FIG. As shown in FIGS. 23 and 24 , the wiring boards A and B both have a shape in which the first wiring layer 11 side, which is the semiconductor chip mounting surface, is warped in a convex shape. Wiring board entire warp T 1 and T 3, shown in Table 1 the warp T 2 and T 4 of the semiconductor chip mounting area.
Claims (10)
前記第１の主面を形成する第１の絶縁層から露出する第１のピッチで配置された第１の電極パッドと、
前記第２の主面を形成する第２の絶縁層に隣接する第３の絶縁層上に設けられ、前記第２の絶縁層の開口部から露出する、前記第１のピッチよりも広い第２のピッチで配置された第２の電極パッドと、
前記第３の絶縁層に設けられ、前記第２の電極パッドと前記第３の絶縁層が被覆する配線層とを電気的に接続する導体が形成された貫通孔と、を有し、
前記貫通孔の前記第２の電極パッド側の径は、前記貫通孔の前記第３の絶縁層が被覆する配線層側の径よりも大きく、
前記第２の絶縁層は、補強部材を備えていることを特徴とする配線基板。 A wiring board having a first main surface and a second main surface opposite to the first main surface, wherein a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately laminated. ,
A first electrode pad disposed at a first pitch exposed from a first insulating layer forming the first main surface;
A second width wider than the first pitch is provided on a third insulating layer adjacent to the second insulating layer forming the second main surface and exposed from the opening of the second insulating layer. Second electrode pads arranged at a pitch of
A through hole provided in the third insulating layer, in which a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer is formed;
The diameter of the through hole on the second electrode pad side is larger than the diameter of the through hole on the wiring layer side covered by the third insulating layer,
The wiring board, wherein the second insulating layer includes a reinforcing member.
前記開口部の底部に露出する前記第２の電極パッド部分に凹部が設けられている請求項１記載の配線基板。 The wiring substrate according to claim 1, wherein a recess is provided in the second electrode pad portion exposed at the bottom of the opening.
前記凹部の側壁の最外縁部は、前記開口部の側壁の最内縁部と一致している請求項２記載の配線基板。 The wiring board according to claim 2, wherein an outermost edge portion of the side wall of the recess coincides with an innermost edge portion of the side wall of the opening.
前記第１の主面を形成する第１の絶縁層から露出する第１のピッチで配置された第１の電極パッドと、
前記第２の主面を形成する第２の絶縁層に隣接する第３の絶縁層上に設けられ、前記第２の絶縁層の開口部から露出する、前記第１のピッチよりも広い第２のピッチで配置された第２の電極パッドと、
前記第３の絶縁層に設けられ、前記第２の電極パッドと前記第３の絶縁層が被覆する配線層とを電気的に接続する導体が形成された貫通孔と、を有し、
前記貫通孔の前記第２の電極パッド側の径は、前記貫通孔の前記第３の絶縁層が被覆する配線層側の径よりも大きく、
前記第３の絶縁層は、補強部材を備えていることを特徴とする配線基板。 A wiring board having a first main surface and a second main surface opposite to the first main surface, wherein a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately laminated. ,
A first electrode pad disposed at a first pitch exposed from a first insulating layer forming the first main surface;
A second width wider than the first pitch is provided on a third insulating layer adjacent to the second insulating layer forming the second main surface and exposed from the opening of the second insulating layer. Second electrode pads arranged at a pitch of
A through hole provided in the third insulating layer, in which a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer is formed;
The diameter of the through hole on the second electrode pad side is larger than the diameter of the through hole on the wiring layer side covered by the third insulating layer,
The wiring board, wherein the third insulating layer includes a reinforcing member.
前記第１の主面を形成する第１の絶縁層から露出する第１のピッチで配置された第１の電極パッドと、
前記第２の主面を形成する第２の絶縁層に隣接する第３の絶縁層上に設けられ、前記第２の絶縁層の開口部から露出する、前記第１のピッチよりも広い第２のピッチで配置された第２の電極パッドと、
前記第３の絶縁層に設けられ、前記第２の電極パッドと前記第３の絶縁層が被覆する配線層とを電気的に接続する導体が形成された貫通孔と、を有し、
前記貫通孔の前記第２の電極パッド側の径は、前記貫通孔の前記第３の絶縁層が被覆する配線層側の径よりも大きく、
前記第２の絶縁層は感光性の絶縁性樹脂から構成され、その他の絶縁層は非感光性の同一組成の絶縁性樹脂から構成され、
前記第３の絶縁層のみが補強部材を備えていることを特徴とする配線基板。 A wiring board in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked, and has a first main surface and a second main surface that is the opposite surface.
A first electrode pad disposed at a first pitch exposed from a first insulating layer forming the first main surface;
A second width wider than the first pitch is provided on a third insulating layer adjacent to the second insulating layer forming the second main surface and exposed from the opening of the second insulating layer. Second electrode pads arranged at a pitch of
A through hole provided in the third insulating layer, in which a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer is formed;
The diameter of the through hole on the second electrode pad side is larger than the diameter of the through hole on the wiring layer side covered by the third insulating layer,
The second insulating layer is made of a photosensitive insulating resin, and the other insulating layers are made of a non-photosensitive insulating resin having the same composition,
Only the third insulating layer includes a reinforcing member.
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| JP2013229526A (en) * | 2012-04-26 | 2013-11-07 | Ngk Spark Plug Co Ltd | Multilayer wiring board and method of manufacturing the same |
| JP5677627B2 (en) | 2012-05-24 | 2015-02-25 | 富士フイルム株式会社 | Polarizing plate and liquid crystal display device |
| JP5990421B2 (en) * | 2012-07-20 | 2016-09-14 | 新光電気工業株式会社 | Wiring substrate, manufacturing method thereof, and semiconductor package |
| JP5952153B2 (en) * | 2012-09-28 | 2016-07-13 | 京セラ株式会社 | Multilayer wiring board and mounting structure using the same |
| US10424547B2 (en) * | 2017-08-30 | 2019-09-24 | Advanced Semiconductor Engineering Inc. | Semiconductor device package and a method of manufacturing the same |
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| JPH04322451A (en) * | 1991-04-23 | 1992-11-12 | Hitachi Ltd | Semiconductor device |
| JP2000244127A (en) * | 1998-12-24 | 2000-09-08 | Ngk Spark Plug Co Ltd | Wiring board and its manufacture |
| JP2000286362A (en) * | 1999-03-30 | 2000-10-13 | Mitsubishi Gas Chem Co Inc | Printed circuit board for ultra-thin BGA type semiconductor plastic package |
| JP2000294677A (en) * | 1999-04-05 | 2000-10-20 | Fujitsu Ltd | High density thin film wiring board and method of manufacturing the same |
| JP2001284809A (en) * | 2000-04-03 | 2001-10-12 | Ibiden Co Ltd | Multilayer circuit board and its manufacturing method |
| JP3760101B2 (en) * | 2001-02-13 | 2006-03-29 | 富士通株式会社 | Multilayer printed wiring board and manufacturing method thereof |
| JP2002290022A (en) * | 2001-03-27 | 2002-10-04 | Kyocera Corp | Wiring board, method of manufacturing the same, and electronic device |
| JP4070193B2 (en) * | 2002-10-01 | 2008-04-02 | 京セラ株式会社 | Wiring board and electronic component mounting structure |
| JP4072176B2 (en) * | 2005-08-29 | 2008-04-09 | 新光電気工業株式会社 | Manufacturing method of multilayer wiring board |
| JP4806279B2 (en) * | 2006-03-17 | 2011-11-02 | 三菱樹脂株式会社 | Insulating substrate containing glass cloth |
| JP4929784B2 (en) * | 2006-03-27 | 2012-05-09 | 富士通株式会社 | Multilayer wiring board, semiconductor device and solder resist |
| JP2008028302A (en) * | 2006-07-25 | 2008-02-07 | Sumitomo Bakelite Co Ltd | Multilayer circuit board and semiconductor device using the multilayer circuit board |
| JP2008041932A (en) * | 2006-08-07 | 2008-02-21 | Toray Ind Inc | Method of manufacturing wiring board |
| JP5092547B2 (en) * | 2007-05-30 | 2012-12-05 | 凸版印刷株式会社 | Method for manufacturing printed wiring board |
| JP5096855B2 (en) * | 2007-09-27 | 2012-12-12 | 新光電気工業株式会社 | Wiring board manufacturing method and wiring board |
| JP2009224461A (en) * | 2008-03-14 | 2009-10-01 | Shinko Electric Ind Co Ltd | Wiring board and method of manufacturing the same |
| JP5295596B2 (en) * | 2008-03-19 | 2013-09-18 | 新光電気工業株式会社 | Multilayer wiring board and manufacturing method thereof |
| JP5302635B2 (en) * | 2008-11-13 | 2013-10-02 | パナソニック株式会社 | Multilayer wiring board |
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