JP2012003811A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can avoid a multi-selection state in which both Y switches of selected bit line and non-selected bit line are selected.SOLUTION: A semiconductor device comprises: a Y switch for electrical-potentially connecting a bit line to an IO line according to the potential of a gate electrode; a via for supplying a Y switch control signal to the gate electrode of the Y switch; a transistor (N1) connected to the gate electrode of the Y switch for setting the gate electrode into GND potential in response to the signal (1) and for controlling the Y switch into electrically-nonconductive; and a circuit (P1 to P3) for precharging and equalizing the bit line in precharge voltage. The activation of the precharge signal in which the gate electrode of the Y switch is set into GND potential corresponds to the timing of the activation of the equalizer circuit.

Description

  The present invention relates to a semiconductor device, and more particularly to a device suitable for application to a semiconductor device including a transistor for controlling connection between data lines.

  Hereinafter, DRAM (Dynamic Random Access Memory) will be outlined as a related-art semiconductor device. FIG. 1 is a diagram schematically showing an example of the configuration of a general DRAM. As shown in FIG. 1, a memory array 1, an X decoder and an X timing generation circuit 2, a Y decoder and a Y timing generation circuit 3, a decoder control circuit 4, a DLL (Delay Locked Loop) 9, and a data latch circuit 5 , An input / output interface 6, an internal clock (CLK) generation circuit 7, and a control signal generation circuit 8. The memory array 1 includes banks 0 to m, and each bank includes memory mat columns 1, 2, and 3. Of course, the bank configuration, the memory mat configuration in the bank, and the like are not limited to such a configuration. The control signal generation circuit 8 receives command signals (/ CS (chip select), / RAS (row address strobe), / CAS (column address strobe), / WE (write enable)) and decodes the command. Then, a control signal is generated according to the command decoding result and output to the X decoder and X timing generation circuit 2, the Y decoder and Y timing generation circuit 3, the decoder control circuit 4, and the like. Note that the symbol “/” in front of the signal name indicates an active state when the signal level is Low. In addition, the row address of the input address signal (ADD) is decoded by the X decoder 2, and the word line WL is selected by the sub word driver (SWD). When the word line WL is selected, data is read from the memory cell (MC) to the bit line (BL) and amplified by the sense amplifier (SA). The column address of the address (ADD) is decoded by the Y decoder 3, the selected column selection signal is activated, and the bit line (BL) and the sense amplifier (SA) are selected.

  The output (read data) amplified by the sense amplifier (SA) is transferred to the data latch circuit 5 and the input / output interface 6 and output to the outside from the DQ pin. The DQ pin (DQ terminal) is a plurality of pins, so-called a plurality of I / O terminals. The data strobe signals DQS and / DQS serve as trigger signals for latching data when data is input from the outside. The data mask signal DM is a control signal for masking data, for example. When the data mask signal DM is set to High simultaneously with the input of data, writing of the data to the memory cell is masked (inhibited) and writing is not performed. The data mask signal DM is an external terminal of the semiconductor device and includes a plurality of data mask signal DM terminals. Each data mask signal DM is associated with one of a plurality of groups formed of a plurality of corresponding DQ terminals.

  When writing data to the memory cell, when the data mask signal DM is set to Low and data is input to the DQ pin, the write data is transferred to the sense amplifier (SA) via the input / output interface 6 and the data latch circuit 5. The sense amplifier (SA) drives the bit line (BL) according to the write data, and writes data to the memory cell connected to the bit line (BL) and connected to the selected word line.

  FIG. 2 is a diagram illustrating an example of a typical configuration of the sense amplifier (SA). FIG. 2 shows a part of the bit line system of the shared sense amplifier circuit (SA). The word line is driven by the sub word driver circuit 14. In the memory cell MC, the gate electrode is connected to the word line, one of the drain or source diffusion layers is connected to the NMOS transistor connected to the bit line, and one end is connected to the other of the source or drain diffusion layers of the NMOS transistor. A capacitor Cs whose end is connected to a power source (plate electrode) is provided.

  Although not particularly limited, the DRAM data transfer system shown in FIG. 2 has a hierarchical structure in which a bit line is connected to a local IO line via a Y switch and further connected to a main IO line (global IO line). It is said. The memory cell MC connected to the illustrated word line is connected to the bit line BLT, and the memory cell connected to the adjacent word line (not shown) is a folded bit connected to the bit line BLB complementary to the BLT. A line. The sense amplifier circuit (SA) connected between the bit line pair (BLT / B) has a source commonly connected to the PCS line, a PMOS transistor pair whose gate and drain are cross-connected, and a source commonly connected to the NCS line. In addition, an NMOS transistor pair in which a gate and a driver are cross-connected is provided. A drain of the PMOS transistor pair and a drain of the NMOS transistor pair are connected to each other and connected to the bit line pair (BLT / B). A pair of True and Bar bit lines BLT and BLB is also expressed as BLT / B.

  In FIG. 2, the bit line pair (BLT / BLB) of the memory mat 0 (11) shown on the upper side of the figure and the bit line pair (BLT / BLB) of the memory mat 1 (13) shown on the lower side are between them. The arranged sense amplifier (SA) 12 is shared. Between the sense amplifier circuit (SA circuit) and the bit line pair on the memory mat 0 (11) side, a pass transistor (NMOS transistor) whose on (conductive) and off (non-conductive) are controlled by the control signal SHRB0. And a pass transistor (NMOS) between the sense amplifier (SA) and the bit line pair on the memory mat 1 (13) side, which is controlled to be turned on (conductive) / off (non-conductive) by the control signal SHRB1. Transistor). The bit line pair BLT / B on the memory mat 0 (11) side includes three NMOS transistors whose gates are connected to the control signal BLEQT0 and are controlled to be on (conductive) and off (non-conductive). ), A circuit for precharging the bit line pair BLT / B from the precharge power supply and equalizing the bit line pair BLT / B of the memory mat 0 (11) is provided. Similarly, the bit line pair BLT / B on the memory mat 1 (13) side includes three NMOS transistors whose gates are connected to the control signal BLEQT1 to control on (conductive) and off (non-conductive). A circuit for precharging the bit line pair BLT / B from the precharge power supply and equalizing the bit line pair BLT / B of the memory mat 1 (13) when on (conductive) is provided.

  Further, the drain pair of the PMOS transistor pair and the NMOS transistor pair of the sense amplifier (SA) connected in common has a gate connected to the column selection signal YS and is controlled to be on (conductive) / off (non-conductive). It is connected to a local IO line pair (LIO line pair) via (NMOS transistor). A PMOS transistor 18 that inputs a control signal RSAEP1T to the gate is provided between the VARY power supply line of the memory array power supply and the PCS, and an NMOS transistor 20 that inputs the control signal RSAENT to the gate is provided between the VSSSA power supply line and the NCS. Between the PCS and the NCS, there are provided a precharge circuit that is turned on (conductive) when the control signal EQCS is High, precharges the PCS and the NCS, and an equalize circuit 19 that equalizes the PCS and the NCS.

  FIG. 3 is a diagram schematically showing the configuration of the data transfer method (hierarchical IO method) in the memory array 1 of FIG. In FIG. 3, RWBUS is a trunk wiring for performing intra-chip data transfer. A bus driver (BUDD) <k> 301 is a kth bus driver circuit connected to RWBUS. A main amplifier circuit (MA) <k> 302 for amplifying data on the MIO lines (complementary MIOT and MIOB) is connected to the bus driver circuit <k> 301.

  The main amplifier circuit <k> 302 is connected to the kth MIO line pair MIOT <k>, MIOB <k> in the array. The main amplifier circuit (MA) <k> 302 is differentially connected to the MIO line pair MIOT <k> and MIOB <k>, and is connected to the bus driver (BUSD) <k> 301. At the time of writing, a write amplifier (not shown) of the main amplifier circuit (MA) <k> 302 receives an output from the bus driver (BUDD) <k> 301 and outputs a differential output signal to the MIO line pair MIOT <k>, Output to MIOB <k>. At the time of reading, the data amplifier (not shown) of the main amplifier circuit (MA) <k> 302 receives the signals of the MIO line pair MIOT <k> and MIOB <k> differentially, converts them to the CMOS level, and converts them into a bus driver. (BUSD) <k> 301 is output.

  M + 1 SWC circuits 303 (SWC <0> to SWC <m>)) are connected to the MIO line pairs (MIOT <k>, MIOB <k>). SWC is a cross portion of the MIO line pair and the LIO line pair.

  Among the m + 1 SWC circuits 303 (SWC <0> to SWC <m>), sense amplifier arrays SA <0> and SA <1 for reading data from the word line WL selected by decoding the row address signal. >, SA <0>,... The logic is configured so that the SWC circuits corresponding to SA <n> are selected and the others are not selected. SWC <0> is connected to LIO line pair LIOT <0>, LIOB <0>. SWC <1> is connected to LIO line pair LIOT <1>, LIOB <1>. Similarly, SWC <m> is connected to LIO line pair LIOT <m>, LIOB <m>.

  In FIG. 3, when the word line WL is selected, SWC <0> (303) is selected. The LIO line is controlled by the n + 1 Y switch control signals (column selection signals) YS <0> to YS <n> from the column decoder to control the conduction / non-conduction of the Y switch. One of <0> to SA <n> is selected, and one selected sense amplifier SA is connected. The Y switch pair of each column is connected between the bit line pair BLT / B and the local IO line pair LIOT / N, and the NMOS transistor pair having the gate electrode connected in common and connected to the Y switch control signal YS. Consists of.

  In DRAMs, redundant cells are provided to repair defective cells, and repair measures are taken, such as creating a fail map by determining good or defective in the wafer test process during semiconductor manufacturing, and replacing defective cells with redundant cells. The As an example of the remedy, for example, when the access address corresponds to the address of the defective cell, programming such as fusing of the fuse circuit is performed so as to replace the redundant cell with the address to access so as not to access the defective cell, When selecting a redundant cell, control is performed so that the Y switch (relieved Y switch) of the bit line (relieved bit line) connected to the defective cell (relieved cell) and the word line are not selected (inactive). Is done. That is, the gate electrode of the Y switch to be repaired Y switch connected to the bit line to be repaired is fixed to the low potential by the Y switch control signal and is not selected.

  When the gate electrode of the Y switch floats due to a connection failure such as a via that transmits the Y switch control signal to the gate electrode of the Y switch, the gate electrode of the Y switch becomes disconnected from the Y switch control signal. It becomes impossible to discharge the charge of the gate electrode to GND. For this reason, the gate electrode of the Y switch becomes a high potential (or the gate-source voltage of the NMOS transistor constituting the Y switch exceeds the threshold voltage) due to capacitive coupling or the like when the potential of the adjacent wiring or the like fluctuates. The Y switch that should not be selected may become conductive. In this case, both the Y switch that should not be selected and the Y switch of the selected bit line to be read are selected, causing a problem that control becomes impossible. This problem will be described below with reference to FIG. FIG. 8 is a diagram created by the inventors of the present application for explaining the problem.

  The local IO line pair Local-I / O_T / B is connected to the main IO line pair via a switch circuit (SWC in FIG. 3). Local-I / O_T / B is connected to bit selection via the Y switch. A memory cell MC is provided at the intersection of the bit line and the word selection WL. Bit selection is performed by a column decoder (not shown), the Y switch control signal corresponding to the selected column is set to High, and the Y switch having the gate electrode connected to the Y switch control signal is turned on. At the time of data reading, the sense amplifier SA differentially amplifies the difference potential of the bit line pair, and the potential of the selected bit line is differentially output to Local-I / O_T / B. In FIG. 8, for the sake of simplicity, the sense amplifier SA is schematically shown in a single-end input and single-end output inverter format (when one of the Local-I / O_T / B is High, the other is Low). However, it is constituted by a differential latch circuit connected between bit lines as in the sense amplifier circuit (SA circuit) shown in FIG.

  The Y switch control signal supplied to the gate electrode of the Y switch (read Y-Switch) selected at the time of reading is set to the High potential, and the selected cell MC (word line WL) connected to the selected bit line (read BitLine). High) is read out to the bit line, and High and Low are originally output to Local-I / O_T / B via the Y switch (High expectation, Low expectation).

  On the other hand, the gate electrode of the Y switch (repaired Y-Switch) connected to the repaired bit line (repaired BitLine) is fixed to the GND potential (Fix Low) by the Y switch control signal. As indicated by an X in FIG. 8, due to poor connection of the via connected to the gate electrode, it is not fixed low, and becomes a high potential in a floating state and becomes conductive when the Y switch is not selected. . As a result, the data (Low) of the memory cell MC connected to the rescued bit line and the selected word line and its inverted signal are output to Local-I / O_T, B.

  The original read value (expected value) of Local-I / O_T / B should be High, but this time, the data (Low) of the selected cell connected to the bit line to be repaired is read at the same time. The value is Low. Note that Local-I / O_B is High, which is an inverted signal of Local-I / O_T.

  FIG. 9 is a diagram illustrating the layout image of the circuit of FIG. FIG. 9 is a diagram created by the inventors of the present application for explaining the problem. As shown in FIG. 9, the gate of the repaired Y switch is fixed to Low (FIX Low), but does not become Low even when not selected (Floating High) due to a Y-switch control signal and contact failure. For this reason, the Y switch connected in common to the selected word line WL and in which the data (Low) of the memory cell connected to the read bit line and the data (High) of the memory cell connected to the bit line to be repaired are turned on. To Local-I / O_T / Bar. The original read value (expected value) of Local-I / O_T should be High, but the data (Low) of the selected cell connected to the bit line to be repaired is simultaneously read and connected to the main IO line. The data amplifier in the main amplifier is determined to be Low.

  FIG. 10 is a timing chart showing an operation example of FIG. FIG. 10 is a diagram created by the inventors of the present application for explaining the problem. In FIG. 10, LIOT / N is a LOCAL_IOT / B, and LIOPREA is a LIOT / N precharge control signal. When LIOT / N is Low, LIOT / N is precharged and equalized to the precharge power supply voltage VDD. In FIG. 10, for ease of explanation, READ / WRITE access is set to the same four clock cycles.

  In Write Cycle (write cycle), the write amplifier in the main amplifier connected to the main IO line MIO is driven to High / Low based on the write data supplied from the external data terminal, and is connected to the main IO line MIO. The IO line LION / T is changed from the precharge voltage VDD to a high potential and a low potential corresponding to the write data. The broken line waveform represents an example of the transition of the potential of the gate electrode in the floating state of the Y switch connected to the unselected relief bit line. In the last one clock cycle of Write Cycle, the control signal LIOPREA for controlling the precharge of the local IO line LION / T is set to Low, and the local IO line LIOT / N is precharged and equalized to the precharge voltage.

  In Read Cycle (read cycle), the gate potential (floating gate) of the Y switch connected to the non-selected relief bit line is set to the high potential (floating high) by charge accumulation due to coupling of nearby signal wirings and the like. Reach. For this reason, the Y switch connected to the unselected relief bit line becomes conductive, and the multi-select state where both the Y switch of the selected read bit line and the Y switch of the unselected relief bit line become conductive. . In the last clock cycle of Read Cycle, LIOPREA is set to Low, and LIOT / N is precharged and equalized to the precharge voltage. Note that FIG. 10 shows an example in which the gate electrode rises to the high potential in the Read Cycle as the waveform (broken line) of the gate electrode that is followed, but the potential of the gate electrode is the threshold voltage. Is exceeded, the non-selected Y switch is turned on.

  As described above, when a Y switch in which the gate electrode is floated due to a contact failure such as a via connected to the gate electrode is detected in the wafer test process, the column is replaced with a redundant column by a well-known redundancy function. On the other hand, even if the Y switch control signal is controlled to be non-selected (Low), the node of the gate electrode of the Y switch is floating, and the I / O line is communicating with the redundant Y switch by coupling. A disturb is given to the (local IO line) (multi-selected state), resulting in an access failure to the redundant address.

  Note that in a Y switch in which the gate electrode is floated due to a contact failure or the like, the gate electrode is in a floating state and becomes a high selection state. In addition to the Y switch of the selected bit line, a non-selected Y switch (the gate electrode is The problem of the multi-select state that both floating high) are selected can occur in any Y switch shown in FIG. Furthermore, since the multi-selection state occurs when the gate-source voltage VGS of the unselected Y switch (NMOS transistor) exceeds the threshold voltage, the time axis is not limited and may occur at any time. For example, when a multi-selection state occurs in WRITE CYCLE, a non-selected Y switch is turned on, and data may be written to a memory cell of a non-selected bit line that is electrically connected to the local IO line by the Y switch.

  Note that Patent Document 1 discloses a configuration of a semiconductor memory device that reduces the bit line capacitance by reducing the number of bit line contacts in the sense amplifier portion. FIGS. A configuration is disclosed in which a switch control signal (CSL) is supplied to the gate electrodes of eight transistors via respective vias.

JP-A-10-313101

  As described above, when the gate electrode of the Y switch is floating, the level is slightly increased due to the coupling of the nearby wiring, etc., but is pushed up, and the Y switch with the gate floating due to charge accumulation becomes conductive. As a result, the multi-selection state is selected in which both the Y switch of the selected bit line and the Y switch of the non-selected bit line are selected, and disturb is applied to the IO line for reading from the selected bit line, and control becomes impossible. . With recent progress in miniaturization of semiconductor manufacturing, it is essential to cope with problems such as floating of the gate electrode due to contact failure or the like (knowledge by the present inventors).

  In order to solve at least one of the above-described problems, the present invention is generally configured as follows.

  According to one aspect of the present invention, a first transistor that electrically connects a second node and a third node according to the potential of the first node, and a first signal to the first node A first via to be supplied and a control connected to the first node, set the first node to a predetermined potential in response to a second signal, and electrically disconnects the first transistor A second transistor for controlling the second node to a predetermined potential in a first period (period), and activating the second signal to activate the first signal. The second period (period) in which the node is set to a predetermined potential corresponds to the first period (period) in which the equalizing circuit is activated.

According to another aspect of the present invention, a first data line connected directly or indirectly to a memory cell;
A second data line provided in common to the plurality of first data lines and transmitting data to and from the selected first data line;
Provided corresponding to each of the plurality of first data lines, connected between the first data line and the second data line, and connected between the first data line and the second data line. A first switch transistor having a gate electrode connected to a selection control signal for controlling electrical conduction and non-conduction;
A circuit provided corresponding to the second data line and precharging the second data line in response to activation of a precharge signal;
A control circuit including a second switch transistor that performs control to short-circuit the gate electrode of the first transistor to the first power supply regardless of the potential of the selection control signal;
The first power supply has a voltage for turning off the first transistor in which the first power supply voltage is applied to the gate electrode,
The control circuit makes the first switch transistor conductive when the precharge signal is activated and precharges the second data line based on a signal associated with the precharge signal. A semiconductor device is provided in which the gate electrode of the transistor is short-circuited to the first power source and is controlled to be non-conductive when the precharge signal is inactivated.

  According to the present invention, it is possible to avoid a multi-selection state in which both the Y switch of the selected bit line and the Y switch of the non-selected bit line are selected.

It is a figure which shows the structural example of DRAM. It is a figure which shows the structure of a bit line system. It is a figure which shows the structure of a hierarchical IO system typically. FIG. 10 illustrates one embodiment of the present invention. It is a figure explaining another aspect of this invention. It is a figure explaining exemplary embodiment of the present invention. FIG. 6 illustrates timing waveforms for an exemplary embodiment of the present invention. It is a figure explaining related technology. It is a figure explaining the layout of related technology. It is a figure which shows the timing waveform of related technology.

  A typical example of a preferred mode of the present invention that solves the problems of the present invention (Preferred Modes) is shown below. Referring to FIG. 4, according to one of the preferred embodiments of the present invention (Preferred Modes), the second node (node2) and the third node (node3) are connected to each other according to the potential of the first node (node1). A first transistor (Tr. 1) connected to the first node, a first via (Via. 1) for supplying a first signal to the first node (node 1), and a first node (node 1) In response to the second signal, the second transistor (Tr. 2) for controlling the first transistor (Tr. 1) to be electrically non-conductive and the second node (node 2) are first connected. And an equalizing circuit (EQ) that controls to a predetermined potential in a period (first period or first timing), and an activation period (second period, second period) of the second signal , The second timing) It corresponds to one period (first period, or the first timing).

  In an example of the aspect of the present invention, a third transistor (Tr. 3) that potential-connects the second node (node 2) and the fifth node (node 5) according to the potential of the fourth node (node 4). , A control circuit (CNTL) for controlling the third transistor (Tr.3), and when the control circuit (CNTL) controls the third transistor (Tr.3) to be electrically conductive, The first signal is controlled so as to control the first transistor (Tr. 1) to be electrically non-conductive.

  In an example of the aspect of the present invention, the control circuit (CNTL) electrically controls the first transistor (Tr.1) when the third transistor (Tr.3) is electrically controlled. The first signal is controlled so as to be controlled to be non-conductive. The control circuit (CNTL) includes an address associated with the third node (node3) and a determination circuit (not shown) that compares information regarding whether or not the address is a defective address. The control circuit (CNTL) controls bidirectional communication of information between the third node and the fifth node and the second node.

  In an example of the aspect of the present invention, the period in which the second transistor (Tr. 2) is electrically conductive is at least a period in which the equalization circuit (EQ) controls the second node to the predetermined potential. It is some period.

  In one example of an aspect of the present invention, the third and fifth nodes (node3, node5) are nodes associated with the corresponding first and second memory cells, respectively, and the second node (node2) is A node related to an external terminal of the semiconductor device.

  In one example of an aspect of the present invention, the first and second memory cells have the same address, and the second memory cell is replaced with a defective (FAIL) first memory cell. It is.

  In one example of an aspect of the present invention, the third and fifth nodes are nodes of bit lines connected to the corresponding plurality of memory cells, respectively, and the first signal is related to a decoded address. The second node (node2) is a local data line.

  In one example of an aspect of the present invention, the hierarchical data line includes a local data line (Local IO) and one global data line (MIO in FIG. 3) related to the plurality of local data lines, The fifth node (node3, node5) is the local data line (Local IO), and the second node (node2) is the global data line (MIO). In this case, in FIG. 3, the first transistor (Tr. 1) is a switch transistor in the SWC that controls the connection between LIO and MIO, and the third transistor (Tr. 3) is a connection between another LIO and MIO. A switch transistor in another SWC that controls the above is configured.

  In an example of the aspect of the present invention, the output of the second transistor (Tr. 2) is commonly connected to the first node 1 (node 1) and the fourth node (node 4), and corresponds to the second signal. The first and third transistors (Tr.1, Tr.3) may be configured to be electrically non-conductive in common. Alternatively, instead of the control circuit (CTRL), the gate electrode of the third transistor (Tr. 3) is connected to the third transistor via the via (via that electrically connects the gate electrode and the upper metal wiring layer). (Tr.3) is connected to another first signal (Y switch control signal output from the column decoder) for controlling conduction, and one end of the second transistor (Tr.2) is connected to the first node 1 (node1). ) And the fourth node (node4) in common, and the first and third transistors (Tr.1, Tr.3) are electrically non-conductive in response to the second signal. It is good also as a structure controlled to.

  Hereinafter, an example in which the present invention is applied to a DRAM having a hierarchical bit line configuration having LIOT / N (Local-I / O_T / B) described with reference to FIG. 1, FIG. 2, FIG. However, it goes without saying that the present invention is not limited to such a configuration. However, it is needless to say that the claimed contents of the present application are not limited to this preferred mode, but are the contents described in the claims of the present application.

  As described above, the potential of the gate of the Y switch connected to the Local-I / O is controlled by the Y switch control signal at one contact, but it is representative of the preferred embodiment of the present invention (Preferred Modes). According to a typical example, the gate of the Y switch is connected to a signal controlled by a signal that precharges the Local-I / O in addition to the Y switch control signal at two points. The gate can be controlled. As a result, even if the connection point between the Y switch gate electrode and the Y switch control signal is floating due to a contact failure or the like, it is electrically connected to GND at the other point of the gate electrode. The potential of the gate electrode is forcibly set to the GND potential. As a result, an unintended operation (problem) that the gate electrode of the Y switch becomes floating high and the Y switch becomes conductive can be suppressed.

  Local-I / O precharges and equalizes to the precharge power supply voltage, and at the same time, the transistor (N1) connected between the gate electrode of the Y switch and GND is made conductive to lower the gate electrode of the Y switch to the GND level. Thus, the gate potential of the floating Y switch is returned to Low, and the Y switch is prevented from becoming conductive.

  FIG. 6 is a diagram showing the configuration of an embodiment of the present invention. As shown in FIG. 6, the gate electrode of the Y switch is connected by two contacts. That is, the Y switch control signal from the column decoder and the signal (1) connected to the drain terminal of the NMOS transistor N1 whose source is connected to GND (ground).

  Between Local-I / O_T / B, the PMOS transistor P1 whose gate is connected to LIOPREA, the source is connected to the precharge power supply terminal VBLP, the drain is connected to Local-I / O_T / B, and the gate is A precharge / equalize circuit including PMOS transistors P2 and 3 connected to LIOPREA is provided. LIOPREA is generated by inverting the Local-I / O precharge control signal with the inverter INV. Further, an NMOS transistor N1 connected between the common gate of the Y switch of Local-I / O_T / B and the GND and receiving a Local-I / O precharge control signal at the gate is provided. When the Local-I / O precharge control signal is High, LIOPREA is Low, the PMOS transistors P1, P2, and P3 are turned on, the Local-I / O_T / B is precharged and equalized, and the NMOS transistor N1 is In order to conduct (turn on), the common gate of the Y switch of Local-I / O_T / B is set to the GND potential.

  When the Local-I / O precharge signal is Low, LIOPREA is High, the NMOS transistor N1 is non-conductive (OFF), LIOPREA is High, and the PMOS transistors P1, P2, and P3 are non-conductive.

  At the time of Local-I / O precharge and equalization, the gate potential of the Y switch for controlling the connection between the Local-I / O and the bit line is set to Low, so that the common gate of the Y switch Even when the common gate of the Y switch floats due to a contact failure that propagates the switch control signal, by setting the GND potential forcibly at the precharge performed every access cycle, a plurality of different column addresses can be set. The Y switch is prevented from being selected at the same time.

  FIG. 7 is a timing diagram showing the operation of one embodiment of the present invention. A clock signal CK (/ CK), a voltage waveform of LIOT / N, a voltage waveform of LIOPREA and its inverted signal (1) are shown. In a few clock cycles of WRITE CYCLE, LIOPREA is set to High, PMOS transistors P1 to P3 connected to LIOT / N are turned off, NMOS transistor N1 is turned off, and LIOT / N based on write data. Is driven high / low. The Y switch of the selected column connected to LIOT / N becomes Y switch control signal High and the Y switch is turned on, LIOT / N write data is transferred to the selected bit line, and the memory cell of the selected word line Write data is stored in the capacity.

  In the fourth clock cycle of WRITE CYCLE, LIOPREA is set to Low, PMOS transistors P1 to P3 connected to LIOT / N are turned on (conductive), and LIOT / N is set to precharge power supply voltage and precharge / equalize. Is done. In this fourth clock cycle, the bit line pair is also precharged and equalized to a precharge power supply voltage by a precharge equalizing circuit provided between the bit line pairs.

  The signal (1) input to the gate of the NMOS transistor N1 becomes High (a complementary signal to LIOPREA), the NMOS transistor N1 is turned on (conductive), and the common gate of the Y switch connected to LIOT / N is set to the GND potential. Is done. That is, the contact (via) connecting the Y switch control signal to the common gate of the Y switch connected to LIOT / N has a defect, and the gate of the Y switch floats, as shown in FIG. 7 as the Y switch gate level. Even if the potential gradually rises due to coupling with a nearby signal line or the like, the NMOS transistor N1 is forcibly set to the GND potential by turning on (conducting). In FIG. 7, WRITE CYCLE and READ CYCLE are four clock cycles, but the present invention is not limited to such a configuration. The precharge may be performed based on, for example, an input of a precharge command that is input following an ACT command (bank active) or a READ / WRITE command.

  In the next READ CYCLE, LIOPREA becomes High, the NMOS transistor N1 is turned off, the common gate of the Y switch is in a floating state, and even if the potential gradually rises again, in the fourth cycle of READ CYCLE, LIOPREADA becomes Low. The signal (1) input to the gate of the NMOS transistor N1 becomes High (signal (1) is a complementary signal of LIOPREA), the NMOS transistor N1 is turned on (conductive), and the Y switch connected to LIOT / N These common gates are set to the GND potential. The PMOS transistors P1 to P3 connected to LIOT / N are turned on (conductive), and LIOT / N is precharged and equalized to the precharge power supply voltage.

  That is, in the READ CYCLE, when the LIOT / N difference potential is read (the LIOT / N difference potential transferred to the main IO MIO is differentially amplified by the data amplifier), the potential of the common gate of the Y switch is The threshold voltage of the NMOS transistor constituting the Y switch is not reached. For this reason, the non-selected Y switch is turned off. As a result, in READ CYCLE, the occurrence of a situation in which the Y switch connected to the unselected bit line (the gate is in a floating state) and the Y switch connected to the selected bit line are simultaneously set to the conductive state is avoided. Is done.

  In the present embodiment, the source is connected to GND with respect to the gate electrode of the Y switch pair (Y-Switch in FIG. 3) that controls the connection between the bit line pair of the memory array and the LIOT / N. The control signal (1) from the drain of the NMOS transistor N1 that inputs the IO precharge signal to the gate is connected to the gate electrode at a connection point different from the connection point between the Y switch control signal and the gate electrode ( The gate electrode of the Y switch is controlled at two points). At that time, in correspondence with the LIOT / N precharge / equalization circuits (P1, P2, P3), one NMOS transistor N1 for inputting a Local-IO precharge signal to the gate is provided, and the local IO line pair LIOT / N is provided. The control signal (1) from the drain of the one NMOS transistor N1 is connected in common to the gate electrodes of the plurality of Y switch pairs connected to the plurality of bit line pairs connected to each other, and the local IO line pair Of course, the gate electrodes of a plurality of Y switch pairs may be simultaneously reset to the GND potential during LIOT / N precharge. That is, one NMOS transistor N1 that resets the gate electrode of the Y switch pair to the GND potential at the time of precharging may be provided for a plurality of Y switch pairs. Alternatively, it is needless to say that one NMOS transistor N1 may be provided near each Y switch pair, and a Local-IO precharge signal may be connected to the gate of each NMOS transistor N1 by wiring.

  The technical idea of the present application can be applied to, for example, a data signal transmission route of a memory or a data processor. Further, the circuit format such as the generation method of the signal (1) for forcibly setting the gate electrode of the Y switch to the low potential and the circuit for generating other control signals are not limited to the circuit formats disclosed in the embodiments. . In addition, the first transistor Tr. Although the Y switch in which 1 is an NMOS transistor has been described as an example, the first transistor Tr. 1 is a PMOS transistor, the second transistor Tr. 2 is turned on, the first transistor Tr. 1 is set to the power supply voltage (VDD), and the first transistor Tr. 1 is turned off.

  The technical idea of the present invention can be applied to various semiconductor devices. For example, a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), and an ASP (Amplified Semiconductor). The present invention can be applied. Examples of the product form of the semiconductor device to which the present invention is applied include SOC (system on chip), MCP (multichip package), and POP (package on package). The present invention can be applied to a semiconductor device having any of these product forms and package forms. The transistor may be a field effect transistor (FET). In addition to a MOS (Metal Oxide Semiconductor), a transistor such as a MIS (Metal-Insulator Semiconductor) or a TFT (Thin Film Transistor) may be used. it can. It can be applied to various FETs such as transistors. Furthermore, some bipolar transistors may be included in the device. Further, the PMOS transistor (P-type channel MOS transistor) is a second conductivity type transistor, and the NMOS transistor (N-type channel MOS transistor) is a typical example of the first conductivity type transistor.

  The present invention can be modified or adjusted within the scope of the entire disclosure (including claims) of the present invention and based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Memory array 2 X decoder and X timing generation circuit 3 Y decoder and Y timing generation circuit 4 Decoder control circuit 5 Data latch circuit 6 Input / output interface 7 Internal clock (CLK) generation circuit 8 Control signal generation circuit 9 DLL (Delay Locked Loop) : Delay locked loop)
11 Memory mat 0
12 Sense amplifier section 13 Memory mat 1
14 Sub-word driver circuit 18 PMOS transistor 19 Equalize circuit 20 NMOS transistor 301 Bus driver (BUSD)
302 Main amplifier (MA)
303 SWC circuit 304 Sense amplifier (SA)

Claims (10)

A first transistor that potentialally connects the second node and the third node according to the potential of the first node;
A first via for supplying a first signal to the first node;
A second transistor connected to the first node and electrically non-conductively controlled in response to a second signal;
An equalizing circuit for controlling the second node to a predetermined potential in a first period;
And the second period of the second signal corresponds to the first period. A third transistor for potential-connecting the second node and the fifth node according to the potential of the fourth node;
A control circuit for controlling the third transistor;
With
2. The control circuit according to claim 1, wherein the control circuit controls the first signal to control the first transistor to be electrically non-conductive when the third transistor is controlled to be electrically conductive. Semiconductor device.   3. The semiconductor device according to claim 2, wherein the period in which the second transistor is electrically conductive is at least a part of a period in which the equalizing circuit controls the second node to the predetermined potential.   The control circuit includes a determination circuit that compares an address associated with the third node and information regarding whether or not the address is a defective address, and the control circuit corresponds to a determination result of the determination circuit. 4. The semiconductor device according to claim 2, wherein bidirectional communication of information between the second node and one of the third node and the fifth node is selectively controlled. The second period of the second signal is changed to the first period and corresponds to the period of the first signal,
5. The semiconductor device according to claim 4, wherein the period in which the second transistor is electrically conductive is at least a part of a period in which the first signal controls the first transistor to be inactive. The third and fifth nodes are nodes associated with corresponding first and second memory cells, respectively;
The semiconductor device according to claim 4, wherein the second node is a node related to an external terminal of the semiconductor device. The first and second memory cells have the same address;
The semiconductor device according to claim 6, wherein the second memory cell is a memory cell that is replaced with the first memory cell associated with the defective first via. The third and fifth nodes are bit line nodes connected to the corresponding plurality of the memory cells, respectively.
The first signal is a signal associated with a decoded address;
The semiconductor device according to claim 6, wherein the second node is a local data line. A hierarchical data line including a local data line and one global data line related to the plurality of local data lines, wherein the third and fifth nodes are the local data lines, Are the global data lines,
The semiconductor device according to claim 6, wherein the first signal is a signal related to a decoded address. A first data line connected directly or indirectly to the memory cell;
A second data line provided in common to the plurality of first data lines and transmitting data to and from the selected first data line;
Provided corresponding to each of the plurality of first data lines, connected between the first data line and the second data line, and connected between the first data line and the second data line. A first switch transistor having a gate electrode connected to a selection control signal for controlling electrical conduction and non-conduction;
A circuit provided corresponding to the second data line and precharging the second data line in response to activation of a precharge signal;
A control circuit including a second switch transistor that performs control to short-circuit the gate electrode of the first transistor to the first power supply regardless of the potential of the selection control signal;
The first power supply has a voltage for turning off the first transistor in which the first power supply voltage is applied to the gate electrode,
The control circuit makes the second switch transistor conductive when the precharge signal is activated to precharge the second data line based on a signal associated with the precharge signal, and A semiconductor device, wherein a gate electrode of one transistor is short-circuited to the first power supply and controlled to be non-conductive when the precharge signal is inactivated.

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