JP2011258733A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

The heat dissipation efficiency of a WLP heat spreader is improved.
A semiconductor device includes a semiconductor substrate having an integrated circuit on a main surface side, a wiring formed on an insulating film coated on a passivation film, an electrode, and an electrode other than the electrode. And a heat spreader 30 provided on the back surface 11 b of the semiconductor substrate 11. The edge portion 33 of the heat spreader 30 protrudes from the edge of the back surface 11 b of the semiconductor substrate 11.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  As a semiconductor chip packaging method, there is a so-called WLP (Wafer Level Package) method. In the WLP method, after forming a wiring and a sealing resin layer on the main surface of the semiconductor wafer on which the integrated circuit is formed, the semiconductor wafer is diced together with the sealing resin layer to obtain individual chips. (For example, Patent Document 1).

  In order to dissipate heat generated from the integrated circuit inside the chip, a heat spreader such as a metal film is provided on the back surface of the semiconductor chip (see, for example, Patent Document 1). In the WLP method, after sealing the main surface of a semiconductor wafer, a metal film is formed on the back surface of the semiconductor wafer by vapor deposition or the like, and then the sealing resin layer, the semiconductor wafer, and the metal film are diced (for example, patents). Reference 1).

JP 2005-158929 A

  Incidentally, it is desired to further improve the heat dissipation efficiency by the heat spreader. Therefore, the problem to be solved by the present invention is to increase the heat radiation efficiency by the heat spreader.

  In order to solve the above-described problems, a semiconductor device according to the present invention includes a semiconductor substrate having an integrated circuit on one surface, and a heat spreader provided on the other surface of the semiconductor substrate. The edge portion protruded from the edge of the other surface of the semiconductor substrate.

Preferably, the surface of the heat spreader is uneven.
Preferably, the heat spreader is made of a metal such as copper or aluminum.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is partitioned into a plurality of chip regions, and the other surface of the semiconductor wafer having an integrated circuit on one surface for each of the chip regions. A heat spreader is provided, and a groove is formed along the boundary line by cutting from one surface of the semiconductor wafer to the other surface or halfway through the heat spreader along the boundary line of the chip region. The heat spreader was cut along the groove with a narrow cut width.

Preferably, a sealing layer is formed on one surface of the semiconductor wafer before the heat spreader is provided on the other surface of the semiconductor wafer.
Preferably, the surface of the heat spreader is uneven.
Preferably, the heat spreader is made of a metal such as copper or aluminum.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention has an edge portion protruding from the edge of the semiconductor substrate on the other surface of the semiconductor substrate having an integrated circuit on one surface. Form a heat spreader.

  Preferably, a heat dissipation member larger than the heat spreader is partitioned into a plurality of chip regions, and each chip region is provided on the other surface of the semiconductor wafer having an integrated circuit on one surface, and a boundary between the chip regions Cutting along one line from one surface of the semiconductor wafer to the other surface or halfway through the heat dissipation member to divide the semiconductor wafer into a plurality of the semiconductor substrates and form grooves along the boundary line; The heat radiating member is cut along the groove with a cut width narrower than the groove, and the heat radiating member is divided into the heat spreaders.

  According to the present invention, since the portion near the edge of the heat spreader protrudes from the edge of the back surface of the semiconductor substrate, the area of the heat spreader is larger than the area of the back surface of the semiconductor substrate. Therefore, the heat dissipation efficiency by the heat spreader is improved.

The perspective view of the semiconductor device in the embodiment of the present invention. Sectional drawing of the semiconductor device in the embodiment. The perspective view and sectional drawing in 1 process of the method of manufacturing the semiconductor device in the embodiment. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG. The perspective view and sectional drawing in the process following FIG.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated using drawing. However, the embodiments described below are given various technically preferable limitations for carrying out the present invention, but the scope of the present invention is not limited to the following embodiments and illustrated examples.

[Configuration of semiconductor device]
FIG. 1 is a perspective view showing the semiconductor device 1. FIG. 2 is a cross-sectional view showing the semiconductor device 1. This semiconductor device 1 is packaged in a chip size (so-called CSP: Chip Size Package). The semiconductor device 1 includes a semiconductor substrate 11, a passivation film 13, an insulating film 14, a wiring base 21, a wiring 23, an electrode 25, a sealing layer 26, a solder bump 27, a heat spreader 30, and the like.

  The semiconductor substrate 11 is obtained by dividing a semiconductor wafer. The semiconductor substrate 11 is made of a semiconductor material such as silicon. The main surface 11a of the semiconductor substrate 11 is a surface on the front side, and an integrated circuit is formed on the surface layer on the main surface 11a side. A plurality of connection pads 15 are formed on the main surface 11 a of the semiconductor substrate 11. The connection pad 15 is a part of the wiring of the integrated circuit formed on the surface layer on the main surface 11a side. A main surface 11 a of the semiconductor substrate 11 is covered with a passivation film 13. The passivation film 13 is made of silicon oxide or silicon nitride. A passivation film 13 is covered with an insulating film 14. The insulating film 14 is made of an epoxy resin, a polyimide resin, or other resin. For example, the insulating film 14 may be made of a high-functional plastic material such as polyimide (PI) or polybenzoxazole (PBO), a plastic material such as epoxy, phenol, or silicon, or a composite material thereof. .

  An opening 13 a is formed at a position of the passivation film 13 that overlaps the connection pad 15. An opening 14 a is formed in the insulating film 14 at a position overlapping the connection pad 15. The connection pad 15 is located in the openings 13 a and 14 a, and a part or the whole of the connection pad 15 is not covered with the passivation film 13 and the insulating film 14. Note that the insulating film 14 may be omitted.

  A conductive pattern 20 is formed on the insulating film 14 (on the passivation film 13 when there is no insulating film 14). The conductive pattern 20 includes a wiring base 21 and a wiring (upper layer conductor) 23, the wiring base 21 is formed on the insulating film 14, and the wiring 23 is formed on the wiring base 21.

  The wiring substrate 21 is obtained by patterning a seed layer. The wiring substrate 21 is a copper (Cu) thin film, a titanium (Ti) thin film, a thin film in which copper is laminated on titanium, or other metal thin films. The wiring substrate 21 is formed in a predetermined shape. A part of the wiring substrate 21 is laminated on the connection pad 15, and the wiring substrate 21 is connected to the connection pad 15 through the openings 13 a and 14 a.

  The wiring 23 is made of copper plating or other metal plating. In plan view, the wiring 23 is patterned into a predetermined shape, and the planar shape of the wiring 23 and the planar shape of the wiring substrate 21 are substantially the same. The wiring 23 is thicker than the wiring base 21. The conductive pattern 20 may not be a laminate of the wiring base 21 and the wiring 23. For example, the conductive pattern 20 may be a single layer of conductor, or may be a laminate of more conductor layers than two layers.

  An electrode 25 is formed on one end of the wiring 23. The electrode 25 is a post electrode provided in a column shape. The electrode 25 is made of copper or other metal. The height (thickness) of the electrode 25 is larger than the thickness of the wiring 23. A portion of the wiring 23 that serves as a base for the electrode 25 is a land 24.

A light-shielding sealing layer 26 is formed on the insulating film 14, and the wiring 23 is covered with the sealing layer 26. The top surface of the electrode 25 is not covered by the sealing layer 26, but the peripheral side surface of the electrode 25 is protected by the sealing layer 26. The surface of the sealing layer 26 is provided flush with the top surface of the electrode 25 or is slightly higher than the top surface of the electrode 25.
The sealing layer 26 is made of an epoxy resin, a polyimide resin, or other insulating resin, and is preferably made of a thermosetting resin (eg, epoxy resin) containing a filler (eg, glass filler).

  Solder bumps 27 are formed on the top surface of the electrodes 25. The solder bump 27 and the electrode 25 are electrically connected to each other by bonding the solder bump 27 to the top surface of the electrode 25. The solder bump 27 may not be provided.

  The back surface 11b of the semiconductor substrate 11 is the opposite surface of the main surface 11a. A heat spreader 30 is fixed to the back surface 11b. The heat spreader 30 may be directly attached to the back surface 11b of the semiconductor substrate 11, or may be bonded to the back surface 11b of the semiconductor substrate 11 with a heat conductive adhesive. The heat spreader 30 is made of a material having higher heat dissipation than the material (silicon) of the semiconductor substrate 11. For example, the heat spreader 30 is made of a metal such as copper or aluminum. The heat spreader 30 is, for example, a plate shape, a film shape, a sheet shape, or a laminated body, and heat generated from an integrated circuit or the like of the semiconductor substrate 11 is dissipated by the heat spreader 30.

  The surface 30 a of the heat spreader 30, that is, the lower surface of the heat spreader 30 is provided unevenly. Thereby, the heat dissipation performance of the heat spreader 30 is improved.

  Specifically, a plurality of protrusions 32 are arranged in a matrix by forming lattice-shaped grooves 31 on the surface 30a of the heat spreader 30. In addition, the shape of the groove | channel 31 does not need to be a grid | lattice form. For example, if the groove 31 is striped, a plurality of parallel protrusions are formed on the surface 30 a of the heat spreader 30. Moreover, the groove | channel 31 may not be formed in the surface 30a of the heat spreader 30, but the surface 30a may be a flat surface.

  When viewed in a plan view, the heat spreader 30 is larger than the semiconductor substrate 11, and the edge portion 33 of the heat spreader 30 protrudes laterally from the edge 11 c of the back surface 11 b of the semiconductor substrate 11. Thereby, the heat dissipation efficiency by the heat spreader 30 improves. Therefore, even when the heat generation amount in the semiconductor substrate 11 is large, the semiconductor substrate 11 can dissipate heat.

  Further, since the heat spreader 30 is fixed to the back surface 11b of the semiconductor substrate 11, the semiconductor substrate 11 can be reinforced. In particular, the bending strength of the semiconductor device 1 is improved.

  In addition, although the sealing layer 26 of the semiconductor device 1 shown in FIGS. 1 and 2 is thick and the electrode 25 is provided in a columnar shape, the sealing layer 26 may be thin. When the sealing layer 26 is thin, there is no electrode 25, an opening is formed in a portion of the sealing layer 26 that overlaps the land 24, and a solder bump 27 is formed on the land 24 in the opening. 27 protrudes from the opening.

[Manufacturing Method of Semiconductor Device (First Method)]
A method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 3 to 13 show the manufacturing process of the semiconductor device 1, (a) in FIGS. 3 to 13 is a perspective view of the semiconductor wafer 50, and (b) is a partial sectional view of the semiconductor wafer 50. is there.

  When the semiconductor device 1 is manufactured, a semiconductor wafer 50 (shown in FIG. 3) before being singulated is used. As shown in FIG. 3, the semiconductor wafer 50 is partitioned into a plurality of chip regions 51 by lattice-shaped dicing streets (boundary lines) 52 as planned division lines. These chip regions 51 are arranged in a matrix. An integrated circuit is formed for each chip region 51 on the surface layer of the semiconductor wafer 50 on the main surface 50a side. On the main surface 50a of the semiconductor wafer 50, a plurality of connection pads 15 are formed. A passivation film 13 is formed on the main surface 50 a of the semiconductor wafer 50, and an insulating film 14 is formed on the passivation film 13. Openings 13a and 14a are formed in the passivation film 13 and the insulating film 14, and the connection pads 15 are exposed in the openings 13a and 14a. On the back surface 50b of the semiconductor wafer 50, a semiconductor (for example, silicon) is exposed. Note that the insulating film 14 may be omitted.

  As shown in FIG. 4, a seed is formed on the entire surface of the insulating film 14 (or the passivation film 13 when there is no insulating film 14) by electroless plating, vapor phase growth (for example, sputtering) or a combination thereof. Layer 61 is deposited. The seed layer 61 also grows on the inner wall surfaces of the openings 13 a and 14 a and the connection pad 15. The seed layer 61 is a copper (Cu) thin film, a titanium (Ti) thin film, a thin film in which copper is laminated on titanium, or another metal thin film.

Next, as shown in FIG. 5, the wiring 23 is patterned. Specifically, a mask such as a resist is set on the seed layer 61, and electrolytic plating is performed using the seed layer 61 as an electrode in a state where the seed layer 61 is partially covered with the mask. In the mask, an opening corresponding to the position and shape of the wiring 23 to be formed is formed, and the wiring 23 is grown on the seed layer 61 in the opening of the mask by electrolytic plating. The wiring 23 is grown thicker than the seed layer 61. In the case where the mask is a resist, an opening is formed in the resist by exposure and development.
After the wiring 23 is formed, the mask is removed.

Next, the electrode 25 is formed. Specifically, a mask made of a dry film resist or the like thicker than the wiring 23 is placed on the seed layer 61 and the wiring 23, and the seed layer 61 and the wiring 23 are placed with the seed layer 61 and the wiring 23 covered with the mask. Electrolytic plating is performed as an electrode. In the mask, openings corresponding to the position and shape of the electrode 25 to be formed are formed, and these openings overlap the lands 24 provided at the end of the wiring 23. Therefore, the electrode 25 grows on the land 24 and in the opening of the mask by electrolytic plating. Here, the electrode 25 is grown so that the height (thickness) of the electrode 25 is sufficiently thicker than the thickness of the wiring 23. In the case where the mask is a dry film resist, an opening is formed in the dry film resist by exposure and development.
After the formation of the electrode 25, the mask is removed.

  After removing the mask, the portion of the seed layer 61 that does not overlap the wiring 23 is removed by etching, so that the seed layer 61 is processed into the wiring base 21 as shown in FIG. At this time, the surfaces of the wiring 23 and the electrode 25 are partially etched, but the wiring 23 and the electrode 25 remain because the wiring 23 and the electrode 25 are sufficiently thicker than the seed layer 61. The conductive pattern 20 and the electrode 25 may be formed by a subtracting method or an additive method other than those described above.

  Next, the sealing layer 26 is formed over the entire insulating film 14 (the passivation film 13 when there is no insulating film 14). Specifically, a sealing resin is applied on the insulating film 14 (the passivation film 13 when there is no insulating film 14), the wiring 23 and the electrode 25 are covered with the sealing resin, and the sealing resin is applied. Is cured. In this state, since the electrode 25 is embedded in the sealing layer 26, the surface of the sealing layer 26 is ground. By grinding the surface of the sealing layer 26, the top surface of the electrode 25 is exposed, and the surface of the sealing layer 26 is substantially flush with the top surface of the electrode 25. At this time, the top surface of the electrode 25 is also ground, and the top surface of the electrode 25 becomes flat. Note that the prepreg may be attached to the insulating film 14 (or the passivation film 13 in the case where the insulating film 14 is not provided), and the prepreg may be cured to form the sealing layer 26.

After forming the sealing layer 26, the back surface 50b of the semiconductor wafer 50 is ground by a grinder or the like, and the top surface of the electrode 25 is lightly etched. These grinding steps and etching steps may not be performed.
Then, as shown in FIG. 7, solder bumps 27 are formed on the top surface of the electrode 25.

  Next, as illustrated in FIG. 8, the solder bump 27 is protected by the protective material 66 by covering the sheet-shaped protective material 66 from above the solder bump 27. Although a gap is formed between the protective material 66 and the sealing layer 26 as shown in FIG. 8, the protective material 66 may be in close contact with the sealing layer 26. It is preferable that the protective material 66 is adhesive / flexible and loses its adhesiveness by ultraviolet rays. The protective material 66 may not be covered.

  Next, as shown in FIG. 9, a heat dissipation member 70 is provided on the back surface 50 b of the semiconductor wafer 50. Specifically, the heat radiating member 70 is formed by depositing a metal material on the back surface 50b of the semiconductor wafer 50 by vapor phase growth (for example, sputtering or vapor deposition). Or the heat radiating member 70 previously formed in the shape of a thin plate or a sheet is bonded to the back surface 50b of the semiconductor wafer 50 with a heat conductive adhesive. The heat radiating member 70 may be provided on the back surface 50 b of the semiconductor wafer 50 by other methods. The heat radiating member 70 is a base of the heat spreader 30 and is a heat spreader larger than the heat spreader 30.

  Next, as shown in FIG. 10, the surface 70 a of the heat radiating member 70 is made uneven by shaping the surface 70 a of the heat radiating member 70. Specifically, a mask (for example, a resist by a photoresist method) is installed on the surface 70a of the heat radiating member 70, and the surface 70a of the heat radiating member 70 is etched with the heat radiating member 70 partially covered by the mask. Thus, the groove 31 is formed. Alternatively, the groove 31 is formed on the surface 70a of the heat radiating member 70 by sandblasting. Alternatively, the groove 31 is formed by half dicing the heat dissipation member 70 from the surface 70 a of the heat dissipation member 70. In addition, the surface 70a of the heat radiating member 70 may not be uneven.

  Next, the protective material 66 is peeled off. For example, the protective material 66 is peeled off by irradiating the protective material 66 with ultraviolet rays.

  Next, as shown in FIG. 11, the heat dissipating member 70 faces the dicing tape 80, the heat dissipating member 70 is attached to the dicing tape 80, and a dicing frame 81 is installed around the semiconductor wafer 50.

Next, the stacked body of the heat dissipation member 70, the semiconductor wafer 50, and the sealing layer 26 is separated into a plurality of semiconductor devices 1.
Specifically, first, as shown in FIG. 12, the sealing layer 26 and the semiconductor wafer 50 are half-diced along the dicing street 52 by the first dicing blade. As a result, lattice-like grooves 65 along the dicing street 52 are formed in the sealing layer 26 and the semiconductor wafer 50. In the half dicing, cutting is performed from the surface of the sealing layer 26 to the middle of the heat radiating member 70, but not to the surface 70a of the heat radiating member 70. The depth of cut with respect to the heat radiating member 70 is preferably 30 μm from the interface between the semiconductor wafer 50 and the heat radiating member 70. By such half dicing, the semiconductor wafer 50 is divided into a plurality of semiconductor substrates 11, and the sealing layer 26 is divided for each semiconductor substrate 11. Note that the groove 65 may be cut from the front surface of the sealing layer 26 to the back surface 50b of the semiconductor wafer 50 to reduce the depth of the groove 65.

  Next, as shown in FIG. 13, the heat radiating member 70 is cut along the dicing street 52 by the second dicing blade thinner than the first dicing blade and thinner than the width of the groove 65. When cutting, the heat radiating member 70 is divided into a plurality of heat spreaders 30 by cutting from the bottom of the groove 65 to the surface 70 a of the heat radiating member 70. Since the second dicing blade is thinner than the width of the groove 65, the width of the notch 74 of the heat radiating member 70 is narrower than the width of the groove 65. Therefore, the edge portion 33 of the divided heat spreader 30 can be protruded from the edge 11 c of the back surface 11 b of the semiconductor substrate 11.

  According to the manufacturing method as described above, the heat spreader 30 can be provided in a plurality of semiconductor devices 1 by dicing the semiconductor wafer 50, the sealing layer 26, and the heat dissipation member 70, so that productivity is improved. To do.

[Manufacturing Method of Semiconductor Device (Second Method)]
In the first method, the heat dissipation member 70 is provided on the back surface 50 b of the semiconductor wafer 50 after the solder bumps 27 are formed.
On the other hand, in the second method, the solder bumps 27 are formed after the heat radiation member 70 is provided on the back surface 50 b of the semiconductor wafer 50. Hereinafter, the second method will be specifically described.

  The steps until the sealing layer 26 is formed are the same as those in the first method (see FIGS. 3 to 6). Thereafter, as shown in FIG. 14, a heat dissipation member 70 is provided on the back surface 50 b of the semiconductor wafer 50. Next, as shown in FIG. 15, the surface 70 a of the heat radiating member 70 is made uneven by shaping the surface 70 a of the heat radiating member 70. These steps are the same as in the case of the first method.

Next, as shown in FIG. 16, solder bumps 27 are formed on the top surface of the electrodes 25.
Next, the stacked body of the heat dissipation member 70, the semiconductor wafer 50, and the sealing layer 26 is separated into a plurality of semiconductor devices 1. This step is the same as in the case of the first method (see FIGS. 12 and 13).

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Semiconductor substrate 11a Main surface 11b Back surface 11c Edge 26 Sealing layer 30 Heat spreader 30a Surface 31 Groove 32 Protrusion 33 Edge part 50 Semiconductor wafer 50a Main surface (one surface)
50b Back side (the other side)
51 Chip area 52 Dicing street 65 Groove 70 Heat dissipation member 70a Surface

Claims (9)

A semiconductor substrate having an integrated circuit on one side;
A heat spreader provided on the other surface of the semiconductor substrate;
With
A semiconductor device, wherein a portion near the edge of the heat spreader protrudes from an edge of the other surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein a surface of the heat spreader is uneven.   The semiconductor device according to claim 1, wherein the heat spreader is made of a metal such as copper or aluminum. A plurality of chip regions, and a heat spreader is provided on the other surface of the semiconductor wafer having an integrated circuit on one surface for each of the chip regions;
Cut along the boundary line of the chip region from one surface of the semiconductor wafer to the other surface or halfway through the heat spreader to form a groove along the boundary line,
A method of manufacturing a semiconductor device, comprising cutting the heat spreader along the groove with a cut width narrower than the groove.   5. The method of manufacturing a semiconductor device according to claim 4, wherein a sealing layer is formed on one surface of the semiconductor wafer before the heat spreader is provided on the other surface of the semiconductor wafer.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the surface of the heat spreader is formed to be uneven.   The method of manufacturing a semiconductor device according to claim 4, wherein the heat spreader is formed of a metal such as copper or aluminum.   A method of manufacturing a semiconductor device, comprising: forming a heat spreader having an edge portion protruding from an edge of the semiconductor substrate on the other surface of the semiconductor substrate having an integrated circuit on one surface. A heat dissipating member larger than the heat spreader is partitioned into a plurality of chip regions, and provided on the other surface of the semiconductor wafer having an integrated circuit on one surface for each chip region,
The semiconductor wafer is divided into a plurality of the semiconductor substrates and cut along the boundary line by cutting from one surface of the semiconductor wafer to the other surface or halfway of the heat radiating member along the boundary line of the chip region. Forming grooves,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the heat radiating member is cut along the groove with a cut width narrower than the groove, and the heat radiating member is divided into the heat spreaders.

Images