JP2011257667A - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

Stable sustain discharge is generated in a plasma display panel and unnecessary radiation is suppressed.
A power recovery unit that causes a sustain-side sustain pulse to rise or fall by resonating an interelectrode capacitance and an inductor, and clamps a sustain-side sustain pulse voltage to a third voltage V63 or a fourth voltage (-V63). And a scan electrode drive circuit having a scan side clamp unit that clamps the voltage of the scan side sustain pulse to the first voltage V53 or the second voltage (−V53). The sustain side sustain pulse rises or falls using the power recovery unit, and the sustain side voltage is set to the third voltage or the fourth voltage using the sustain side clamp unit after ½ time of the resonance period has elapsed. Clamp to the voltage, and clamp the scan electrode voltage to the second voltage or the first voltage using the scan side clamp unit at the same time or after the sustain electrode voltage clamp. Te, generating the sustain discharge.
[Selection] Figure 9

Description

  The present invention relates to a method for driving a plasma display panel and a plasma display apparatus using the same.

  A typical plasma display panel (hereinafter abbreviated as “panel”) as a display device includes a front substrate on which a plurality of display electrode pairs each composed of a pair of scan electrodes and sustain electrodes are formed, and a plurality of data electrodes. A plurality of discharge cells are formed between the rear substrate and the rear substrate. Then, ultraviolet rays are generated by gas discharge in the discharge cell, and the phosphors of red, green and blue colors are excited and emitted by the ultraviolet rays to perform color display.

  As a method for driving the panel, a subfield method in which one field period is divided into a plurality of subfields and gray levels are displayed by a combination of subfields to emit light is generally used. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. To display an image.

  Various technologies for reducing power consumption have been proposed for plasma display devices using such panels. Focusing on the fact that the display electrode pair is a capacitive load as one of the techniques for reducing the power consumption particularly during the sustain period, the display electrode pair is driven by resonating the interelectrode capacitance of the display electrode pair and the inductor. A so-called power recovery circuit is disclosed (for example, see Patent Document 1).

JP 11-242458 A

  Since the power recovery circuit described above operates by resonance, the drive impedance is relatively high. Therefore, if a discharge occurs during the operation of the power recovery circuit, a large voltage drop may occur and the sustain discharge may become unstable. Conventionally, in order to stably generate a sustain discharge, the resonance of the power recovery circuit is interrupted halfway and switched to a clamp circuit with a low drive impedance to supply a sustain pulse voltage to the display electrode pair.

  However, if the resonance of the power recovery circuit is interrupted halfway, unnecessary radiation increases. Therefore, there has been a problem that new components must be added to suppress unnecessary radiation.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a panel driving method and a plasma display device that generate stable sustain discharge and suppress unnecessary radiation.

  According to the present invention, a scan-side sustain pulse having a first voltage and a second voltage is applied to a scan electrode, and a third voltage and a second voltage are applied to the sustain electrode. A panel driving method for generating a sustain discharge in a discharge cell by applying a sustain-side sustain pulse having four voltages, wherein the scan-side clamp clamps the voltage of the scan-side sustain pulse at a first voltage or a second voltage. A scan electrode driving circuit having a power supply unit, a power recovery unit that causes the sustain side sustain pulse to rise or fall by resonating the interelectrode capacitance between the scan electrode and the sustain electrode and the inductor, and the voltage of the sustain side sustain pulse And a sustain electrode drive circuit having a sustain side clamp section that clamps to the third voltage or the fourth voltage, and using the power recovery section, the sustain side sustain pulse rises or falls. After the half of the resonance period of the inter-capacitance and the inductor has elapsed, the sustain-side clamp unit is used to clamp the sustain electrode voltage to the third voltage or the fourth voltage, simultaneously with the sustain electrode voltage clamp. Alternatively, a sustain discharge is generated by clamping the scan electrode voltage to the second voltage or the first voltage using the scan-side clamp unit. By this method, it is possible to provide a panel driving method that generates stable sustain discharge and suppresses unnecessary radiation.

  In the panel driving method of the present invention, the inductance of the inductor may be set so that the resonance period between the interelectrode capacitance and the inductor is shorter than twice the discharge delay time of the sustain discharge.

  The present invention also provides a panel including a plurality of discharge cells each having a scan electrode and a sustain electrode, a scan electrode driving circuit for applying a scan-side sustain pulse having a first voltage and a second voltage to the scan electrode, and a sustain electrode A sustain electrode driving circuit for applying a sustain side sustain pulse having a third voltage and a fourth voltage to the scan electrode sustain circuit, wherein the scan electrode sustain circuit determines the voltage of the scan side sustain pulse as the first voltage or the first voltage. The sustain electrode driving circuit includes a scan-side clamp unit that clamps to two voltages, and the sustain electrode drive circuit resonates the interelectrode capacitance between the scan electrode and the sustain electrode and the inductor to cause the sustain-side sustain pulse to rise or fall A recovery unit and a sustain side clamp unit that clamps the voltage of the sustain side sustain pulse to the third voltage or the fourth voltage, and the rise of the sustain side sustain pulse using the power recovery unit or The voltage of the sustain electrode is clamped to the third voltage or the fourth voltage by using the sustain-side clamp unit after a time ½ of the resonance period between the interelectrode capacitance and the inductor has elapsed, and the sustain electrode A sustain discharge is generated by clamping the voltage of the scan electrode to the second voltage or the first voltage using the scan-side clamp unit at the same time as or after the clamp. With this configuration, it is possible to provide a plasma display device that generates stable sustain discharge and suppresses unnecessary radiation.

  In the plasma display device of the present invention, the inductance of the inductor may be set so that the resonance period between the interelectrode capacitance and the inductor is shorter than twice the discharge delay time of the sustain discharge.

  According to the present invention, it is possible to provide a panel driving method and a plasma display device that generate stable sustain discharge and suppress unnecessary radiation.

It is a disassembled perspective view of the panel of the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel of the plasma display apparatus. It is a circuit block diagram of the plasma display device. It is a circuit diagram of the data electrode drive circuit of the plasma display device. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. It is a circuit diagram of the sustain electrode drive circuit of the plasma display device. It is a drive voltage waveform figure of the plasma display apparatus. It is a circuit block diagram for demonstrating the operation | movement in the sustain period of the plasma display apparatus. It is a figure which shows the detail of the sustain pulse of the plasma display apparatus. It is a figure which shows the detail of the sustain pulse of the plasma display apparatus in Embodiment 2 of this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. In the present embodiment, a discharge gas with a xenon partial pressure of 10% is used to improve luminance. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. In panel 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) that are long in the row direction are arranged and long in the column direction. m data electrodes D1 to Dm (data electrode 22 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi (i = 1 to n) intersects with one data electrode Dj (j = 1 to m). , M × n discharge cells are formed in the discharge space. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  FIG. 3 is a circuit block diagram of plasma display device 30 according to the first exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 31 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the respective circuit blocks.

  FIG. 4 is a circuit block diagram of data electrode drive circuit 32 of plasma display device 30 according to the first exemplary embodiment of the present invention. The data electrode drive circuit 32 includes a reference potential setting unit 41 and an address pulse generation unit 44. The reference potential setting unit 41 includes a switching element Q41 and a switching element Q42, and sets the potential of the node P44, which is the reference potential of the write pulse generation unit 44, to the negative voltage V41 or the ground potential. The write pulse generator 44 includes a power supply E44 of a positive voltage V44 superimposed on the potential of the node P44, switching elements Q4H1 to Q4Hm for applying a high voltage side voltage of the power supply E44 to the data electrodes D1 to Dm, and a power supply E44. Switching elements Q4L1 to Q4Lm for applying the low-voltage side voltage to the data electrodes D1 to Dm. Then, the image data for each subfield is converted into address pulses corresponding to the data electrodes D1 to Dm and applied to the data electrodes D1 to Dm.

  FIG. 5 is a circuit block diagram of scan electrode drive circuit 33 of plasma display device 30 according to the first exemplary embodiment of the present invention. Scan electrode drive circuit 33 includes sustain pulse generator 50, ramp voltage generator 55, ramp voltage generator 56, reference potential setting unit 57, and scan pulse generator 59.

  Sustain pulse generation unit 50 includes a scanning-side clamp unit 53 having a switching element Q53 and a switching element Q54. Then, a scan-side sustain pulse having a positive voltage V53 and a negative voltage V54 is output to the node P59 that is the reference potential of the scan pulse generator 59.

  The ramp voltage generator 55 generates an up-ramp voltage that rises to a positive voltage V55 and outputs it to the node P59. The ramp voltage generator 56 generates a down-ramp voltage that decreases to a negative voltage V56 and outputs it to the node P59. The reference potential setting unit 57 includes a switching element Q57 that sets the voltage at the node P59 to a negative voltage V57, and a switching element Q58 that sets the ground potential, that is, 0 (V).

  Scan pulse generating unit 59 applies power source E59 of positive voltage V59 superimposed on the reference potential of scan pulse generating unit 59, and switching elements Q5H1 to Q5Hn for applying a high voltage side voltage of power source E59 to scan electrodes SC1 to SCn. And switching elements Q5L1 to Q5Ln for applying the voltage on the low voltage side of the power supply E59 to the scan electrodes SC1 to SCn. Then, a scan pulse is applied to each scan electrode SC1 to SCn.

  FIG. 6 is a circuit block diagram of sustain electrode drive circuit 34 of plasma display device 30 according to the first exemplary embodiment of the present invention. Sustain electrode drive circuit 34 includes a sustain pulse generation unit 60 and a voltage application unit 65.

  Sustain pulse generating unit 60 includes a power recovery unit 61 having a capacitor C61, a switching element Q61, a switching element Q62, a diode D61, a diode D62, and an inductor L61, and a sustaining side clamp unit 63 having a switching element Q63 and a switching element Q64. And sustain-side sustain pulses having a positive voltage V63 and a negative voltage V64 are output to sustain electrodes SU1 to SUn. The capacitor C61 has a capacity sufficiently larger than the interelectrode capacity Cp, and is charged to an intermediate potential between the voltage V63 and the voltage V64, that is, the voltage ((V63 + V64) / 2). Work as.

  Voltage application unit 65 includes a switching element Q65 that outputs positive voltage V65 to sustain electrodes SU1 to SUn, and a switching element Q66 that outputs a ground potential.

  Next, a driving method for driving the panel 10 will be described. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. The initializing operation at this time includes a forced initializing operation for forcibly generating an initializing discharge in all the discharge cells and a selective initializing operation for generating an initializing discharge in the discharge cells that have generated a sustain discharge. . In the address period, a scan pulse is applied to the scan electrodes SC1 to SCn and an address pulse is selectively applied to the data electrodes D1 to Dm, and an address discharge is selectively generated in the discharge cells to emit light to form wall charges. To do. In the sustain period, a number of scan-side sustain pulses and sustain-side sustain pulses corresponding to the luminance weight are applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn to generate sustain discharges in the discharge cells that have generated address discharges. To emit light. At this time, a pulse voltage in phase with the sustain-side sustain pulse is also applied to the data electrodes D1 to Dm. Hereinafter, the scan-side sustain pulse and the sustain-side sustain pulse are also simply referred to as “sustain pulse”.

  In the present embodiment, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is, for example, (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). Further, the subfield SF1 is a subfield for performing a forced initialization operation, and the subsequent subfields SF2 to SF10 are subfields for performing a selective initialization operation. However, in the present invention, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 7 is a drive voltage waveform diagram of plasma display device 30 according to the first exemplary embodiment of the present invention, and shows drive voltage waveforms applied to each electrode of the panel in each subfield.

  In the first half of the initializing period of subfield SF1, switching element Q42 and switching elements Q4L1 to Q4Lm are turned on to apply 0 (V) to data electrodes D1 to Dm, switching element Q66 is turned on and sustain electrodes SU1 to SUn. 0 (V) is applied to. Then, switching element Q58 is turned on, the potential at node P59 is set to 0 (V), switching elements Q5H1 to Q5Hn are turned on, and voltage V59 is applied to scan electrodes SC1 to SCn. Next, switching element Q58 is turned off, and ramp voltage generator 55 is operated. Then, the potential at the node P59 rises gradually toward the voltage V55. In this way, a ramp voltage that gradually increases toward voltage (V59 + V55) is applied to scan electrodes SC1 to SCn. While this ramp voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, and a wall voltage is accumulated on each electrode. . Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the second half of the initialization period, switching element Q66 is turned off, switching element Q65 is turned on, and voltage V65 is applied to sustain electrodes SU1 to SUn. Then, ramp voltage generator 55 is turned off, switching element Q53 is turned on, switching elements Q5H1 to Q5Hn are turned off, and Q5L1 to Q5Ln are turned on to apply voltage V53 to scan electrodes SC1 to SCn.

  Thereafter, switching element Q53 is turned off and ramp voltage generator 56 is operated. Then, the potential at the node P59 gradually decreases toward the voltage V56. In this way, a ramp voltage that gradually decreases toward voltage V56 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge occurs again during this period, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  Thus, in the initializing period of subfield SF1, a forced initializing operation for forcibly generating initializing discharge in all the discharge cells is performed.

  In the address period of subfield SF1, voltage V65 is continuously applied to sustain electrodes SU1 to SUn. Then, the switching element Q57 is turned on to set the potential of the node P59 to the negative voltage V57, the switching elements Q5L1 to Q5Ln are turned off, and the switching elements Q5H1 to Q5Hn are turned on, whereby the voltages (V57 + V59) are applied to the scan electrodes SC1 to SCn. Is applied.

  Next, the switching element Q5H1 is turned off and the switching element Q5L1 is turned on, so that the scan pulse of the negative voltage V57 is applied to the scan electrode SC1 in the first row. Then, the switching element Q4Lk of the address pulse generator 44 corresponding to the data electrode Dk (k = 1 to m) of the discharge cell to be lit in the first row among the data electrodes D1 to Dm is turned off and the switching element Q4Hk is turned on. Then, an address pulse of voltage V44 is applied to the data electrode Dk. Then, in the discharge cells in the first row, address discharge occurs in the discharge cells to which the address pulse is applied, and an address operation for accumulating wall voltage on each electrode is performed. On the other hand, no address discharge occurs in the discharge cells to which no address pulse is applied. In this way, the write operation is selectively performed. Thereafter, switching element Q5L1 is turned off and switching element Q5H1 is turned back on.

  Next, the switching element Q5H2 is turned off and the switching element Q5L2 is turned on to apply a scan pulse to the scan electrode SC2 in the second row, and the data electrode of the discharge cell to emit light in the second row among the data electrodes D1 to Dm. An address pulse is applied to Dk. Then, address discharge occurs selectively in the discharge cells in the second row. The above address operation is performed up to the discharge cell in the nth row.

  Thereafter, switching elements Q5H1 to Q5Hn of scan pulse generator 59 are turned off, switching element Q57 is turned off, switching element Q58 is turned on, switching elements Q5L1 to Q5Ln are turned on, and 0 (V) is applied to scan electrodes SC1 to SCn. To do.

  Although details will be described later in the sustain period of subfield SF1, a scan-side sustain pulse of positive voltage V53, which is the first voltage, is applied to scan electrodes SC1 to SCn, and the fourth voltage is applied to sustain electrodes SU1 to SUn. A sustain side sustain pulse having a negative voltage V64 is applied. Further, the voltage V41 is also applied to the data electrodes D1 to Dm. Then, a sustain discharge is generated in the discharge cell that has caused the address discharge in the address period.

  Next, a scan-side sustain pulse of negative voltage V54 that is the second voltage is applied to scan electrodes SC1 to SCn, and a sustain-side sustain pulse of positive voltage V63 that is the third voltage is applied to sustain electrodes SU1 to SUn. . Further, a voltage (V41 + V44) is also applied to the data electrodes D1 to Dm. Then, a sustain discharge is generated in the discharge cell that has caused the address discharge in the address period.

  Here, the sustain side sustain pulse amplitude (V63-V64) is set larger than the scan side sustain pulse amplitude (V63-V64).

  In the same manner, a sustain side having a first voltage V53 and a second voltage V54 is applied to scan electrodes SC1 to SCn, and a sustain side having a third voltage V63 and a fourth voltage V64 is applied to sustain electrodes SU1 to SUn. A sustain pulse is applied, and a pulse voltage is also applied to the data electrodes D1 to Dm. As a result, a sustain discharge is continuously generated in the discharge cells that have caused the address discharge in the address period. Here, the number of sustain pulses applied to each electrode is set according to the luminance weight.

  The reason for applying the pulse voltage to the data electrodes D1 to Dm is as follows. Assuming that a constant voltage is applied to the data electrodes D1 to Dm in the sustain period, the sustain side sustain pulse has a large amplitude (V63-V64), so that the data electrodes D1 to Dm and the sustain electrode regardless of the presence or absence of the address discharge. There is a risk of discharge occurring between SU1 and SUn. When discharge occurs regardless of the presence or absence of address discharge, images cannot be displayed normally. Therefore, in the present embodiment, a pulse voltage having the same phase as the sustain side sustain pulse is also applied to the data electrodes D1 to Dm to suppress the discharge between the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn.

  In order to apply the voltage V41 to the data electrodes D1 to Dm, the switching element Q42 is turned off, the switching elements Q4H1 to Q4Hm are turned off, the switching element Q41 is turned on, and the switching elements Q4L1 to Q4Lm are turned on. In order to apply the voltage (V41 + V44) to the data electrodes D1 to Dm, the switching element Q42 is turned off, the switching elements Q4L1 to Q4Lm are turned off, the switching element Q41 is turned on, and the switching elements Q4H1 to Q4Hm are turned on.

  At the end of the sustain period, switching element Q41 of data electrode driving circuit 32 is turned off, switching elements Q4H1 to Q4Hm are turned off, switching element Q42 is turned on, switching elements Q4L1 to Q4Lm are turned on, and data electrodes D1 to Dm are set to 0. Apply (V). Further, all the switching elements of sustain pulse generating unit 60 of sustain electrode drive circuit 34 are turned off and switching element Q66 is turned on to apply 0 (V) to sustain electrodes SU1 to SUn. Then, the switching element Q53 of the scan electrode driving circuit 33 is turned off, the switching element Q54 is turned off, the switching element Q58 is turned on, and the ramp voltage generator 55 is operated to scan the ramp voltage that gradually increases toward the voltage V55. Apply to electrodes SC1 to SCn. Then, during this period, a weak erasing discharge occurs between scan electrode SCi that has generated sustain discharge and sustain electrode SUi, leaving positive wall voltage on data electrode Dk, and on scan electrode SCi and sustain electrode SUi. Reduce the wall voltage. Thus, an erasing operation for erasing wall charges for continuously generating the sustain discharge is performed. Thus, the maintenance operation in the maintenance period is completed.

  In the subsequent initialization period of subfield SF2, switching element Q66 of sustain electrode drive circuit 34 is turned off and switching element Q65 is turned on to apply voltage V65 to sustain electrodes SU1 to SUn. Then, switching element Q58 of scan electrode drive circuit 33 is turned on, Q5L1 to Q5Ln are turned on, and 0 (V) is applied to scan electrodes SC1 to SCn. Thereafter, switching element Q58 is turned off and ramp voltage generator 56 is operated. Then, the potential at the node P59 gradually decreases toward the voltage V56. In this way, a ramp voltage that gradually decreases toward voltage V56 is applied to scan electrodes SC1 to SCn. Then, initializing discharge is generated in the discharge cells in which the sustain discharge has been performed in the sustain period of subfield SF1. As described above, in the initialization period of the subfield SF2, the selective initialization operation for generating the initialization discharge in the discharge cells in which the sustain discharge has been performed is performed.

  The subsequent address period and sustain period are substantially the same as the address period and sustain period of the subfield SF1, and the description thereof is omitted. Subsequent subfields SF3 to SF10 are similar to the operation of subfield SF2 except for the number of sustain pulses.

  In this embodiment, voltage values applied to the electrodes are, for example, voltage V59 = 100 (V), voltage V55 = 180 (V), voltage V53 = 20 (V), voltage V54 = −20 (V). , Voltage V56 = −130 (V), voltage V57 = −140 (V), voltage V65 = 100 (V), voltage V63 = 160 (V), voltage V64 = −160 (V), voltage V41 = −120 ( V) and voltage V44 = 60 (V). However, these voltage values are merely an example, and it is desirable to set them to optimum values as appropriate according to the characteristics of the panel, the specifications of the plasma display device 30, and the like.

  Next, the details of the method for driving the panel 10 during the sustain period, which is the subject of the present invention, will be described.

  FIG. 8 is a circuit block diagram for explaining the operation in the sustain period of plasma display device 30 in the first exemplary embodiment of the present invention. FIG. 8 shows the interelectrode capacitance Cp of the panel 10, the sustain pulse generating unit 50 on the scan electrode side, and the sustain pulse generating unit 60 on the sustain electrode side, and other circuit blocks are omitted. The voltages V54 and V64 were set as V54 = − (V53) and V64 = − (V63).

  The sustain pulse generator 50 on the scan electrode side includes a scan clamp 53. However, it does not have a power recovery unit. The scanning side clamp unit 53 includes a switching element Q53 for clamping the scan electrodes SC1 to SCn to the voltage V53 and a switching element Q54 for clamping to the voltage (−V53). The scan-side clamp unit 53 is connected to the scan electrodes SC1 to SCn, which are one end of the interelectrode capacitance Cp, through a scan pulse generator 59 (not shown because it is in a short circuit state during the sustain period).

  Scanning side clamp unit 53 clamps scan electrodes SC1 to SCn to positive voltage V53 via switching element Q53, and clamps scan electrodes SC1 to SCn to negative voltage (−V53) via switching element Q54. In this way, the scanning-side clamp unit 53 clamps the voltage of the scanning-side sustain pulse to the first voltage V53 or the second voltage (−V53). Therefore, the impedance at the time of voltage application by the scanning side clamp unit 53 is small, and a large discharge current due to strong sustain discharge can be stably passed.

  In the present embodiment, the switching elements Q53 and Q54 are configured using IGBTs. However, other switching elements, for example, switching elements such as MOSFETs may be used.

  The sustain pulse generating unit 60 on the sustain electrode side includes a power recovery unit 61 and a sustain side clamp unit 63. The power recovery unit 61 includes switching elements Q61 and Q62, backflow prevention diodes D61 and D62, and a resonance inductor L61. Here, since ((V63 + V64) / 2) = 0, the capacitor C61 is omitted. In addition, sustain side clamp portion 63 has switching element Q63 for clamping sustain electrodes SU1 to SUn to positive voltage V63 and switching element Q64 for clamping to negative voltage (−V63). The power recovery unit 61 and the sustain side clamp unit 63 are connected to sustain electrodes SU <b> 1 to SUn that are one end of the interelectrode capacitance Cp of the panel 10.

  The power recovery unit 61 causes the interelectrode capacitance Cp between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn to resonate with the inductor L61 so that the sustain side sustain pulse rises or falls. At the rise of the sustain pulse, a current is passed from the ground potential via the switching element Q61, the diode D61, and the inductor L61, and the charge is transferred to the interelectrode capacitance Cp. When the sustain pulse falls, the charge stored in the interelectrode capacitance Cp is returned to the ground potential via the inductor L61, the diode D62, and the switching element Q62. In this way, the sustain side sustain pulse that changes from the positive voltage V63 to the negative voltage (−V63) rises and falls. Thus, since the power recovery unit 61 drives the sustain electrodes SU1 to SUn by resonance without being supplied with power from the power source, the power consumption is ideally “0”.

  Since the operation of the sustain side clamp unit 63 is the same as the operation of the scanning side clamp unit 53, description thereof is omitted.

  In the present embodiment, switching elements Q61 to Q54 are configured using IGBTs. However, other switching elements, for example, switching elements such as MOSFETs may be used.

  FIG. 9 is a diagram showing details of the sustain pulse of plasma display device 30 according to the first exemplary embodiment of the present invention, and also shows the current flowing through inductor L61, the discharge current, and the voltage at node P61.

  Here, one repetition period of the sustain pulse (hereinafter abbreviated as “sustain period”) is divided into four periods indicated by T11 to T14, and each period will be described.

(Period T11)
At time t11, the switching element Q61 of the power recovery unit 61 is turned on. Then, current starts to flow from the ground potential to the sustain electrodes SU1 to SUn through the switching element Q61, the diode D61, and the inductor L61, and the voltage of the sustain electrodes SU1 to SUn starts to rise. After 1/2 of the resonance period of inductor L61 and interelectrode capacitance Cp, the voltage of sustain electrodes SU1 to SUn rises to almost voltage V63, and the current flowing through inductor L61 becomes “0”.

  In the present embodiment, the resonance period of the inductor L61 and the interelectrode capacitance Cp is set to a time shorter than twice the discharge delay time. Therefore, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn exceeds the discharge start voltage during this period, but no sustain discharge occurs.

(Period T12)
At time t12 after the current flowing through the inductor L61 becomes “0”, the switching element Q63 of the sustain side clamp portion 63 is turned on. Then, the voltage of sustain electrodes SU1 to SUn is clamped at voltage V63. Further, the switching element Q53 of the scanning side clamp unit 53 is turned off and the switching element Q54 is turned on with a slight delay of δt. Then, the voltages of scan electrodes SC1 to SCn are clamped to voltage (−V53).

  When sustain electrodes SU1 to SUn are clamped to voltage V63 and scan electrodes SC1 to SCn are clamped to voltage (−V53), the voltage difference applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is It becomes a voltage (V53 + V63). In the discharge cell in which the address discharge has occurred, the voltage difference between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn exceeds the discharge start voltage, and a sustain discharge occurs after a time longer than the discharge delay time. .

  After the sustain discharge converges, switching elements Q61 and Q63 of sustain pulse generating unit 60 on the sustain side are turned off.

(Period T13)
At time t13, the switching element Q62 of the power recovery unit 61 is turned on. Then, current starts to flow from the sustain electrodes SU1 to SUn to the ground potential through the inductor L61, the diode D62, and the switching element Q62, and the voltage of the sustain electrodes SU1 to SUn starts to decrease. Then, after 1/2 of the resonance period between the inductor L61 and the interelectrode capacitance Cp, the voltage of the sustain electrodes SU1 to SUn drops to almost the voltage (−V63), and the current flowing through the inductor L61 becomes “0”.

  As described above, since the resonance period of inductor L61 and interelectrode capacitance Cp is set to a time shorter than twice the discharge delay time, scan electrodes SC1 to SCn and sustain electrodes are used in the discharge cells in which the address discharge has occurred. Although the voltage difference between SU1 and SUn exceeds the discharge start voltage during this period, no sustain discharge occurs.

(Period T14)
At time t14 after the current flowing through the inductor L61 becomes “0”, the switching element Q64 of the sustain side clamp portion 63 is turned on. Then, the voltage of sustain electrodes SU1 to SUn is clamped to the voltage (−V63). Further, the switching element Q54 of the scanning side clamp unit 53 is turned off and the switching element Q53 is turned on with a slight delay of δt. Then, the voltages of scan electrodes SC1 to SCn are clamped at voltage V53.

  When sustain electrodes SU1 to SUn are clamped to voltage (−V63) and scan electrodes SC1 to SCn are clamped to voltage V53, the voltage difference applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is The voltage is (−V53−V63). In the discharge cell in which the address discharge has occurred, the voltage difference between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn exceeds the discharge start voltage, and a sustain discharge occurs after a time longer than the discharge delay time. .

  After the sustain discharge converges, switching elements Q62 and Q64 of sustain pulse generating unit 60 on the sustain side are turned off.

  By repeating the operations in the above-described periods T11 to T14, sustain pulse generating units 50 and 60 in the present embodiment apply the necessary number of sustain pulses to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.

  As described above, in the present embodiment, after the sustain side sustain pulse rises or falls using the power recovery unit 61, and after a time ½ of the resonance period between the interelectrode capacitance Cp and the inductor L61 has elapsed. The sustain side clamp unit 63 is used to clamp the voltage of the sustain electrodes SU1 to SUn to the third voltage V63 or the fourth voltage V64, and the scan side clamp unit 53 is used after the sustain electrode SU1 to SUn is clamped. The voltage of scan electrodes SC1 to SCn is clamped at second voltage V54 or first voltage V53 to generate a sustain discharge.

  In the present embodiment, the resonance period between the inductor L61 and the interelectrode capacitance Cp is set to 600 nsec, and the lengths of the periods T11 and T13 are set to 300 nsec. The lengths of the period T12 and the period T14 are set to 2200 nsec. The slight time δt is 50 nsec.

  In the present embodiment, in period T12 and period T14, after the voltage of sustain electrodes SU1 to SUn is clamped, the voltage of scan electrodes SC1 to SCn is clamped with a slight delay of δt. However, scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn may be clamped before sustain pulses are generated in period T12 and period T14, and the voltages of scan electrodes SC1 to SCn and the voltages of sustain electrodes SU1 to SUn are substantially equal. You may clamp at the same time.

  As described in the period T11 to the period T14, in the present embodiment, the inductance of the inductor L61 is set so that the resonance period of the interelectrode capacitance Cp, the inductor, and L61 is shorter than twice the discharge delay time of the sustain discharge. is doing. The power recovery unit 61 is used to raise or fall the sustain pulse on the scanning side, and the current flowing through the inductor L61 is “0” after a time ½ of the resonance period between the interelectrode capacitance Cp and the inductor L61 has elapsed. After that, the sustain-side clamp unit 63 is used to clamp the voltage of the sustain electrodes SU1 to SUn at the third voltage V63 or the fourth voltage V64, and scanning is performed simultaneously with or after the sustain electrode SU1 to SUn is clamped. The sustain discharge is generated by clamping the voltage of the scan electrodes SC1 to SCn to the second voltage V54 or the first voltage V53 using the side clamp part 53. Thereby, unnecessary radiation can be suppressed and stable sustain discharge can be generated.

  The reason why unnecessary radiation is suppressed by driving the panel in this way will be described.

  When attention is paid to the voltage at the node P61 (nodes on the side of the diodes D61 and D62 of the inductor L61) of the power recovery unit 61 shown in FIG. 8, in the present embodiment, as shown in FIG. The voltage across the inductor L61 becomes equal at the time when the value becomes “0”. When the voltage at the node P61 rises to the voltage V63 and when the voltage at the node P61 falls to the voltage (−V63), the slight stray capacitance associated with the node P61 and the inductor L61 resonate and a high frequency of 30 MHz or higher. Ringing with components occurs. A sustain discharge occurs after the ringing begins to attenuate.

  On the other hand, according to the conventional driving method, ringing having a high frequency component is observed at one end of the inductor of the power recovery unit simultaneously with the occurrence of the sustain discharge or after the start of the sustain discharge.

  As a result, the timing at which ringing with a high frequency component occurs overlaps with the timing at which sustain discharge occurs, thereby increasing unnecessary radiation and shifting the timing at which ringing with a high frequency component occurs and the timing at which sustain discharge occurs. Therefore, it is assumed that unnecessary radiation can be suppressed. In this embodiment, since the sustain discharge is generated after the ringing having a high-frequency component starts to attenuate, the timing at which the ringing occurs and the timing at which the sustain discharge occurs are deviated and unnecessary radiation is suppressed. It is done.

  Further, in the present embodiment, after the voltage V63 or the voltage (−V63) is applied to the sustain electrodes SU1 to SUn using the sustain side clamp part 63, the scan side clamp part 53 is scanned after a slight delay of δt. A voltage (−V53) or a voltage V53 is applied to the electrodes SC1 to SCn. Therefore, a sustain discharge is generated at a timing when a voltage larger than the voltage applied using power recovery unit 61 is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. In other words, before applying the voltage (−V53) or the voltage V53 to the scan electrodes SC1 to SCn using the scan side clamp part 53, only a low voltage is present between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn. Since no voltage is applied, the discharge delay time is substantially increased. Therefore, the timing at which ringing occurs and the timing at which sustain discharge occurs are separated in time. Therefore, increasing the absolute values of voltage V53 and voltage (−V53) applied to scan electrodes SC1 to SCn is advantageous in suppressing unnecessary radiation. However, since sustain pulse generating unit 50 on the scan electrode side does not have a power recovery unit, increasing absolute values of voltage V53 and voltage (−V53) increases the power consumption of sustain pulse generating unit 50. Therefore, in this embodiment, by setting (voltage V53) ≈0.2 × (voltage V63), the sustain pulse amplitude on the scan electrode side is set to about 20% of the sustain pulse on the sustain electrode side. .

(Embodiment 2)
FIG. 10 is a diagram showing details of the sustain pulse of the plasma display device in accordance with the second exemplary embodiment of the present invention, and also shows the current flowing through inductor L61, the discharge current, and the voltage at node P61.

  The first difference between the second embodiment and the first embodiment is that the resonance period of the inductor L61 and the interelectrode capacitance Cp is not necessarily set to a time shorter than twice the discharge delay time. The second difference between the second embodiment and the first embodiment is that the absolute values of the sustain-side sustain pulse voltage V63 and voltage (−V63) are the same as the voltage V63 and voltage (−V63) of the first embodiment. The absolute value of the voltage V53 and the voltage (−V53) of the scan-side sustain pulse is set to be larger than the absolute value of the voltage V53 and the voltage (−V53) in the first embodiment. It is a point that has been.

  Again, one sustain period is divided into four periods indicated by T21 to T24, and each period will be described in detail.

(Period T21)
At time t21, the switching element Q61 of the power recovery unit 61 is turned on. Then, current starts to flow from the ground potential to the sustain electrodes SU1 to SUn through the switching element Q61, the diode D61, and the inductor L61, and the voltage of the sustain electrodes SU1 to SUn starts to rise. After 1/2 of the resonance period of inductor L61 and interelectrode capacitance Cp, the voltage of sustain electrodes SU1 to SUn rises to almost voltage V63, and the current flowing through inductor L61 becomes “0”.

  In the present embodiment, the resonance period between the inductor L61 and the interelectrode capacitance Cp is set to a time longer than twice the discharge delay time. However, unlike Embodiment 1, the voltage V63 is set lower than the discharge start voltage. Therefore, even a discharge cell that has caused an address discharge does not reach the discharge start voltage and does not generate a sustain discharge.

(Period T22)
At time t22 after the current flowing through the inductor L61 becomes “0”, the switching element Q63 of the sustain side clamp unit 63 is turned on. Then, the voltage of sustain electrodes SU1 to SUn is clamped at voltage V63. Further, the switching element Q53 of the scanning side clamp unit 53 is turned off and the switching element Q54 is turned on. Then, the voltages of scan electrodes SC1 to SCn are clamped to voltage (−V53).

  When sustain electrodes SU1 to SUn are clamped to voltage V63 and scan electrodes SC1 to SCn are clamped to voltage (−V53), the voltage difference applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is It becomes a voltage (V53 + V63). In the discharge cell in which the address discharge has occurred, after the voltage difference between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn exceeds the discharge start voltage, a sustain discharge occurs after a time longer than the discharge delay time elapses. .

  After the sustain discharge converges, switching elements Q61 and Q63 of sustain pulse generating unit 60 on the sustain side are turned off.

(Period T23)
At time t23, the switching element Q62 of the power recovery unit 61 is turned on. Then, current starts to flow from the sustain electrodes SU1 to SUn to the ground potential through the inductor L61, the diode D62, and the switching element Q62, and the voltage of the sustain electrodes SU1 to SUn starts to decrease. Then, after 1/2 of the resonance period between the inductor L61 and the interelectrode capacitance Cp, the voltage of the sustain electrodes SU1 to SUn drops to almost the voltage (−V63), and the current flowing through the inductor L61 becomes “0”.

  As described above, the resonance period between the inductor L61 and the interelectrode capacitance Cp is set to a time longer than twice the discharge delay time, but the voltage V63 is set lower than the discharge start voltage. Therefore, even a discharge cell that has caused an address discharge does not reach the discharge start voltage and does not generate a sustain discharge.

(Period T24)
At time t24 after the current flowing through the inductor L61 becomes “0”, the switching element Q64 of the sustain side clamp portion 63 is turned on. Then, sustain electrodes SU1 to SUn are clamped to voltage (−V63). Further, the switching element Q54 of the scanning side clamp unit 53 is turned off and the switching element Q53 is turned on. Then, the voltages of scan electrodes SC1 to SCn are clamped at voltage V53.

  When sustain electrodes SU1 to SUn are clamped to voltage (−V63) and scan electrodes SC1 to SCn are clamped to voltage V53, the voltage difference applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is The voltage is (−V53−V63). In the discharge cell in which the address discharge has occurred, after the voltage difference between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn exceeds the discharge start voltage, a sustain discharge occurs after a time longer than the discharge delay time elapses. .

  After the sustain discharge converges, switching elements Q62 and Q64 of sustain pulse generating unit 60 on the sustain side are turned off.

  By repeating the operations in the above-described periods T21 to T24, sustain pulse generating units 50 and 60 in the present embodiment apply the necessary number of sustain pulses to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.

  The voltage values in the second embodiment are, for example, voltage V63 = 120 (V), voltage V64 = −120 (V), voltage V53 = 60 (V), and voltage V54 = −60 (V). The resonance period between the inductor L61 and the interelectrode capacitance Cp is 1600 nsec, the lengths of the periods T21 and T23 are 800 nsec, and the lengths of the periods T21 and T23 are 1700 nsec.

  In the present embodiment, scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn are described as being clamped simultaneously in period T22 and period T24. However, they do not necessarily have to be the same, and the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn may be clamped before the sustain pulse is generated in the period T22 and the period T24.

  In the second embodiment, as described in the period T21 to the period T24, the resonance period of the inductor L61 and the interelectrode capacitance Cp is set to a time longer than twice the discharge delay time. However, since the sustain-side sustain pulse amplitude is set low, a sustain discharge occurs after the current flowing through the power recovery inductor L61 becomes “0”. Therefore, also in the second embodiment, a sustain discharge occurs after ringing having a high frequency component starts to attenuate. Therefore, the timing at which ringing occurs and the timing at which sustain discharge occurs deviate and unnecessary radiation is suppressed.

  It should be noted that the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the optimal values according to the panel characteristics, the plasma display device specifications, and the like.

  INDUSTRIAL APPLICABILITY The present invention can generate a stable sustain discharge in a panel and suppress unwanted radiation, and is useful as a panel driving method and a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 22 Data electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 41, 57 Reference potential setting part 44 Write pulse generator 50, 60 Sustain pulse generator 53 Scan side clamp 55, 56 Lamp voltage generator 59 Scan pulse generator 61 Power recovery unit 63 Sustain side clamp 65 Voltage application unit Cp Interelectrode capacitance L61 Inductor

Claims (4)

In a plasma display panel having a plurality of discharge cells each having a scan electrode and a sustain electrode, a scan-side sustain pulse having a first voltage and a second voltage is applied to the scan electrode, and a third voltage and a second voltage are applied to the sustain electrode. A plasma display panel driving method for generating a sustain discharge in the discharge cell by applying a sustain side sustain pulse having four voltages,
A power recovery unit configured to resonate an interelectrode capacitance between the scan electrode and the sustain electrode and an inductor to cause the sustain side sustain pulse to rise or fall; and a voltage of the sustain side sustain pulse to the third voltage Alternatively, a scan electrode having a sustain electrode drive circuit having a sustain side clamp unit that clamps to the fourth voltage, and a scan side clamp unit that clamps the voltage of the scan side sustain pulse to the first voltage or the second voltage. Drive circuit,
Using the power recovery unit, the sustain side sustain pulse rises or falls,
The voltage of the sustain electrode is clamped to the third voltage or the fourth voltage using the sustain-side clamp unit after a time ½ of the resonance period of the interelectrode capacitance and the inductor has elapsed,
A plasma display panel that generates the sustain discharge by clamping the scan electrode voltage to the second voltage or the first voltage using the scan-side clamp unit simultaneously with or after the sustain electrode voltage clamp. Driving method. 2. The method of driving a plasma display panel according to claim 1, wherein the inductance of the inductor is set so that a resonance period between the interelectrode capacitance and the inductor is shorter than twice a discharge delay time of the sustain discharge. A plasma display panel having a plurality of discharge cells each having a scan electrode and a sustain electrode; a scan electrode driving circuit for applying a scan-side sustain pulse having a first voltage and a second voltage to the scan electrode; and the sustain electrode A plasma display device having a sustain electrode driving circuit for applying a sustain side sustain pulse having a third voltage and a fourth voltage,
The sustain electrode driving circuit includes a power recovery unit configured to resonate an interelectrode capacitance between the scan electrode and the sustain electrode, and an inductor, so that the sustain side sustain pulse rises or falls, and the sustain side sustain pulse A sustain side clamping unit that clamps the voltage of the second voltage to the third voltage or the fourth voltage,
The scan electrode driving circuit includes a scan side clamp unit that clamps the voltage of the scan side sustain pulse to the first voltage or the second voltage,
The sustain side sustain pulse rises or falls using the power recovery unit, and the sustain side clamp unit is used after ½ time of the resonance period between the interelectrode capacitance and the inductor has elapsed. The sustain electrode voltage is clamped to the third voltage or the second voltage, and at the same time as or after the sustain electrode clamp, the scan side clamp unit is used to set the scan electrode voltage to the second voltage or the second voltage. A plasma display apparatus that generates a sustain discharge by clamping to a first voltage. The plasma display apparatus according to claim 3, wherein the inductance of the inductor is set so that a resonance period between the interelectrode capacitance and the inductor is shorter than twice a discharge delay time of the sustain discharge.

Images