JP2011248597A - Tester simulation apparatus, tester simulation program, and tester simulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a total time to be required for logic verification and test debugging.SOLUTION: A tester simulation device 1 for virtually simulating a test in a DUT by a tester includes: a virtual device 11 where the operation of the DUT is modeled on a simulator; a virtual tester 12 for applying an input pattern of a verification scenario to perform the logic verification of the virtual device 11 to the virtual device 11, inputting a response pattern to be outputted from the virtual device 11, comparing the pattern with an expectation value pattern, and determining the quality; and a test pattern generation part 14 for acquiring the input pattern and the expectation value pattern from the virtual tester 12, and generating the acquired input pattern and the expectation value pattern as a test pattern to actually test the DUT when the input pattern and the response pattern are the normal ones.

Description

  The present invention relates to a tester simulation apparatus, a tester simulation program, and a tester simulation method for virtually simulating a test of a device under test.

  A semiconductor test apparatus (tester) is used to determine pass / fail of a device under test (DUT). In order to perform a DUT test, a test program that runs on a tester and a test pattern for determining whether or not the DUT is good are verified by simulation. A technique for performing this kind of simulation is disclosed in Patent Document 1, for example.

  FIG. 3 shows an example of a conventional tester simulation apparatus. In FIG. 3, the tester simulation apparatus 100 is schematically configured to include a logic simulator 101, a storage device 102, a debugger 103, and a waveform display device 104. The logic simulator 101 is software that performs simulation, and includes a virtual tester 111, a virtual device 112, and a test circuit model 113.

  The virtual tester 111 and the virtual device 112 are virtual models of actual testers and DUTs, respectively. The test circuit model 113 defines the connection relationship between the virtual tester 111 and the virtual device 112, and sets the pin connection relationship and the delay amount between the actual DUT and the tester.

  The storage device 102 includes a test program storage unit 121 and a test pattern storage unit 122. The test program storage unit 121 stores a test program, and the test pattern storage unit 122 stores a test pattern. The debugger 103 is software that verifies a test program that runs on the virtual tester 111. The waveform display device 104 is connected to the output side of the virtual tester 111 and displays a waveform of an input pattern applied from the virtual tester 111 to the virtual device 112.

  The logic simulator 101 is mainly used for performing test debugging (test program and test pattern debugging). Therefore, first, the virtual tester 111 reads the test program from the test program storage unit 121 and executes the control contents of the test program.

  Execution of the test pattern is started based on the control contents of the test program. In order to execute the test pattern, the virtual tester 111 reads the test pattern from the test pattern storage unit 122. In the test pattern, an input pattern to be applied to the virtual tester 111 and an expected value pattern are set.

  The virtual tester 111 applies the read input pattern to the virtual device 112. The virtual device 112 operates based on the input pattern and outputs a response pattern, and this response pattern is input to the virtual tester 111. The virtual tester 111 compares the response pattern with the expected value pattern, and performs pass / fail determination (pass-fail determination).

  The debugger 103 verifies the control contents of the test program of the virtual tester 111. As a result of the verification, if there is a defect in the control content of the test program, the content of the test program stored in the test program storage unit 121 is corrected. The test program is debugged by the above verification and correction.

  In addition to test program debugging, test patterns are also debugged. The virtual tester 111 performs the above-described determination. If there is no problem in the test pattern, the expected value pattern matches the response pattern, and all the determination results are paths. In other words, if the determination result includes a failure, the test pattern is defective. Thereby, the defect of the test pattern is verified.

  The input pattern applied from the virtual tester 111 is displayed on the waveform display device 104, and if the displayed waveform is an unintended waveform, this also verifies the problem of the test pattern.

  If there is a defect in the test pattern, the test pattern in the test pattern storage unit 122 is corrected. Then, verification and correction are performed until the test pattern is normal (for example, correction is performed until all determination results are passed). As described above, test debugging (test program and test pattern debugging) is performed, and a test program and a test pattern that can be used for the actual test are generated.

JP 2003-240824 A

  By performing test debugging using a tester simulation device, it is possible to generate a normal test program and a test pattern free from defects that can be used in actual tests. However, this test debug is based on the premise that the logic verification has been completed and the virtual device 112 is accurate.

  The virtual device 112 is DUT design information, and there may be an error in the design information. The actual DUT is manufactured based on the design information. Therefore, if there is an error in the design information, the manufactured DUT is a defective product. Therefore, the virtual device 112 is verified in advance before performing test debugging. This is logic verification. When a failure is detected by logic verification, the design information is corrected until the failure is eliminated, and the correct virtual device 112 is set.

  Therefore, the logic verification and the test debugging are performed in different phases, and the test debugging phase is performed after the logic verification phase is completed. Accordingly, a predetermined time is required for each phase. In recent years, DUTs tend to be highly functional and complicated, and the amount of information to be processed is large, so that much time is required for logic verification and test debugging. Therefore, the total time until the logic verification and the next test debug are completed is very long.

  Therefore, an object of the present invention is to shorten the total time required for logic verification and test debugging.

  In order to solve the above problems, a first tester simulation apparatus of the present invention is a tester simulation apparatus that virtually simulates a test of a device under test by a tester, and the operation of the device under test is modeled on a simulator. The virtual device and the verification scenario input pattern for logical verification of this virtual device are applied to the virtual device, the response pattern output from this virtual device is input, and compared with the expected value pattern. The virtual tester that performs the determination, the input pattern and the expected value pattern are acquired from the virtual tester, and when the input pattern and the response pattern are normal, the acquired input pattern and expected value pattern are received from the target tester. As a test pattern for actual testing of test devices A test pattern generator for forming, characterized by comprising a.

  According to this tester simulation apparatus, when the result of logic verification is normal, the input pattern and expected value pattern of the verification scenario are generated as test patterns. As a result, the generated input pattern is not required to be corrected, and a test debug is performed. As a result, the test pattern can be debugged simultaneously with the logic verification, and the total time can be reduced.

  A second tester simulation apparatus according to the present invention is a first tester simulation apparatus based on setting data in which control contents executed by the virtual tester are set in parallel with the logic verification and the generation of the test pattern. And a test program generator for generating a normal test program.

  According to this tester simulation apparatus, a test program is debugged in parallel with test pattern debugging and logic verification. As a result, logic verification and test debugging can all be performed in parallel, and the total time can be further reduced.

  A third tester simulation apparatus of the present invention is the first or second tester simulation apparatus, provided between the virtual device and the virtual tester, and a test circuit model that defines a connection relationship between the two, The input pattern and the response pattern include a bypass path for bypassing the test circuit model.

  According to this tester simulation apparatus, a test circuit model and a bypass path for bypassing are provided. Thereby, it is not necessary to generate a test pattern such as a high-speed interface, and it is possible to cope with logic verification of a device that does not pass through a test circuit model.

  A fourth tester simulation program according to the present invention is a tester simulation program for virtually simulating a test of a device under test by a tester, and a virtual device means that models the operation of the device under test on a simulator. Then, an input pattern of a verification scenario for performing logical verification of the virtual device means is applied to the virtual device means, and a response pattern output from the virtual device means is input and compared with an expected value pattern to determine pass / fail. The virtual tester means to perform, the input pattern and the expected value pattern are acquired from the virtual tester means, and when the input pattern and the response pattern are normal, the acquired input pattern and expected value pattern are To perform device testing Test pattern generating means for generating a test pattern, characterized in that to function as a.

  A fifth tester simulation program according to the present invention is a fourth tester simulation program, and sets the control contents to be executed by the virtual tester means in parallel with the logic verification and the generation of the test pattern. It is made to function as a test program generation means for generating a test program based on the set data.

  A sixth tester simulation method of the present invention is a tester simulation method for virtually simulating a test of a device under test by a tester, and a verification scenario for inputting the operation of the device under test into a virtual device modeled The input pattern and the response pattern output from the virtual device are logically verified. When the normal input pattern and the normal response pattern are obtained by the logical verification, the normal input pattern and the expected value pattern are tested. It is characterized by generating as a pattern.

  A seventh tester simulation method according to the present invention is a sixth tester simulation method, wherein the control contents of a virtual tester that models the operation of the tester in parallel with the generation of the normal input pattern and the logic verification. A test program to be executed by the virtual tester is generated based on the set setting data.

  According to the present invention, when the logic verification is normal, the input pattern and the expected value pattern of the verification scenario are generated as test patterns, so that the test pattern can be debugged simultaneously with the logic verification. Therefore, the total time required for logic verification and test pattern debugging can be shortened. In addition, the time required for logic verification and test debugging can be further shortened by debugging the test program in parallel with this.

It is a functional block diagram which shows schematic structure of a tester simulation apparatus. It is a hardware block diagram for performing each function of FIG. It is a block diagram for demonstrating the conventional tester simulation apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. A tester simulation apparatus 1 shown in FIG. 1 mainly includes a logic simulator 2, a storage device 3, and a waveform display device 4.

  The logic simulator 2 is used to virtually simulate an actual test environment of a device under test (DUT), and is software that runs on a computer. The logic simulator 2 includes a virtual device 11, a virtual tester 12, a test circuit model 13, a test pattern generation unit 14, a test program generation unit 15, a debug tool 16, and a conversion output unit 17.

  The virtual device 11 is a virtual model of the DUT on the simulator, and serves as DUT design information. The actually manufactured DUT has a circuit configuration based on the design information. Therefore, the virtual device 11 performs the same operation as the DUT. The virtual tester 12 is a model of a tester for performing a DUT test on a simulator. The virtual tester 12 includes a pattern input unit 21, a pattern comparison unit 22, an expected value output unit 23, and a virtual tester control unit 24, and is set to perform the same operation as the actual tester.

  The pattern input unit 21 applies an input signal to the virtual device 11. A plurality of continuous input signals are applied to the virtual device 11 as an input pattern. The virtual device 11 performs an internal operation by applying an input signal and outputs a response signal. The response signal also has a plurality of continuous response patterns, and the response pattern is input from the virtual device 11 to the virtual tester 12.

  The pattern comparison unit 22 inputs a response pattern from the virtual device 11 and inputs an expected value pattern from the expected value output unit 23. The expected value pattern output by the expected value output unit 23 is a pattern serving as a reference for comparing response patterns. The pattern comparison unit 22 compares the response pattern with the expected value pattern and performs pass / fail determination (pass / fail determination). The virtual tester control unit 24 controls the entire operation of the virtual tester 12 and performs an operation based on the control contents of the test program.

  The test circuit model 13 is data defining the connection relationship and the delay amount between the virtual tester 12 and the virtual device 11. The actual tester and DUT are provided with a plurality of pins, and the pins are connected to each other. The test circuit model 13 defines the connection relationship and the delay amount of each pin at this time.

  The test pattern generation unit 14 generates a test pattern used for the actual test. The virtual tester 12 applies an input pattern to the virtual device 11, and at the same time acquires an input pattern applied by the test pattern generation unit 14. The test pattern generation unit 14 also acquires an expected value pattern output to the pattern comparison unit 22.

  The test pattern generation unit 14 generates and holds the acquired input pattern and expected value pattern as a temporary test pattern. Then, only when the input pattern applied from the virtual tester 12 and the response pattern input to the virtual tester 12 are all normal, the temporarily generated test pattern is generated as a formal test pattern. On the other hand, when any one or both of the input pattern and the response pattern has a problem, the test pattern temporarily generated is discarded.

  The test program generation unit 15 generates a test program that controls the tester. The test program is a program in which the control content of the virtual tester 12 is set, and operates on the tester in the actual test. The test program generation unit 15 generates a test program that reads setting data (to be described later) and executes the control contents. The generated test program is read by the virtual tester 12 and the control content is executed.

  The debug tool 16 verifies the test program. The test program is generated based on the setting data, and when the content of the setting data has an error, a problem occurs in the test program. This failure is verified by the debug tool 16. The test program generated by the test program generation unit 15 is provisional, and is generated as a formal test program only when it is normal as a result of verification by the debug tool 16.

  The conversion output unit 17 is connected to the test pattern generation unit 14 and the test program generation unit 15 and acquires a test pattern and a test program. The test pattern and the test program acquired by the conversion output unit 17 are normal without defects and can be used for actual tests. The conversion output unit 17 stores the test pattern and the test program in the storage device 3.

  The logic simulator 2 is set in a dedicated language such as HDL (Hardware Description Language), and test patterns and test programs that operate in the logic simulator 2 are also in HDL format. On the other hand, the language of the test program used for the actual tester may be different from that of HDL. In this case, the language is converted into the language of the test program and the test pattern. Also, the data format, the command format, etc. may be converted.

  A test circuit model 13 is interposed between the virtual tester 12 and the virtual device 11, and bypass paths BP1 and BP2 are provided so as to bypass the test circuit model 13. The bypass path BP1 is a path for directly applying the input pattern to the virtual device 11, and BP2 is a path for directly inputting the response pattern to the virtual tester 12.

  Next, the storage device 3 will be described. The storage device 3 is a hard disk or the like that can store various data. The storage device 3 includes a verification scenario storage unit 31, a test program storage unit 32, a test pattern storage unit 33, and a setting data storage unit 34.

  The verification scenario storage unit 31 stores a verification scenario. The verification scenario is data for performing logical verification, and has an input pattern and an expected value pattern applied to the virtual device 11. For this reason, the input pattern of the verification scenario is a pattern for logic verification. The input pattern that the pattern input unit 21 applies to the virtual device 11 is the input pattern of this verification scenario.

  The test program storage unit 32 stores the test program output from the conversion output unit 17, and the test pattern storage unit 33 stores the test pattern. The setting data storage unit 34 stores data for setting the control contents of the test program as setting data. The setting data here includes four data: test circuit setting data, timing setting data, terminal level setting data, and pattern list data.

  The test circuit setting data is data related to the connection between the virtual device 11 and the virtual tester 12, that is, data for setting the test circuit model 13. The timing setting data defines the timing of various signals such as a rate signal that defines the operation cycle of the tester, a strobe signal that defines the determination timing, and a timing edge signal that defines the timing of waveform edge change.

  The terminal level setting data sets a threshold value indicating whether the response signal is at a high level or a low level. The response signal output from the virtual device 11 is a voltage, and the terminal level setting data sets a threshold value for identifying whether the voltage is at a high level or a low level. The pattern list data is information on the list name of each test pattern when there are a plurality of test patterns.

  Basically, a test program can be generated by using the above four data as setting data. However, if there is necessary data other than these, the data may be set as setting data and used for generating a test program.

  The waveform display device 4 is a display device for displaying a waveform, and is connected to the logic simulator 2. The waveform display device 4 is provided to display the waveform of the input signal applied from the pattern input unit 21 and the response signal output from the virtual device 11. A path between the virtual device 11 and the virtual tester 12 is branched, and an input signal and a response signal are input to the waveform display device 4 from the branch point. Moreover, the waveform display of the input signal and the response signal inside the virtual device 11 is also possible, and the waveform display device 4 is connected to the inside of the virtual device 11.

  FIG. 2 shows a hardware configuration of each block of FIG. 1, and a CPU 41, a memory 42, a storage device 3, and a waveform display device 4 are connected via a bus 43. The CPU 41 is a means for executing various software including the logic simulator 2, and the memory 42 is a storage means for executing the software. The storage device 3 is the same as that shown in FIG. 1 and stores the above-described software. The waveform display device 4 is the same as that shown in FIG. 1, and each device is connected by a bus 43.

  The above is the schematic configuration. Next, the operation will be described. In the present invention, the test pattern is debugged simultaneously with the logic verification, and the test program is debugged in parallel with the logic verification and the test pattern debugging.

  Here, the logic verification will be described. Logical verification refers to verifying whether or not the virtual device 11 is normal, correcting the virtual device 11 as necessary, and setting the normal virtual device 11. The virtual device 11 is DUT design information, and there may be an error in the design information. In this case, the error is corrected and a setting is made so that the normal virtual device 11 operates normally.

  An input pattern of a verification scenario is used for logical verification. It is verified whether or not the virtual device 11 operates normally using this input pattern. However, this input pattern itself may have an error. For this reason, the logical verification normally generates both the input pattern of the verification scenario and the virtual device 11. Accordingly, if there is no defect from the beginning in both the input pattern of the verification scenario and the virtual device 11, the logic verification is performed without requiring correction.

  Describe test debugging. Test debugging includes test program debugging and test pattern debugging. Debugging a test program is to generate a normal test program that does not cause a defect, and debugging a test pattern is to generate a normal test pattern that does not cause a defect. Therefore, if a defect has occurred, correction is performed, and if no defect has occurred, correction is not performed.

  The logic simulator 2 shown in FIG. 1 is configured to perform both logic verification and test debugging, that is, a simulation in which both environments are integrated. When the simulation is started using the logic simulator 2, the test program generation unit 15 first starts a test program generation operation. The test program is a program in which the control content of the virtual tester 12 is set, and the control content is executed by operating in the virtual tester control unit 24.

  The test program generation unit 15 reads the setting data from the setting data storage unit 34 and generates a test program. The setting data includes test circuit setting data, terminal level setting data, timing setting data, and pattern list data, and a test program is generated by converting each data into an executable instruction (code). The generated test program is output to the virtual tester control unit 24, and the virtual tester control unit 24 executes the input test program.

  The test program includes an instruction for applying a test pattern, and when the instruction is executed, application of the test pattern is started. Thereby, the virtual tester control unit 24 starts application of the input pattern from the pattern input unit 21. Based on this control, the pattern input unit 21 reads the verification scenario from the verification scenario storage unit 31.

  An expected value pattern is set in the verification scenario, and this expected value pattern is set in the expected value output unit 23. Then, the pattern input unit 21 applies the verification scenario input pattern to the virtual device 11.

  An input pattern from the virtual tester 12 is applied to the virtual device 11 via the test circuit model 13. The virtual device 11 operates based on the input pattern and outputs a response pattern toward the virtual tester 12. The response pattern is input to the pattern comparison unit 22 via the test circuit model 13. The pattern comparison unit 22 compares the expected value pattern output from the expected value output unit 23 with the response pattern, and performs a pass / fail determination.

  At this time, if any one or both of the input pattern of the verification scenario and the setting of the virtual device 11 are defective, the determination result of the pattern comparison unit 22 includes a failure. As a result, it is recognized that there is a problem in either or both of the former and the latter. At this time, if there is a defect in the input pattern of the verification scenario, the correction is performed until the input pattern is normal. Thereby, a normal input pattern is obtained.

  If there is an error in the setting of the virtual device 11, that is, in the design information of the DUT, the design information is corrected. Thereby, a normal virtual device 11 is obtained. When both the input pattern of the verification scenario and the setting of the virtual device 11 become normal, the determination results of the pattern comparison unit 22 are all paths. That is, the above correction is performed until all the determination results of the pattern comparison unit 22 are paths. However, if everything is a path from the beginning, no modification is required.

  As described above, a normal verification scenario input pattern and a normal virtual device 11 are obtained. This is logic verification. The logic verification may be performed using the waveform display device 4. The waveform display device 4 displays the input pattern applied from the pattern input unit 21 on the screen as a waveform, and can confirm whether or not the displayed waveform is the intended waveform. If the waveform is not intended (a waveform different from the original input pattern), the input pattern of the verification scenario is corrected because the input pattern has a defect. Thereby, a normal input pattern is obtained.

  The waveform display device 4 also displays the screen of the response pattern waveform. For this reason, if the displayed waveform is an unintended waveform (a waveform different from the original response pattern), the response pattern is defective. That is, it is recognized that the operation of the virtual device 11 is defective when the waveform of the response pattern is an unintended waveform even though the input pattern is normal.

  For this reason, the setting of the virtual device 11, that is, the design information of the DUT is corrected. Thereby, a normal virtual device 11 is obtained. As described above, the input pattern of the verification scenario and the virtual device 11 can be generated as normal, thereby performing logical verification.

  When the pattern input unit 21 applies an input pattern, the test pattern generation unit 14 acquires an input pattern to be applied simultaneously. That is, the input pattern is acquired regardless of whether or not a defect has occurred, and the expected value pattern is acquired from the pattern comparison unit 22. Then, the input pattern and the expected value pattern are generated as a temporary test pattern.

  Then, when the logic verification is completed, that is, when a normal input pattern and a normal virtual device 11 are obtained, the provisionally generated test pattern is generated as a formal test pattern. On the other hand, if any one or both of the input pattern and the virtual device 11 are defective, the test pattern temporarily generated is discarded.

  The test pattern formally generated by the test pattern generation unit 14 is a normal test pattern with no defects. Therefore, this test pattern can be used as an input pattern to be applied during the actual test. That is, by generating an input pattern of a normal verification scenario used for logic verification as a test pattern, the test pattern is substantially debugged.

  As a result, the test pattern is debugged simultaneously with the logic verification. Conventionally, after performing logic verification to generate a normal virtual device 11, debugging is performed using a separate test pattern. However, both logic verification and test pattern debugging can be performed substantially simultaneously. Can be performed in the same phase. Thereby, the total time can be shortened.

  The virtual tester control unit 24 performs the above series of operations. Then, the debug tool 16 verifies whether or not there is a defect in the control content of the virtual tester control unit 24, that is, the control content of the test program. If there is a defect in the control contents of the test program as a result of verification by the debug tool 16, for example, if there is an error in the order or operation of the control contents, or if there is an error in the instruction format, etc. Program corrections are made.

  The test program is corrected by correcting the contents of various setting data stored in the setting data storage unit 34. The test program generation unit 15 temporarily holds the generated test program, and discards the test program when it is recognized that a failure has occurred. Then, a new test program is generated using the corrected setting data, and the virtual tester control unit 24 starts executing the new test program from the beginning. The debug tool 16 verifies the control contents of the test program again.

  When the debugging tool 16 recognizes that the test program is still defective, the setting data is corrected again, and the test program is corrected until a normal test program without a defect is generated. Then, verification and correction are performed until a correct test program is finally generated. As a result, the test program is debugged.

  The debugging of the above test program is performed in parallel with the logic verification and the debugging of the test pattern. Each unit that debugs a test program is different from each unit that debugs logic verification and test patterns, and each unit can operate independently. For this reason, debugging of a test program, logic verification, and debugging of a test pattern are performed in parallel.

  As described above, debugging of the test pattern and logic verification can be performed at the same time, and the test program can be debugged in parallel with these. The generated test pattern and test program are output to the conversion output unit 17. The conversion output unit 17 converts the test pattern and the test pattern into languages and formats as necessary, stores the test program in the test program storage unit 32, and stores the test pattern in the test pattern storage unit 33. The test patterns and test programs stored in the respective storage units are normal with no defects, and can be used as they are for actual tests.

  Therefore, by performing test pattern debugging at the same time as logic verification and debugging a test program in parallel with these, it becomes possible to perform both logic verification and test debugging in parallel. As a result, since the test pattern is debugged after the logic verification is completed and then the test debugging is performed all in parallel, the time can be greatly reduced. Further, by using the verification scenario for logic verification as it is as a test pattern, it is not necessary to generate a separate test pattern for test debugging.

  Further, when a SerDes (Serializer / Deserializer) high-speed interface or the like is applied as the virtual device 11, the function is not subject to testing, so it is not necessary to generate a test pattern, but it is necessary to perform logic verification. There is a case. In this case, since the virtual tester 12 and the virtual device 11 are directly connected, the test circuit model 13 becomes unnecessary. For this purpose, bypass paths BP1 and BP2 are provided.

  In this case, the bypass paths BP1 and BP2 are enabled, the input pattern is directly applied to the virtual device 11 from the virtual tester 12, and the response pattern from the virtual device 11 is directly input to the virtual tester 12. . As a result, logic verification can be performed. Thus, the logic simulator 2 can be used for logic verification that does not require the generation of a test pattern and does not pass through the test circuit model 13.

DESCRIPTION OF SYMBOLS 1 Tester simulation apparatus 2 Logic simulator 3 Memory | storage device 4 Waveform display apparatus 11 Virtual device 12 Virtual tester 13 Test circuit model 14 Test pattern generation part 15 Test program generation part 16 Debug tool 17 Conversion output part 21 Pattern input part 22 Pattern comparison part 23 Expected value output unit 24 Virtual tester control unit 31 Verification scenario storage unit 32 Test program storage unit 33 Test pattern storage unit 34 Setting data storage unit

Claims (7)

A tester simulation apparatus for virtually simulating a test of a device under test by a tester,
A virtual device that models the operation of the device under test on a simulator;
A virtual tester that applies a verification scenario input pattern for performing logical verification of the virtual device to the virtual device, inputs a response pattern output from the virtual device, and compares the expected pattern with the expected value pattern; ,
The input pattern and the expected value pattern are acquired from the virtual tester, and when the input pattern and the response pattern are normal, the device under test is actually tested with the acquired input pattern and the expected value pattern. A test pattern generation unit for generating a test pattern for
A tester simulation apparatus comprising: In parallel with the logic verification and the generation of the test pattern, it further comprises a test program generation unit that generates a normal test program based on setting data in which the control content executed by the virtual tester is set. The tester simulation apparatus according to claim 1. A test circuit model provided between the virtual device and the virtual tester, which defines a connection relationship between the two,
A bypass path for the input pattern and the response pattern to bypass the test circuit model;
The tester simulation apparatus according to claim 1, further comprising: A tester simulation program for virtually simulating a test of a device under test by a tester,
Computer
Virtual device means for modeling the operation of the device under test on a simulator;
An input pattern of a verification scenario for performing logic verification of the virtual device means is applied to the virtual device means, and a response pattern output from the virtual device means is input and compared with an expected value pattern to determine pass / fail. Virtual tester means,
The input pattern and the expected value pattern are acquired from the virtual tester means, and when the input pattern and the response pattern are normal, the acquired input pattern and the expected value pattern are subjected to an actual test of the device under test. Test pattern generation means for generating a test pattern for performing,
Tester simulation program characterized by functioning as The computer,
The function as a test program generation unit that generates a test program based on setting data in which control contents executed by the virtual tester unit are set in parallel with the generation of the logic verification and the test pattern. 4. The tester simulation program according to 4. A tester simulation method for virtually simulating a test of a device under test by a tester,
Perform logical verification of the input pattern of the verification scenario input to the virtual device that models the operation of the device under test and the response pattern output from the virtual device,
Generating a normal input pattern and an expected value pattern as a test pattern when a normal input pattern and a normal response pattern are obtained by this logic verification;
A tester simulation method characterized by In parallel with the normal input pattern generation and logic verification, a test program to be executed by the virtual tester is generated based on setting data in which the control content of the virtual tester that models the operation of the tester is set. The tester simulation method according to claim 6.

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