JP2011238745A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a threshold voltage of first and second MIS transistors to a desired threshold voltage, in a semiconductor device having the first and second MIS transistors with gate widths different from each other.SOLUTION: A semiconductor device has first and second MIS transistors. The first MIS transistor has a first gate insulating film 15A having a first high dielectric constant insulating film 15a, and a first gate electrode 20A. The second MIS transistor has a second gate insulating film 15B having a second high dielectric constant insulating film 15b, and a second gate electrode 20B. The first and second gate insulating films include an adjustment metal. A first gate width W1 of the first MIS transistor is smaller than a second gate width W2 of the second MIS transistor. An average adjustment metal concentration of the adjustment metal in the first gate insulating film is lower than that of the adjustment metal in the second gate insulating film.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having different gate widths and having a gate insulating film containing an adjustment metal, and a manufacturing method thereof. About.

  In order to miniaturize LSI, it is required to reduce the thickness of the gate insulating film. Therefore, in recent years, it has been studied to apply a high dielectric constant insulating film such as a hafnium (Hf) -based oxide film as the gate insulating film. Thereby, the electrical film thickness of the gate insulating film can be reduced while increasing the physical film thickness of the gate insulating film to suppress the leakage current.

  However, when a high dielectric constant insulating film is used as the gate insulating film and a conventional polysilicon film is used as the gate electrode, the threshold voltage of the MISFET (hereinafter referred to as MIS transistor) increases due to a phenomenon called Fermi level pinning. There are disadvantages. Further, in this case, due to a phenomenon called depletion of the gate electrode, the gate capacitance is reduced, a high electric field cannot be applied under the gate electrode, and the driving capability of the MIS transistor is reduced.

  Therefore, a technique has been proposed in which a metal film is used as the gate electrode instead of the conventional polysilicon film. When a high dielectric constant insulating film is used as the gate insulating film and a metal film is used as the gate electrode, it is necessary to control the threshold voltage of the n-type MIS transistor and the threshold voltage of the p-type MIS transistor independently of each other. is there.

  Therefore, in order to lower the threshold voltage of the n-type MOS transistor by shifting the effective work function of the n-type MOS (Metal Oxide Semiconductor) transistor to the band edge side, for example, lanthanum (La) is included as a gate insulating film. A technique using an Hf-based oxide film has been proposed (see, for example, Patent Document 1). The reason why the effective work function of the n-type MOS transistor can be shifted to the band edge side by using an Hf-based oxide film containing La as the gate insulating film is as follows. When La is included in the Hf-based oxide film, the flat band voltage shifts to the minus side, and therefore the effective work function of the n-type MOS transistor can be shifted to the band edge side.

  Hereinafter, the configuration of a conventional semiconductor device will be described with reference to FIG. FIG. 6 is a cross-sectional view in the gate length direction showing the configuration of a conventional semiconductor device.

  The conventional semiconductor device shown in FIG. 6 includes an n-type MOS transistor nTr1 and a p-type MOS transistor pTr.

  As shown in FIG. 6, an element isolation region 102 is formed on the silicon substrate 101. A P well diffusion layer 103 is formed in the first NMOS region of the silicon substrate 101. On the other hand, an N well diffusion layer 104 is formed in the PMOS region of the silicon substrate 101.

  On the first NMOS region of the silicon substrate 101, a gate insulating film 117a and a gate electrode 116a are sequentially formed. On the other hand, on the PMOS region in the silicon substrate 101, a gate insulating film 117b, a SiN film 109b, a La (O) film 111b, and a gate electrode 116b are sequentially formed.

  SiN films 118a and 118b and TEOS films 119a and 119b are sequentially formed on the side surfaces of the gate electrodes 116a and 116b. Source / drain diffusion layers 120a and 120b are formed below the sides of the gate electrodes 116a and 116b in the silicon substrate 101, respectively.

  The gate insulating film 117a includes a silicon oxide film 105a and a high dielectric constant gate insulating film (HfSiO film containing La) 106a. On the other hand, the gate insulating film 117b includes the silicon oxide film 105b and the HfSiON film 110b not including La.

  The gate electrode 116a includes a WSi film 114a, a barrier metal 113a, and a doped polycrystalline silicon film 115a. On the other hand, the gate electrode 116b includes a W film 112b, a barrier metal 113b, and a doped polycrystalline silicon film 115b.

JP 2009-194352 A

  However, when a conventional semiconductor device manufacturing method is used to manufacture a semiconductor device having an n-type MOS transistor and a p-type MOS transistor having different gate widths, there are the following problems. This problem will be described with reference to FIG. FIG. 7 is a cross-sectional view in the gate width direction showing the configuration of a conventional semiconductor device. In FIG. 7, the same components as those shown in FIG. 6 are denoted by the same reference numerals as those shown in FIG. Therefore, in the description of FIG. 7, the description similar to the description of FIG.

  The conventional semiconductor device shown in FIG. 7 includes n-type MOS transistors nTr2 and nTr1 and a p-type MOS transistor pTr. The gate width WTr2 of the n-type MOS transistor nTr2 is smaller than the gate width WTr1 of the n-type MOS transistor nTr1 (WTr2 <WTr1).

  The semiconductor device shown in FIG. 7 includes the following components in addition to the same components as the semiconductor device shown in FIG.

  On the second NMOS region in the silicon substrate 101, a gate insulating film 117c and a gate electrode 116c are sequentially formed. An SiN film 118c and a TEOS film 119c are sequentially formed on the side surface of the gate electrode 116c. The figure shown in FIG. 7 is a cross-sectional view in the gate width direction and not in the gate length direction. Therefore, although not shown in FIG. A drain diffusion layer is formed.

  The gate insulating film 117c includes a silicon oxide film 105c and a high dielectric constant gate insulating film (HfSiO film containing La) 106c. The gate electrode 116c includes a WSi film 114c, a barrier metal 113c, and a doped polycrystalline silicon film 115c.

  In FIG. 6, reference numerals are omitted, but active regions 101 c, 101 a, and 101 b surrounded by the element isolation region 102 are formed in the second and first NMOS and PMOS regions of the silicon substrate 101. .

  Although not shown in FIG. 6, in order to control the threshold voltages of the n-type MOS transistors nTr1 and nTr2, for example, boron (B) or the like is provided immediately below the gate electrodes 116c and 116a in the active regions 101c and 101a. P-type channel regions 121c and 121a containing p-type impurities are formed. On the other hand, in order to control the threshold voltage of the p-type MOS transistor pTr, an n-type channel region 121b containing an n-type impurity is formed immediately below the gate electrode 116b in the active region 101b.

  Since the channel region 121c and the channel region 121a are formed in the same process, the average impurity concentration X121c of the p-type impurity in the channel region 121c immediately after formation and the average of the p-type impurity in the channel region 121a immediately after formation. The impurity concentration X121a is the same (X121c = X121a).

  However, p-type impurities contained in the channel regions 121c and 121a are diffused into the element isolation region 102 by heat treatment performed after the formation of the channel regions 121c and 121a.

  As described above, since the channel region 121c and the channel region 121a are formed in the same process, the number and conditions of the heat treatment performed after the formation are the same between the channel region 121c and the channel region 121a. Therefore, the diffusion amount M121c of the p-type impurity diffusing from the channel region 121c into the element isolation region 102 is the same as the diffusion amount M121a of the p-type impurity diffusing from the channel region 121a into the element isolation region 102. Yes (M121c = M121a).

  Since the gate width WTr2 is smaller than the gate width WTr1 (WTr2 <WTr1), the channel width of the channel region 121c is smaller than the channel width of the channel region 121a. For this reason, the proportion of the diffusion amount M121c in the channel region 121c is relatively large, while the proportion of the diffusion amount M121a in the channel region 121a is relatively small.

  Since the proportion of the diffusion amount M121c in the channel region 121c is relatively large, the average impurity concentration Y121c of the p-type impurity in the channel region 121c after manufacture is the average impurity concentration of the p-type impurity in the channel region 121c immediately after formation. It is significantly lower than X121c (Y121c <X121c).

  On the other hand, since the proportion of the diffusion amount M121a in the channel region 121a is relatively small, the average impurity concentration Y121a of the p-type impurity in the channel region 121a after manufacture is the average of the p-type impurity in the channel region 121a immediately after formation. The impurity concentration is not significantly lower than the impurity concentration X121a, and the average impurity concentration Y121a is substantially the same as the average impurity concentration X121a (Y121a = X121a).

  Therefore, the average impurity concentration Y121c of the p-type impurity in the channel region 121c after manufacture is lower than the average impurity concentration Y121a of the p-type impurity in the channel region 121a after manufacture (Y121c <Y121a). Generally, as the average impurity concentration of p-type impurities in the channel region decreases, the threshold voltage of the n-type MOS transistor decreases. For this reason, the threshold voltage of the n-type MOS transistor nTr2 is lower than the threshold voltage of the n-type MOS transistor nTr1.

  Thus, conventionally, as the channel width becomes smaller, the average impurity concentration of the p-type impurity in the channel region after manufacture becomes lower than the average impurity concentration of the p-type impurity in the channel region immediately after formation. Therefore, the threshold voltage of the n-type MOS transistor is lowered. That is, the reverse narrow channel effect occurs in which the threshold voltage of the MOS transistor decreases as the gate width decreases.

  As described above, conventionally, the threshold voltage of the n-type MOS transistors nTr2 and nTr1 is lowered by using the HfSiO film containing La as the high dielectric constant gate insulating films 106c and 106a. On the other hand, the average impurity concentration of the p-type impurity in the channel region 121a having a large channel width is substantially the same as that immediately after formation after the manufacture, but the average impurity concentration of the p-type impurity in the channel region 121c having a small channel width. Therefore, the threshold voltage of the n-type MOS transistor nTr2 is lower than that immediately after formation, so that the threshold voltage of the n-type MOS transistor nTr1 becomes lower.

  Therefore, conventionally, although the threshold voltage of the n-type MOS transistor nTr1 having a large gate width WTr1 can be lowered to a desired threshold voltage, the threshold voltage of the n-type MOS transistor nTr2 having a small gate width WTr2 is There is a problem that the voltage becomes too low, becomes lower than the desired threshold voltage, and cannot be set to the desired threshold voltage.

  In view of the above, an object of the present invention is to control the threshold voltage of the first and second MIS transistors to a desired threshold voltage in a semiconductor device including first and second MIS transistors having different gate widths. That is.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device including a first MIS transistor and a second MIS transistor, and the first MIS transistor is a first active in a semiconductor substrate. A first gate insulating film formed on the region and having a first high dielectric constant insulating film; and a first gate electrode formed on the first gate insulating film; and the second MIS transistor includes: A second gate insulating film formed on the second active region of the semiconductor substrate and having a second high dielectric constant insulating film; and a second gate electrode formed on the second gate insulating film. The first gate insulating film and the second gate insulating film each include an adjustment metal, and the first gate width of the first MIS transistor is larger than the second gate width of the second MIS transistor. Small and second The average adjusting metal concentration of the adjusting metal in the gate insulating film is lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film. A first channel region including a first impurity formed immediately below the first gate electrode, and a second channel including a second impurity formed immediately below the second gate electrode in the second active region. The average impurity concentration of the first impurity in the first channel region is preferably lower than the average impurity concentration of the second impurity in the second channel region.

  According to the semiconductor device of the present invention, the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film is set to the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film. Lower than the metal concentration. As a result, the effective work function of the first MIS transistor is changed to an effective work function close to the midgap, while the effective work function of the second MIS transistor is changed to an effective work function close to the band edge. The threshold voltage of the transistor can be higher than the threshold voltage of the second MIS transistor.

  For this reason, the average impurity concentration of the first impurity (for example, p-type impurity) in the first channel region after manufacture is increased by the heat treatment performed after the formation of the first and second channel regions. The threshold voltage of the first MIS transistor becomes lower than the threshold voltage of the second MIS transistor by lowering the average impurity concentration of the second impurity (eg, p-type impurity) in the two channel regions. Even so, as described above, the threshold voltage of the first MIS transistor can be made higher than the threshold voltage of the second MIS transistor. Therefore, comprehensively, the threshold voltage of the first MIS transistor and the threshold voltage of the second MIS transistor can be made the same.

  In this way, by making the average adjustment metal concentration of the adjustment metal in the first gate insulating film lower than the average adjustment metal concentration of the adjustment metal in the second gate insulating film, It is possible to compensate for a difference in threshold voltage between the first and second MIS transistors caused by a difference in average impurity concentration between the first and second impurities in the second channel region. Therefore, the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.

  In the semiconductor device according to the present invention, the first gate width is preferably 100 nm or less, and the second gate width is preferably 200 nm or more.

  In the semiconductor device according to the present invention, it is preferable that the first MIS transistor and the second MIS transistor are n-type MIS transistors, and the adjustment metal is lanthanum.

  In the semiconductor device according to the present invention, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film is higher than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film. And low.

  In the semiconductor device according to the present invention, the first gate insulating film includes a first interface layer formed on the first active region and a first high dielectric constant insulating film formed on the first interface layer. And the second gate insulating film includes a second interface layer formed on the second active region and a second high dielectric constant insulating film formed on the second interface layer. It is preferable to become.

  In the semiconductor device according to the present invention, the first interface layer and the second interface layer are preferably made of a silicon oxide film.

  In the semiconductor device according to the present invention, the first high dielectric constant insulating film and the second high dielectric constant insulating film are preferably made of a metal oxide having a relative dielectric constant of 10 or more.

  In the semiconductor device according to the present invention, the first gate electrode includes a first metal film formed on the first gate insulating film and a first silicon film formed on the first metal film. Thus, the second gate electrode is preferably composed of a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a first MIS having a first gate insulating film and a first gate electrode formed on a first active region in a semiconductor substrate. A method for manufacturing a semiconductor device, comprising: a transistor; and a second MIS transistor having a second gate insulating film and a second gate electrode formed on a second active region in the semiconductor substrate. A step (a) of forming a gate insulating film forming film having a high dielectric constant insulating film on the active region and the second active region, and a first position located on the first active region in the gate insulating film forming film An adjustment metal is introduced into one region to form a first gate insulating film formation film, while an adjustment metal is introduced into a second region located on the second active region in the gate insulation film formation film. Second gate insulation A step (b) of forming a formation film, a step (c) of forming a gate electrode formation film on the first gate insulation film formation film and the second gate insulation film formation film, a gate electrode formation film, The first gate insulating film forming film and the second gate insulating film forming film are patterned to form a first gate insulating film and a gate electrode forming film made of the first gate insulating film forming film on the first active region. And forming a second gate insulating film formed of the second gate insulating film and a second gate electrode formed of the gate electrode forming film on the second active region. Step (d), wherein the first gate width of the first MIS transistor is smaller than the second gate width of the second MIS transistor. In step (b), the first gate insulating film formation film The average adjustment metal of the adjustment metal in The first gate insulating film forming film and the second gate insulating film forming film are formed in such a manner that the degree is lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film. It is characterized by that.

  According to the method for manufacturing a semiconductor device of the present invention, the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film formation film is set to the adjustment metal in the second gate insulation film formation film. Lower than the average metal concentration for adjustment. As a result, the effective work function of the first MIS transistor is changed to an effective work function close to the midgap, while the effective work function of the second MIS transistor is changed to an effective work function close to the band edge. The threshold voltage of the transistor can be higher than the threshold voltage of the second MIS transistor.

  For this reason, the average impurity concentration of the first impurity (for example, p-type impurity) in the first channel region after manufacture is increased by the heat treatment performed after the formation of the first and second channel regions. The threshold voltage of the first MIS transistor becomes lower than the threshold voltage of the second MIS transistor by lowering the average impurity concentration of the second impurity (eg, p-type impurity) in the two channel regions. Even so, as described above, the threshold voltage of the first MIS transistor can be made higher than the threshold voltage of the second MIS transistor. Therefore, comprehensively, the threshold voltage of the first MIS transistor and the threshold voltage of the second MIS transistor can be made the same.

  Thus, by making the average adjustment metal concentration of the adjustment metal in the first gate insulating film formation film lower than the average adjustment metal concentration of the adjustment metal in the second gate insulation film formation film. The difference between the threshold voltages of the first and second MIS transistors generated due to the difference in the average impurity concentration of the first and second impurities in the first and second channel regions can be compensated. Therefore, the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.

  In the method for manufacturing a semiconductor device according to the present invention, the step (b) includes a first adjustment metal having a first film thickness and including an adjustment metal on the first region in the gate insulating film formation film. A step (b1) of forming a film, and a step (b2) of forming a second adjustment metal film having the second film thickness and including the adjustment metal on the second region in the gate insulating film formation film And after the steps (b1) and (b2), the first gate insulating film is formed by introducing the adjusting metal in the first adjusting metal film into the first region of the gate insulating film forming film by heat treatment. A step (b3) of forming a formation film and introducing the adjustment metal in the second adjustment metal film into the second region of the gate insulation film formation film to form the second gate insulation film formation film; The first film thickness is preferably thinner than the second film thickness.

  In the method for manufacturing a semiconductor device according to the present invention, the step (b) includes a step (b1) of forming an adjustment metal film containing an adjustment metal on the gate insulating film formation film, and a step (b1). The adjusting metal in the adjusting metal film is introduced into the first region of the gate insulating film forming film by the first heat treatment to form the first gate insulating film forming film, and the adjusting metal film in the adjusting metal film is adjusted. A step (b2) of introducing a metal into the second region of the gate insulating film forming film, and a step of removing a portion of the adjustment metal film located on the first gate insulating film forming film after the step (b2). After step (b3) and step (b3), a second gate insulating film forming film is formed by additionally introducing the adjusting metal in the adjusting metal film into the second region of the gate insulating film forming film by a second heat treatment. A step (b4) of forming Masui.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the average adjustment metal concentration of the adjustment metal in the first gate insulating film is greater than the average adjustment metal concentration of the adjustment metal in the second gate insulating film. To compensate for the difference in the threshold voltage of the first and second MIS transistors caused by the difference in the average impurity concentration of the first and second impurities in the first and second channel regions. can do. Therefore, the threshold voltage of the first and second MIS transistors can be controlled to a desired threshold voltage.

(a)-(c) is a figure which shows the structure of the semiconductor device based on the 1st Embodiment of this invention, (a) is a top view, (b) is Ib-Ib shown to (a) (C) is a cross-sectional view taken along the line Ic-Ic shown in (a) (cross-sectional view in the gate length direction). (a)-(c) is sectional drawing of the gate width direction which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a)-(c) is sectional drawing of the gate width direction which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a)-(c) is sectional drawing of the gate width direction which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a)-(c) is sectional drawing of the gate width direction which shows the manufacturing method of the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention in order of a process. It is sectional drawing of the gate length direction which shows the structure of the conventional semiconductor device. It is sectional drawing of the gate width direction which shows the structure of the conventional semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (c). 1A to 1C are diagrams showing a configuration of a semiconductor device according to the first embodiment of the present invention, FIG. 1A is a plan view, and FIG. FIG. 1A is a cross-sectional view taken along the line Ib-Ib shown in FIG. 1A (a cross-sectional view in the gate width direction). FIG. 1C is a cross-sectional view taken along the line Ic-Ic shown in FIG. ). In FIG. 1A, for the sake of simplicity, only the first and second active regions and the first and second gate electrodes surrounded by the element isolation region 11 are illustrated. In FIGS. 1A to 1C and FIGS. 2A to 5C described later, the “first nMIS region” refers to a region where an n-type first MIS transistor is formed. Say. The “second nMIS region” refers to a region where an n-type second MIS transistor is formed. The first MIS transistor is a transistor used for, for example, an SRAM (Static Random Access Memory). The second MIS transistor is a transistor used in a logic circuit, for example.

  As shown in FIGS. 1A to 1C, the semiconductor device according to the present embodiment includes a first MIS transistor Tr1 and a second MIS transistor Tr2.

  As shown in FIG. 1A, a first active region 10a surrounded by the element isolation region 11 is formed in the first nMIS region in the semiconductor substrate. In the second nMIS region in the semiconductor substrate, a second active region 10b surrounded by the element isolation region 11 is formed. A first gate insulating film (see FIGS. 1B and 1C: 15A) and a first gate electrode 20A are sequentially formed on the first active region 10a. A second gate insulating film (see FIGS. 1B and 1C: 15B) and a second gate electrode 20B are sequentially formed on the second active region 10b.

  The first gate width W1 of the first MIS transistor Tr1 is smaller than the second gate width W2 of the second MIS transistor Tr2 (W1 <W2). The first gate width W1 is, for example, 100 nm or less. The second gate width W2 is, for example, 200 nm or more. Here, “first and second gate widths W1 and W2” refer to the widths of the first and second active regions 10a and 10b in the gate width direction.

  As shown in FIGS. 1B to 1C, a p-type well region 12 is formed in the semiconductor substrate 10.

  As shown in FIGS. 1B to 1C, the first MIS transistor Tr1 includes a first gate insulating film 15A formed on the first active region 10a and the first gate insulating film 15A. The first gate electrode 20A formed in the first active region 10a, the p-type first channel region 13a formed immediately below the first gate electrode 20A in the first active region 10a, and the side surface of the first gate electrode 20A The first offset spacer 21a formed above, and the first n-type extension region 22a formed below the side of the first gate electrode 20A in the first active region 10a (particularly, FIG. 1C) The first sidewall 23a formed on the side surface of the first gate electrode 20A via the first offset spacer 21a, and the outer side of the first sidewall 23a in the first active region 10a. The first n-type source drain region 24a (in particular, FIG. 1 (c) refer) formed and a.

  As shown in FIGS. 1B to 1C, the second MIS transistor Tr2 includes a second gate insulating film 15B formed on the second active region 10b and a second gate insulating film 15B. The second gate electrode 20B formed in the second active region 10b, the p-type second channel region 13b formed immediately below the second gate electrode 20B in the second active region 10b, and the side surface of the second gate electrode 20B The second offset spacer 21b formed above, and the second n-type extension region 22b formed below the side of the second gate electrode 20B in the second active region 10b (in particular, FIG. 1C) The second sidewall 23b formed on the side surface of the second gate electrode 20B via the second offset spacer 21b, and the outer side of the second sidewall 23b in the second active region 10b. The second n-type source drain region 24b (in particular, FIG. 1 (c) refer) formed and a.

  The first channel region 13a includes a first impurity (for example, a p-type impurity). The second channel region 13b includes a second impurity (for example, a p-type impurity). The average impurity concentration of the p-type impurity in the first channel region 13a is lower than the average impurity concentration of the p-type impurity in the second channel region 13b. As described in the second embodiment described later, the average impurity concentration of the p-type impurity in the first channel region (see FIG. 2 (a): 13A) immediately after the formation and the second impurity immediately after the formation. The average impurity concentration of the p-type impurity in the channel region (see FIG. 2A: 13B) is the same. However, by heat treatment (for example, heat treatment for activating n-type impurities contained in the first and second n-type source / drain implantation regions) performed after the formation of the first and second channel regions, The p-type impurity contained in the first and second channel regions diffuses into the element isolation region 11. For this reason, the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture is lower than the average impurity concentration of the p-type impurity in the second channel region 13b after manufacture.

  The first and second gate insulating films 15A and 15B each contain an adjustment metal (for example, La). The average adjusting metal concentration of the adjusting metal in the first gate insulating film 15A is lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film 15B.

  The first gate insulating film 15A includes a first interface layer 14a and a first high dielectric constant insulating film 15a containing an adjustment metal. The second gate insulating film 15B has a second interface layer 14b and a second high dielectric constant insulating film 15b containing an adjustment metal. The average adjusting metal concentration of the adjusting metal in the first high dielectric constant insulating film 15a is lower than the average adjusting metal concentration of the adjusting metal in the second high dielectric constant insulating film 15b. Specifically, the average La concentration of La in the first high dielectric constant insulating film 15a is, for example, 20% or less. The average La concentration of La in the second high dielectric constant insulating film 15b is, for example, 25%.

  The first and second high dielectric constant insulating films 15a and 15b are made of, for example, a metal oxide having a relative dielectric constant of 10 or more, specifically, for example, HfSiO containing La. The first and second interface layers 14a and 14b are made of, for example, a silicon oxide film.

  The first gate electrode 20A includes a first metal film 19a and a first silicon film 20a. The second gate electrode 20B has a second metal film 19b and a second silicon film 20b.

  According to this embodiment, the average adjustment metal concentration of the adjustment metal (for example, La) in the first gate insulating film 15A is set to the average adjustment metal concentration of the adjustment metal (for example, La) in the second gate insulating film 15B. Lower than metal concentration. As a result, the effective work function of the first MIS transistor Tr1 is set to an effective work function close to the midgap, while the effective work function of the second MIS transistor Tr2 is set to an effective work function close to the band edge. The threshold voltage of the second MIS transistor Tr1 can be made higher than the threshold voltage of the second MIS transistor Tr2.

  For this reason, the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture is increased in the second channel region 13b after manufacture by the heat treatment performed after the formation of the first and second channel regions. Even if the threshold voltage of the first MIS transistor Tr1 may be lower than the threshold voltage of the second MIS transistor Tr2 due to being lower than the average impurity concentration of the p-type impurity at The threshold voltage of the first MIS transistor Tr1 can be made higher than the threshold voltage of the second MIS transistor Tr2. Therefore, comprehensively, the threshold voltage of the first MIS transistor Tr1 and the threshold voltage of the second MIS transistor Tr2 can be made the same.

  As described above, the average adjustment metal concentration of the adjustment metal in the first gate insulating film 15A is made lower than the average adjustment metal concentration of the adjustment metal in the second gate insulating film 15B. It is possible to compensate for the difference in threshold voltage between the first and second MIS transistors Tr1 and Tr2, which is caused by the difference in the average impurity concentration of the p-type impurities in the first and second channel regions 13a and 13b. Therefore, the threshold voltages of the first and second MIS transistors Tr1 and Tr2 can be controlled to a desired threshold voltage.

  For this reason, even if the LSI is highly integrated, the reverse narrow channel effect occurs (that is, the threshold voltage of the MIS transistor decreases as the gate width of the MIS transistor decreases). By reducing the average adjustment metal concentration of the adjustment metal in the medium, it is possible to compensate for a decrease in the threshold voltage of the MIS transistor due to the reverse narrow channel effect. For this reason, the LSI can be highly integrated while controlling the threshold voltage of the MIS transistor to a desired threshold voltage, so that the high integration of the LSI can be accelerated.

  For example, when the first MIS transistor Tr1 is used as a transistor constituting a memory such as an SRAM, the memory is highly integrated while controlling the threshold voltage of the first MIS transistor Tr1 to a desired threshold voltage. Therefore, high integration of the memory can be accelerated.

(Second Embodiment)
2A to 2C, FIGS. 3A to 3C, and FIGS. 4A to 4C are described below with respect to a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The description will be given with reference. 2A to 4C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. In FIG. 2A to FIG. 4C, a first nMIS region, a first pMIS region, a second pMIS region, and a second nMIS region are shown in order from the left side. 2A to 4C, the “first pMIS region” refers to a region where a p-type third MIS transistor is formed. The “second pMIS region” refers to a region where a p-type fourth MIS transistor is formed. The first and third MIS transistors are transistors used for SRAM, for example. The second and fourth MIS transistors are transistors used in a logic circuit, for example. 2 (a) to 4 (c), the same reference numerals as those shown in FIGS. 1 (a) to (c) are assigned to the same components as those in the first embodiment.

First, as shown in FIG. 2A, for example, silicon oxide is formed in an upper portion of a semiconductor substrate 10 made of, for example, silicon (Si), for example, in a trench having a depth of 200 nm to 400 nm by, for example, STI (Shallow Trench Isolation). The element isolation region 11 in which the film (SiO ₂ film) is embedded is selectively formed. As a result, first and second active regions 10 a and 10 b surrounded by the element isolation region 11 are formed in the first and second nMIS regions of the semiconductor substrate 10. At the same time, third and fourth active regions 10 c and 10 d surrounded by the element isolation region 11 are formed in the first and second pMIS regions in the semiconductor substrate 10. The width of the first active region 10a in the gate width direction (ie, the first gate width) W1 is smaller than the width of the second active region 10b in the gate width direction (ie, the second gate width) W2 ( W1 <W2). The first gate width W1 is, for example, 100 nm or less. The second gate width W2 is, for example, 200 nm or more. The width of the third active region 10c in the gate width direction (ie, the third gate width) is smaller than the width of the fourth active region 10d in the gate width direction (ie, the fourth gate width).

  Thereafter, first and second p-type well regions 12x and 12y are formed in the first and second nMIS regions in the semiconductor substrate 10. On the other hand, the n-type well region 12z is formed in the first and second pMIS regions in the semiconductor substrate 10.

After that, by ion implantation, for example, an implantation energy of 10 keV and an implantation dose of 5 × 10 ¹² ions / cm ² are implanted into the first and second active regions 10a and 10b, for example, boron (B). A p-type impurity is implanted. As a result, p-type first and second channel regions 13A and 13B are formed above the first and second active regions 10a and 10b. On the other hand, by ion implantation, for example, arsenic (As) or the like is implanted into the third and fourth active regions 10c and 10d under an ion implantation condition of an implantation energy of 85 keV and an implantation dose of 7 × 10 ¹² ions / cm ² , for example. An n-type impurity is implanted. As a result, n-type third and fourth channel regions 13C and 13D are formed above the third and fourth active regions 10c and 10d.

  At this time, since the first channel region 13A and the second channel region 13B are formed under the same ion implantation conditions, the average impurity concentration X13A of the p-type impurity in the first channel region 13A immediately after the formation is The average impurity concentration X13B of the p-type impurity in the second channel region 13B immediately after formation is the same (X13A = X13B). Similarly, the average impurity concentration of n-type impurities in the third channel region 13C and the average impurity concentration of n-type impurities in the fourth channel region 13D are the same.

  Next, as shown in FIG. 2B, the surface portions of the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b are formed by, for example, heat treatment in an atmosphere containing oxygen gas. Oxidize. As a result, the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b are formed of, for example, a silicon oxide film having a thickness of 1 nm to 2 nm. Two interface layers 14A, 14C, 14D, and 14B are formed.

  After that, for example, by MOCVD (Metal Organic Chemical Vapor Deposition) method, using, for example, tetradimethylaminosilicon and tetradiethylaminohafnium as raw materials, the entire surface of the semiconductor substrate 10 is made of a high-concentration HfSiO film having a thickness of 1 nm to 2 nm, for example. A dielectric insulating film 15 is formed.

  In this manner, the first, third, fourth, and second interface layers 14A, 14C, 14D, and 14B are formed on the first, third, fourth, and second active regions 10a, 10c, 10d, and 10b. Then, a gate insulating film forming film having the high dielectric constant insulating film 15 is formed.

  Thereafter, an adjustment metal film 16 containing, for example, aluminum (Al) with a film thickness of 0.5 nm to 1.5 nm is formed on the high dielectric constant insulating film 15 by, for example, sputtering or ALD (Atomic Layer Deposition). . Thereafter, a protective film 17 made of, for example, a titanium nitride film (TiN film) having a thickness of 10 nm to 20 nm is formed on the adjustment metal film 16 by, for example, sputtering or ALD.

  Next, as shown in FIG. 2C, a resist Re1 is formed on the protective film 17 by lithography so as to open the first and second nMIS regions and cover the first and second pMIS regions. Thereafter, the portions formed in the first and second nMIS regions in the protective film 17 and the adjustment metal film 16 are removed by wet etching, for example, using the resist Re1 as a mask. Thereafter, the resist Re1 is removed.

  Next, as shown in FIG. 3A, an adjustment metal film 18 containing La having a film thickness of 0.5 nm to 1.5 nm, for example, is formed on the entire surface of the semiconductor substrate 10 by, eg, sputtering.

  Next, as shown in FIG. 3B, the first n and first pMIS regions are opened and the second p and second nMIS regions are covered on the adjustment metal film 18 by lithography. A resist Re2 is formed. The resist Re2 may be any resist that opens at least a region corresponding to the first active region 10a. Thereafter, the portion formed in the first n and first pMIS regions in the adjustment metal film 18 is removed by wet etching, for example, using the resist Re2 as a mask, and the portion is thinned. Thereby, the film thickness of the portion is set to, for example, 0.2 nm to 0.8 nm. The film thickness of the portion is set based on the first and second gate widths (see FIG. 2A: W1 and W2) and the film thickness of the adjustment metal film 18.

  In this way, in the gate insulating film forming film having the first to fourth interface layers 14A to 14D and the high dielectric constant insulating film 15, the first region located on the first active region 10a is A first adjustment metal film 18a having a thickness of 1 (for example, 0.2 nm to 0.8 nm) is formed. On the other hand, a second adjustment metal having a second film thickness (for example, 0.5 nm to 1.5 nm) on the second region located on the second active region 10b in the gate insulating film formation film. A film 18b is formed.

  Thereafter, the resist Re2 is removed.

  Next, as shown in FIG. 3C, for example, heat treatment is performed at 700 ° C. for 120 seconds.

  As a result, the adjustment metal (for example, La) in the first adjustment metal film 18a is applied to the first region in the gate insulating film formation film (particularly, on the first active region 10a in the high dielectric constant insulating film 15). The first gate insulating film forming film 15X having the first interface layer 14A and the first high dielectric constant insulating film 15x containing the adjusting metal is formed. The first high dielectric constant insulating film 15x is made of, for example, an HfSiO film containing La.

  At the same time, the adjustment metal (for example, Al) in the adjustment metal film 16 is moved to the third and fourth regions (particularly, on the third and fourth active regions 10c and 10d in the gate insulating film formation film). The third dielectric layer 15 is introduced into the third and fourth active regions 10c and 10d) in the high dielectric constant insulating film 15, and the third high and the fourth interface layers 14C and 14D and the third metal including the adjusting metal are introduced. A third gate insulating film forming film 15Z having a dielectric constant insulating film 15z is formed. The third high dielectric constant insulating film 15z is made of, for example, an HfSiO film containing Al.

  At the same time, the adjustment metal (for example, La) in the second adjustment metal film 18b is applied to the second region in the gate insulating film formation film (in particular, on the second active region 10b in the high dielectric constant insulating film 15). The second gate insulating film forming film 15Y having the second interface layer 14B and the second high dielectric constant insulating film 15y containing the adjusting metal is formed. The second high dielectric constant insulating film 15y is made of, for example, an HfSiO film containing La.

  The first film thickness (for example, 0.2 nm to 0.8 nm) of the first adjustment metal film 18a is changed to the second film thickness (for example, 0.5 nm to 1.5 nm) of the second adjustment metal film 18b. The average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film 15x is set to be smaller than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film 15y. Can be lowered. The average La concentration of La in the first high dielectric constant insulating film 15x is, for example, 20% or less. The average La concentration of La in the second high dielectric constant insulating film 15y is, for example, 25%.

  Next, as shown in FIG. 4A, unreacted portions in the first and second adjustment metal films 18a and 18b, unreacted portions in the protective film 17 and the adjustment metal film 16, for example, by wet etching. Remove parts sequentially. Thereafter, a metal film 19 made of, for example, a TiN film having a thickness of 10 nm to 20 nm is formed on the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y by, for example, ALD. Thereafter, a silicon film 20 made of a polysilicon film having a film thickness of, for example, 70 nm to 100 nm is formed on the metal film 19 by, eg, CVD.

  In this manner, a gate electrode forming film having the metal film 19 and the silicon film 20 is formed on the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y.

  Next, as shown in FIG. 4B, a resist (not shown) is formed on the silicon film 20 by lithography. Thereafter, the gate electrode forming film and the first, third, and second gate insulating film forming films 15X, 15Z, and 15Y are sequentially patterned by etching using the resist as a mask.

  As a result, the first gate insulating film 15A having the first interface layer 14a and the first high dielectric constant insulating film 15a containing the adjustment metal on the first active region 10a, and the first metal film 19a. Then, the first gate electrode 20A having the first silicon film 20a is sequentially formed.

  At the same time, the third gate insulating film 15C having the third interface layer 14c and the third high dielectric constant insulating film 15c containing the adjusting metal on the third active region 10c, and the third metal film 19c. Then, the third gate electrode 20C having the third silicon film 20c is sequentially formed.

  At the same time, the fourth gate insulating film 15D having the fourth interface layer 14d and the fourth high dielectric constant insulating film 15d containing the adjusting metal on the fourth active region 10d, and the fourth metal film 19d. Then, a fourth gate electrode 20D having the fourth silicon film 20d is sequentially formed.

  At the same time, the second gate insulating film 15B having the second interface layer 14b and the second high dielectric constant insulating film 15b containing the adjusting metal on the second active region 10b, and the second metal film 19b. Then, the second gate electrode 20B having the second silicon film 20b is sequentially formed.

  The first gate electrode 20A and the third gate electrode 20C are integrally formed. The fourth gate electrode 20D and the second gate electrode 20B are integrally formed.

  The average adjustment metal concentration of the adjustment metal (for example, La) in the first high dielectric constant insulating film 15a is the average adjustment metal concentration of the adjustment metal (for example, La) in the second high dielectric constant insulating film 15b. Lower than. On the other hand, for the average adjustment metal concentration of the adjustment metal (for example, Al) in the third high dielectric constant insulating film 15c, and for the average adjustment of the adjustment metal (for example, Al) in the fourth high dielectric constant insulating film 15d. The metal concentration is the same.

  Next, as shown in FIG. 4C, on the side surfaces of the first, third, fourth, and second gate electrodes 20A, 20C, 20D, and 20B, the first and first cross-sectional shapes are I-shaped. Third, fourth and second offset spacers 31a, 31c, 31d and 31b are formed. The first offset spacer 31a and the third offset spacer 31c are integrally formed. The fourth offset spacer 31d and the second offset spacer 31b are integrally formed.

  4C is a cross-sectional view in the gate width direction and not in the gate length direction. Therefore, the first and second active regions are not shown in FIG. 4C. First and second n-type extension implantation regions are formed under the sides of the first and second gate electrodes 20A and 20B in 10a and 10b. On the other hand, first and second p-type extension implantation regions are formed in the third and fourth active regions 10c and 10d below the third and fourth gate electrodes 20C and 20D.

  Thereafter, as shown in FIG. 4C, the first, third, fourth and second gate electrodes 20A, 20C, 20D and 20B are formed on the side surfaces of the first, third, fourth and second gate electrodes 20A, 20C, 20D and 20B. First, third, fourth and second sidewalls 33a, 33c, 33d and 33b are formed via offset spacers 31a, 31c, 31d and 31b. The first sidewall 33a and the third sidewall 33c are integrally formed. The fourth sidewall 33d and the second sidewall 33b are integrally formed.

  Thereafter, although not shown in FIG. 4 (c), the first and second n-types are formed on the outer sides of the first and second sidewalls 33a and 33b in the first and second active regions 10a and 10b. A source / drain implantation region is formed. On the other hand, first and second p-type source / drain implantation regions are formed on the outer sides of the third and fourth sidewalls 33c and 33d in the third and fourth active regions 10c and 10d.

  Thereafter, for example, heat treatment is performed at 1000 ° C. for 1 second.

  As a result, the n-type impurities contained in the first and second n-type extension implantation regions are activated to form the first and second n-type extension regions (see FIG. 1C: 22a and 22b). To do. On the other hand, p-type impurities contained in the first and second p-type extension implantation regions are activated to form first and second p-type extension regions.

  At the same time, the n-type impurity contained in the first and second n-type source / drain implantation regions is activated, and the first and second n-type source / drain regions (see FIG. 1 (c): 24a and 24b). Form. On the other hand, the p-type impurities contained in the first and second p-type source / drain implantation regions are activated to form first and second p-type source / drain regions.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  In the present embodiment, the average impurity concentration of the p-type impurity in the first channel region 13A immediately after formation (see FIG. 2A) and the second channel region 13B immediately after formation (see FIG. 2A) The average impurity concentration of the p-type impurities therein is the same. However, the heat treatment performed after the formation of the first and second channel regions 13A and 13B (for example, the n-type impurities contained in the first and second n-type source / drain implantation regions, and the first and second channel regions) The p-type impurities contained in the first and second channel regions 13A and 13B are caused to enter the element isolation region 11 by heat treatment for activating the p-type impurities contained in the p-type source / drain implantation region. Spread. For this reason, the average impurity concentration of the p-type impurity in the first channel region 13a after manufacture (see FIG. 4C) is the same as that in the second channel region 13b after manufacture (see FIG. 4C). It becomes lower than the average impurity concentration of the p-type impurity.

  Similarly, the average impurity concentration of the n-type impurity in the third channel region 13C (see FIG. 2 (a)) immediately after formation and the fourth channel region 13D (see FIG. 2 (a)) immediately after formation. The average impurity concentration of the n-type impurity is the same. However, the heat treatment performed after the formation of the third and fourth channel regions 13C and 13D (for example, the n-type impurities contained in the first and second n-type source / drain implantation regions, and the first and second The n-type impurities contained in the third and fourth channel regions 13C and 13D are caused to enter the element isolation region 11 by heat treatment for activating the p-type impurities contained in the p-type source / drain implantation region. Spread. Therefore, the average impurity concentration of the n-type impurity in the third channel region 13c after manufacture (see FIG. 4C) is the same as that in the fourth channel region 13d after manufacture (see FIG. 4C). It becomes lower than the average impurity concentration of n-type impurities.

  The first MIS transistor Tr1 includes the same components as the first MIS transistor Tr1 in the first embodiment. However, in the present embodiment, since the first gate electrode 20A is formed integrally with the third gate electrode 20C as shown in FIG. 4 (c), of the side surfaces of the first gate electrode 20A, The first sidewall 33a is formed on the side surface other than the side surface adjacent to the third gate electrode 20C via the first offset spacer 31a.

  The second MIS transistor Tr2 includes the same components as the second MIS transistor Tr2 in the first embodiment. However, in the present embodiment, as shown in FIG. 4C, the second gate electrode 20B is formed integrally with the fourth gate electrode 20D, and therefore, of the side surfaces of the second gate electrode 20B. The second sidewall 33b is formed on the side surface other than the side surface adjacent to the fourth gate electrode 20D via the second offset spacer 31b.

  As shown in FIG. 4 (c), the third and fourth MIS transistors Tr3 and Tr4 include third and fourth gate insulating films 15C, 15C formed on the third and fourth active regions 10c and 10d, respectively. 15D, the third and fourth gate electrodes 20C and 20D formed on the third and fourth gate insulating films 15C and 15D, and the third and fourth gates in the third and fourth active regions 10c and 10d. N-type third and fourth channel regions 13c and 13d formed immediately below the gate electrodes 20C and 20D, and third and third channels formed on the side surfaces of the third and fourth gate electrodes 20C and 20D. Four offset spacers 31c and 31d, and first and second p-type extension regions formed laterally below the third and fourth gate electrodes 20C and 20D in the third and fourth active regions 10c and 10d. And the third and fourth gate electrodes 20C, The third and fourth sidewalls 33c and 33d formed on the side surface of 20D via the third and fourth offset spacers 31c and 31d, and the third and fourth active regions 10c and 10d And first and second p-type source / drain regions formed outside the fourth sidewalls 33c and 33d.

  The third and fourth gate insulating films 15C and 15D have third and fourth interface layers 14c and 14d and third and fourth high dielectric constant insulating films 15c and 15d. The third and fourth gate electrodes 20C and 20D have third and fourth metal films 19c and 19d and third and fourth silicon films 20c and 20d.

  The average adjusting metal concentration of the adjusting metal (for example, La) in the first gate insulating film 15A is lower than the average adjusting metal concentration of the adjusting metal (for example, La) in the second gate insulating film 15B. On the other hand, the average adjustment metal concentration of the adjustment metal (for example, Al) in the third gate insulating film 15C and the average adjustment metal concentration of the adjustment metal (for example, Al) in the fourth gate insulating film 15D are as follows. The same.

  The average adjustment metal concentration of the adjustment metal (for example, La) in the first high dielectric constant insulating film 15a is the average adjustment metal concentration of the adjustment metal (for example, La) in the second high dielectric constant insulating film 15b. Lower than. On the other hand, for the average adjustment metal concentration of the adjustment metal (for example, Al) in the third high dielectric constant insulating film 15c, and for the average adjustment of the adjustment metal (for example, Al) in the fourth high dielectric constant insulating film 15d. The metal concentration is the same.

  The average impurity concentration of the p-type impurity in the first channel region 13a is lower than the average impurity concentration of the p-type impurity in the second channel region 13b. Similarly, the average impurity concentration of n-type impurities in the third channel region 13c is lower than the average impurity concentration of n-type impurities in the fourth channel region 13d.

  According to this embodiment, the same effect as that of the first embodiment can be obtained.

  In the present embodiment, the manufacturing method of the semiconductor device including the first, third, fourth, and second MIS transistors has been described. However, the semiconductor according to the first embodiment is manufactured by the same manufacturing method as the present embodiment. A device (that is, a semiconductor device including first and second MIS transistors) can be manufactured. Specifically, after performing the same process as that shown in the first and second nMIS regions in FIG. 2 (a), the first and second nMISs in FIGS. 3 (a) to 4 (c) are performed. The semiconductor device according to the first embodiment can be manufactured by sequentially performing the same processes as those shown in the region.

<Modification of Second Embodiment>
A method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention will be described below with reference to FIGS. 5 (a) to 5 (c). FIGS. 5A to 5C are cross-sectional views in the gate width direction showing the method of manufacturing the semiconductor device according to the modification of the second embodiment of the present invention in the order of steps. 5A to 5C, the same reference numerals as those shown in FIGS. 2A to 4C are assigned to the same components as those in the second embodiment. Therefore, in this modification, the description similar to that of the second embodiment is omitted as appropriate.

  First, steps similar to those shown in FIGS. 2A to 2C in the second embodiment are sequentially performed.

  Next, a step similar to the step shown in FIG. Specifically, the adjustment metal film 18 containing La with a film thickness of 0.5 nm to 1.5 nm, for example, is formed on the entire surface of the semiconductor substrate 10 by, for example, sputtering.

  Next, as shown in FIG. 5A, for example, heat treatment (first heat treatment) is performed at 650 ° C. for 120 seconds.

  Thus, the adjustment metal (for example, La) in the adjustment metal film 18 is removed from the first region in the gate insulating film formation film (particularly, the region located on the first active region 10a in the high dielectric constant insulating film 15). The first gate insulating film forming film 15X having the first interface layer 14A and the first high dielectric constant insulating film 15x containing the adjusting metal is formed.

  At the same time, the adjustment metal (for example, Al) in the adjustment metal film 16 is applied to the third and fourth regions in the gate insulating film formation film (in particular, the third and fourth active regions in the high dielectric constant insulating film 15). 10c and 10d), a high dielectric constant insulating film 15w containing an adjustment metal is formed.

  At the same time, the adjustment metal (for example, La) in the adjustment metal film 18 is applied to the second region in the gate insulating film formation film (particularly, the region located on the second active region 10b in the high dielectric constant insulating film 15). ) To form a high dielectric constant insulating film 15v containing an adjustment metal.

  Next, as shown in FIG. 5B, a resist that opens the first nMIS region and covers the first and second pMIS regions and the second nMIS region on the adjustment metal film 18 by lithography. Re3 is formed. Thereafter, the portion of the adjustment metal film 18 located on the first gate insulating film forming film 15X is removed by wet etching, for example, using the resist Re3 as a mask.

  Thereafter, the resist Re3 is removed.

  Next, as shown in FIG. 5C, for example, a heat treatment (second heat treatment) at 900 ° C. for 30 seconds is performed.

  Thereby, the adjustment metal (for example, Al) in the adjustment metal film 16 is additionally introduced into the third and fourth regions (particularly, the high dielectric constant insulating film 15w including the adjustment metal) in the gate insulating film formation film. Then, the third gate insulating film forming film 15Z having the third high dielectric constant insulating film 15z including the third and fourth interface layers 14C and 14D and the adjusting metal is formed.

  At the same time, the adjustment metal (for example, La) in the adjustment metal film 18 is additionally introduced into the second region (particularly, the high dielectric constant insulating film 15v including the adjustment metal) in the gate insulating film formation film, A second gate insulating film forming film 15Y having the second interface layer 14B and the second high dielectric constant insulating film 15y containing the adjusting metal is formed.

  Next, steps similar to those shown in FIGS. 4A to 4C in the second embodiment are sequentially performed.

  As described above, the semiconductor device according to this modification can be manufactured.

  In this modification, as shown in FIG. 5A, the adjustment metal in the adjustment metal film 18 is removed from the first and second regions (especially high regions) in the gate insulating film formation film by the first heat treatment. After being introduced into the first and second active regions 10a and 10b in the dielectric constant insulating film 15, as shown in FIG. The adjusting metal is additionally introduced only into the second region in the gate insulating film formation film (particularly, the region located on the second active region 10b in the high dielectric constant insulating film 15). Therefore, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film 15x is made lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film 15y. The average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film 15X can be made lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film 15Y. Can do.

  According to this modification, the same effect as that of the second embodiment can be obtained.

  In the second embodiment, the first gate insulating film forming film 15X and the second gate insulating film forming film in which the average adjusting metal concentration of the adjusting metal is higher than that of the first gate insulating film forming film 15X. As a method of forming 15Y, as shown in FIGS. 3A to 3B, a first adjustment metal film 18a having a first film thickness is formed on the first region in the gate insulating film formation film 15. On the other hand, after the second adjustment metal film 18b having a second film thickness larger than the first film thickness is formed on the second region in the gate insulating film formation film 15, FIG. As shown in c), for example, the case of performing heat treatment at 700 ° C. for 120 seconds has been described as a specific example, but the present invention is not limited to this.

  First, for example, the first and second gate insulating film formation films may be formed by the method described in the modification of the second embodiment.

  Second, for example, the first and second gate insulating film formation films may be formed by the method described below.

  First, steps similar to those shown in FIGS. 2A to 2B in the second embodiment are sequentially performed.

  Next, not the resist (see FIG. 2C: Re1) that opens the first and second nMIS regions and covers the first and second pMIS regions, but the central region in the first nMIS region, Then, a resist that opens the second nMIS region and covers the peripheral region (region other than the central region) and the first and second pMIS regions in the first nMIS region is formed. Thus, not the resist that exposes the entire region in the region corresponding to the first active region (see FIG. 2C: Re1), but the resist that exposes only the central region in the region corresponding to the first active region. Form.

  Thereafter, portions of the protective film 17 and the adjustment metal film 16 other than the portion covered with the resist (that is, the central region in the first nMIS region and the portion formed in the second nMIS region) are removed. Thereafter, the resist is removed.

  Next, after performing the same process as the process shown in FIG. 3A in the second embodiment, the process shown in FIG. 3B (that is, the first n, pMIS region in the adjustment metal film 18). The step shown in FIG. 3 (c) in the second embodiment (that is, the adjustment metal in the adjustment metal film is increased by heat treatment without performing the same step as the step of thinning the portion formed in FIG. A step similar to that in the step of introducing the dielectric constant insulating film is performed.

  In this case, the region located on the first active region in the high dielectric constant insulating film during the heat treatment for introducing the adjustment metal (for example, La) in the adjustment metal film into the high dielectric constant insulating film, While only the central portion is in contact with the adjustment metal film, the entire region of the region located on the second active region in the high dielectric constant insulating film is in contact with the adjustment metal film. Therefore, the average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film can be made lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film. The average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film can be made lower than the average adjusting metal concentration of the adjusting metal in the second gate insulating film forming film.

  In the second embodiment and the modification thereof, the average adjustment metal concentration of the adjustment metal (for example, Al) in the third gate insulating film 15C and the adjustment metal in the fourth gate insulating film 15D ( For example, the case where the average adjustment metal concentration of Al) is the same has been described as a specific example, but the present invention is not limited to this.

  As described above, the average impurity concentration of the n-type impurity in the third channel region 13c is increased in the fourth channel region 13d by the heat treatment performed after the formation of the third and fourth channel regions 13C and 13D. It becomes lower than the average impurity concentration of n-type impurities. For this reason, the threshold voltage of the third MIS transistor Tr3 may be lower than the threshold voltage of the fourth MIS transistor Tr4.

  Therefore, the average adjustment metal concentration of the adjustment metal in the third gate insulating film is made lower than the average adjustment metal concentration of the adjustment metal in the fourth gate insulating film. As a result, it is possible to compensate for the difference in the threshold voltages of the third and fourth MIS transistors caused by the difference in the average impurity concentration of the n-type impurities in the third and fourth channel regions. For this reason, the threshold voltage of the third and fourth MIS transistors can be controlled to a desired threshold voltage.

  In the first embodiment, the second embodiment, and modifications thereof, the case where La is used as the adjustment metal contained in the first and second gate insulating films 15A and 15B will be described as a specific example. However, the present invention is not limited to this. For example, other lanthanoid elements or magnesium (Mg) may be used instead of La.

  In the second embodiment and its modification, the case where Al is used as the adjustment metal contained in the third and fourth gate insulating films 15C and 15D has been described as a specific example. For example, tantalum oxide (TaO) may be used instead of Al.

  As described above, the present invention can control the threshold voltage of the first and second MIS transistors to a desired threshold voltage, and thus includes the first and second MIS transistors having different gate widths. It is useful for a semiconductor device and a method for manufacturing the same.

10 semiconductor substrate 10a first active region 10b second active region 10c third active region 10d fourth active region 11 element isolation region 12x first p-type well region 12y second p-type well region 12z n-type Well regions 13A, 13a First channel regions 13B, 13b Second channel regions 13C, 13c Third channel regions 13D, 13d Fourth channel regions 14A, 14a First interface layers 14B, 14b Second interface layers 14C, 14c Third interface layer 14D, 14d Fourth interface layer 15 High dielectric constant insulating film 15v High dielectric constant insulating film 15w High dielectric constant insulating film 15x First high dielectric constant insulating film 15y Second high dielectric constant Insulating film 15z Third high dielectric constant insulating film 15X First gate insulating film forming film 15Y Second gate insulating film forming film 15Z Third gate insulating film forming film 15a First High dielectric constant insulating film 15b Second high dielectric constant insulating film 15c Third high dielectric constant insulating film 15d Fourth high dielectric constant insulating film 15A First gate insulating film 15B Second gate insulating film 15C Third Gate insulating film 15D fourth gate insulating film 16 adjustment metal film 17 protective film 18 adjustment metal film 18a first adjustment metal film 18b second adjustment metal film 19 metal film 20 silicon film 19a first Metal film 19b second metal film 19c third metal film 19d fourth metal film 20a first silicon film 20b second silicon film 20c third silicon film 20d fourth silicon film 20A first gate electrode 20B 2nd gate electrode 20C 3rd gate electrode 20D 4th gate electrode 21a, 31a 1st offset spacer 21b, 31b 2nd offset spacer 31c 3rd offset Spacer 31d fourth offset spacer 22a first n-type extension region 22b second n-type extension region 23a, 33a first sidewall 23b, 33b second sidewall 33c third sidewall 33d fourth side Wall 24a First n-type source / drain region 24b Second n-type source / drain region Re1-Re3 Resist W1 First gate width W2 Second gate width

Claims (12)

A semiconductor device comprising a first MIS transistor and a second MIS transistor,
The first MIS transistor is
A first gate insulating film formed on a first active region in a semiconductor substrate and having a first high dielectric constant insulating film;
A first gate electrode formed on the first gate insulating film,
The second MIS transistor is
A second gate insulating film formed on a second active region in the semiconductor substrate and having a second high dielectric constant insulating film;
A second gate electrode formed on the second gate insulating film,
Each of the first gate insulating film and the second gate insulating film includes an adjustment metal,
A first gate width of the first MIS transistor is smaller than a second gate width of the second MIS transistor;
An average adjustment metal concentration of the adjustment metal in the first gate insulating film is lower than an average adjustment metal concentration of the adjustment metal in the second gate insulating film. apparatus. The semiconductor device according to claim 1,
A first channel region containing a first impurity formed immediately below the first gate electrode in the first active region;
A second channel region containing a second impurity formed immediately below the second gate electrode in the second active region,
The semiconductor device, wherein an average impurity concentration of the first impurity in the first channel region is lower than an average impurity concentration of the second impurity in the second channel region. The semiconductor device according to claim 1 or 2,
The first gate width is 100 nm or less;
The semiconductor device according to claim 1, wherein the second gate width is 200 nm or more. The semiconductor device according to any one of claims 1 to 3,
The first MIS transistor and the second MIS transistor are n-type MIS transistors,
The semiconductor device according to claim 1, wherein the adjustment metal is lanthanum. The semiconductor device of any one of Claims 1-4 WHEREIN:
The average adjustment metal concentration of the adjustment metal in the first high dielectric constant insulating film is lower than the average adjustment metal concentration of the adjustment metal in the second high dielectric constant insulating film. A featured semiconductor device. The semiconductor device according to any one of claims 1 to 5,
The first gate insulating film includes a first interface layer formed on the first active region and the first high dielectric constant insulating film formed on the first interface layer. ,
The second gate insulating film includes a second interface layer formed on the second active region and the second high dielectric constant insulating film formed on the second interface layer. A semiconductor device. The semiconductor device according to claim 6.
The semiconductor device according to claim 1, wherein the first interface layer and the second interface layer are made of a silicon oxide film. The semiconductor device according to any one of claims 1 to 7,
The first high dielectric constant insulating film and the second high dielectric constant insulating film are made of a metal oxide having a relative dielectric constant of 10 or more. The semiconductor device according to any one of claims 1 to 8,
The first gate electrode includes a first metal film formed on the first gate insulating film and a first silicon film formed on the first metal film,
The second gate electrode includes a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film. Semiconductor device. A first MIS transistor having a first gate insulating film and a first gate electrode formed on the first active region in the semiconductor substrate, and a second MIS transistor formed on the second active region in the semiconductor substrate. A method of manufacturing a semiconductor device comprising: a second MIS transistor having a gate insulating film and a second gate electrode;
Forming a gate insulating film forming film having a high dielectric constant insulating film on the first active region and the second active region;
An adjustment metal is introduced into a first region located on the first active region in the gate insulating film forming film to form a first gate insulating film forming film, while the gate insulating film forming film includes the (B) forming the second gate insulating film forming film by introducing the adjustment metal into the second region located on the second active region;
A step (c) of forming a gate electrode formation film on the first gate insulation film formation film and the second gate insulation film formation film;
The gate electrode forming film, the first gate insulating film forming film, and the second gate insulating film forming film are patterned to form a first gate insulating film forming film on the first active region. Forming a first gate electrode comprising the first gate insulating film and the gate electrode forming film, while forming a second gate insulating film comprising the second gate insulating film forming film on the second active region; Forming a second gate electrode made of a gate electrode formation film (d),
A first gate width of the first MIS transistor is smaller than a second gate width of the second MIS transistor;
In the step (b), the average adjusting metal concentration of the adjusting metal in the first gate insulating film forming film is equal to the average adjusting metal of the adjusting metal in the second gate insulating film forming film. A method of manufacturing a semiconductor device, wherein the first gate insulating film forming film and the second gate insulating film forming film are formed so as to be lower than a concentration. In the manufacturing method of the semiconductor device according to claim 10,
The step (b) is a step (b1) of forming a first adjustment metal film having a first film thickness and including the adjustment metal on the first region in the gate insulating film formation film. And (b2) forming a second adjustment metal film having a second film thickness and including the adjustment metal on the second region in the gate insulating film formation film, After the step (b1) and the step (b2), the adjustment metal in the first adjustment metal film is introduced into the first region of the gate insulating film formation film by heat treatment to introduce the first Forming a gate insulating film forming film and introducing the adjusting metal in the second adjusting metal film into the second region of the gate insulating film forming film to form the second gate insulating film forming film; A step (b3) of forming
The method of manufacturing a semiconductor device, wherein the first film thickness is thinner than the second film thickness. In the manufacturing method of the semiconductor device according to claim 10,
The step (b) includes a step (b1) of forming an adjustment metal film including the adjustment metal on the gate insulating film formation film, and a first heat treatment after the step (b1). The adjustment metal in the adjustment metal film is introduced into the first region of the gate insulation film formation film to form the first gate insulation film formation film, and the adjustment metal in the adjustment metal film is formed. After the step (b2) of introducing metal into the second region in the gate insulating film forming film and the step (b2), the metal is positioned on the first gate insulating film forming film in the adjustment metal film. After the step (b3) of removing the portion and the step (b3), the adjustment metal in the adjustment metal film is additionally introduced into the second region in the gate insulating film formation film by a second heat treatment. The second gate insulating film forming film The method of manufacturing a semiconductor device characterized by and a step (b4) to be formed.

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