JP2011228375A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve, for use in probe testing of semiconductor devices, a reduction of the number of probe needles to the necessary minimum and power supply margins for the semiconductor devices.SOLUTION: There are provided mutually adjoining first power pad electrode 21 and second power pad electrode 22 that supply power to an internal circuit and mutually adjoining first grounding pad electrode 23 and second grounding pad electrode 24 that supply grounding to the internal circuit, wherein, one power pad electrode out of the first and second power pad electrodes is connected by a probe needle 4, one grounding pad electrode out of the first and second grounding pad electrodes is connected by a probe needle 4, the first power pad electrode and the second power pad electrode are connected by metal wiring 10, and similarly the first grounding pad electrode and the second grounding pad electrode are connected by metal wiring 10.

Description

  The present invention relates to a layout configuration and a package configuration during pattern design of a semiconductor device (LSI).

  Conventionally, when designing a layout of a semiconductor device, it is common to arrange an indispensable number of power pad electrodes and ground pad electrodes according to the circuit scale of the layout. If it is insufficient, sufficient power cannot be supplied to the semiconductor device. Conversely, if it is too much, the LSI price will increase. Therefore, it is general to provide a necessary number of power pad electrodes and ground pad electrodes according to the layout scale.

  Further, in the selection of non-defective products of LSI using an LSI tester, generally, selection is performed even in a wafer state before packaging. This is a contrivance for sorting out defective products as much as possible in a wafer state where the manufacturing cost is lower than sorting after packaging defective products so as not to waste costs.

  FIG. 3 is a flowchart showing the flow of general non-defective product selection (test) for a semiconductor device. In a normal semiconductor device test, an operation test is first performed on a semiconductor chip in a wafer state. This is generally called a wafer check (wafer test). In the wafer check as described above, generally, a needle-like probe (hereinafter simply referred to as “probe”) is brought into contact with a pad electrode on a semiconductor wafer (chip) to apply a test signal or power supply. Supply voltage and ground voltage. Here, a probe card having a plurality of such probes is referred to as a probe card, an operation test performed using the probe card is referred to as a “probe test”, and step 1 (S1) is performed. Then, if a normal expected value is used as an output signal for the applied test signal, it is determined 1 (S2) that the function is operating normally. If it is OK in the determination 1 (S2), the process goes to the next stage. The non-defective product that has passed the probe test is subjected to an operation test (hereinafter referred to as “package test (S4)”) for the packaged product after performing a packaging process (S3) for mounting on the package. Then, determination 2 (S5) is performed based on the result, and the final non-defective product is selected.

  Patent Document 1 discloses a technique related to an operation test of a semiconductor device using a probe or a probe card.

JP 2007-232536 A

  However, in the above probe test, when checking the operation of a semiconductor product in a wafer state with a probe card to LSI tester configuration, dust called wafer residue is found on the probe card needle tip after repeated measurements. May stick. Then, measurement trouble may occur in the probe test. At this time, problems often occur because the power supply and the ground are not sufficiently supplied due to the influence of the resistance component of dust attached to the power supply, the power supply for supplying the ground, and the probe for the ground electrode. Therefore, in order to perform an accurate determination, it is necessary to clean the wafer tip of the probe card (polishing) and remove the wafer residue at regular intervals. The needle tip cleaning cycle varies depending on the manufacturing process, the probe card needle material, the amount of overdrive during measurement, etc. However, if this cleaning cycle is short, the probe life will be shortened and the number of new purchases will increase. However, there was a problem that the measurement cost was increased, which led to an increase in manufacturing cost and loss of profit.

  In addition, if this cleaning cycle is lengthened, the above-mentioned measurement problems occur, so that stable measurement cannot be performed, and measurement may be performed again. There was also a problem that the manufacturing cost was increased due to the deterioration of the yield.

  The present invention is a semiconductor device, formed on the semiconductor substrate of the semiconductor device, adjacent to the first and second power supply pad electrodes for supplying power to the internal circuit, and formed on the semiconductor substrate of the semiconductor device. Among the first and second power pad electrodes adjacent to each other for supplying ground to the internal circuit and the first and second power pad electrodes, one power pad electrode is connected by a bonding wire, Of the first and second ground pad electrodes, one ground pad electrode includes a lead frame connected by a bonding wire, and the first power pad electrode and the second power pad electrode are metal Connected by wiring, the first ground pad electrode and the second ground pad electrode are connected by metal wiring. It is to provide a semiconductor device characterized by being.

  According to the semiconductor device of the present invention, the measurement can be stabilized by reducing the influence of the resistance component due to dust adhering to the probe supplying power and ground, and the life of the probe card can be extended by reducing the number of cleanings. I can do it. In addition, by suppressing the occurrence of measurement defects, the production cost can be reduced and the profit can be increased by improving the yield.

It is a figure which shows the structure of the probe test of the semiconductor device which concerns on this embodiment. It is a figure which shows the packaged structure of the semiconductor device which concerns on this embodiment. It is a figure which shows the flowchart which concerns on the quality determination which concerns on this embodiment.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a probe test in an LSI tester related to a semiconductor device (wafer state) according to the present application.
There is a pad electrode 2 provided on a semiconductor substrate (wafer 1), and the pad electrode 2 is connected to an I / O cell 3. A protection diode is provided inside the I / O cell 3, and a protection circuit is configured for the power supply line and the ground line. The protection diode has a role of preventing the semiconductor device from being destroyed by electrostatic breakdown, latch-up, or the like. Through the I / O cell 3, a power supply voltage and a ground voltage can be supplied into the semiconductor device, and an input signal and an output signal used for signal processing can be applied.

  Further, there are probe needles 4 outside the wafer 1, and a plurality of probe needles 4 are connected to the LSI tester 6 through a probe card 5 provided. The LSI tester 6 can obtain the expected output signal by supplying the power supply voltage and ground voltage necessary for the actual operating environment, applying the same input signal as in the actual operating environment, and monitoring the output signal. If it is not obtained, it can be judged as defective.

  The wear 1 is connected to the internal power line 7 through the I / O cell 3 and the ground voltage is connected to the ground line 8. The power supply line 7 and the ground line 8 are supplied to a logic circuit in the semiconductor device, for example, an inverter 9 to enable the inverter 9 to operate.

  Here, the first power pad electrode 21 and the second power pad electrode 22 to which the power supply voltage is supplied are provided on adjacent pad electrodes, and similarly, the first power pad electrode to which the ground voltage is supplied. The ground pad electrode 23 and the second ground pad electrode 24 are also provided on adjacent pad electrodes.

  The first power supply pad electrode 21 and the second power supply pad electrode 22 are connected by a metal wiring 10. Similarly, the first ground pad electrode 23 and the second ground pad electrode 24 are also connected by the metal wiring 10.

  In the probe test, the probe generally contacts all the pad electrodes of the power supply pad electrode, the ground pad electrode, and the normal pad electrode (for input signal, output signal, and input / output signal) provided on the wafer 1. It will be. FIG. 1 shows a diagram in which the probe touches six pads, but the probe basically touches all the pad electrodes, but the other pads are omitted.

  At this time, in order to supply the minimum necessary power to the wafer 1 in the environment where the probe test is performed, it is sufficient to supply the power from either one of the first power pad electrode 21 and the second power pad 22. However, the power is supplied from two paths of the first power pad electrode 21 and the second power pad 22. As a result, a certain margin can be provided for the external power supply.

  Because of this margin, even if the number of probe tests is repeated, dust called wafer residue adheres to the tips of the first power supply pad electrode 21 and the second power supply pad 22, and some resistance components are attached. Immediately, the supply of power supply voltage will not be insufficient. Similarly, with respect to the ground, the first ground pad electrode 23 and the second ground pad electrode 24 are provided to ensure a certain margin, and even if dust adheres, the ground voltage cannot be supplied immediately. Things will disappear.

  For the normal pad electrode, even if some dust adheres, it is only necessary to transmit the voltage level of the H level and the L level, so that it is relatively less affected by the resistance component, like a power pad electrode or a ground pad electrode It is not necessary to have a pad electrode for margin.

  FIG. 2 is a diagram showing a configuration in which the wafer 1 is packaged. Each pad electrode 2 of the wafer 1 is connected to each lead terminal 12 of the packaged lead frame using a bonding wire 11.

  Here, the lead terminal (power supply terminal) for supplying the power supply voltage is connected to either one of the first power supply pad electrode 21 and the second power supply pad 22 by the bonding wire 11. In the figure, the first power supply pad electrode 21 is connected by the bonding wire 11 and is not connected, while the second power supply pad electrode 22 is connected to the first power supply voltage for applying a power supply voltage from the outside in the probe test. Used as a dummy pad electrode. At this time, the second power supply pad 22 has 25 after the probe touched by the probe in the probe test, and it can be seen that it was used in the probe test.

  Similarly, a lead terminal (GND terminal) that supplies a ground voltage has one of the first ground pad electrode 23 and the second ground pad 24 connected by the bonding wire 11. In the figure, the first ground pad electrode 23 is connected by the bonding wire 11 and is not connected, while the second ground pad electrode 24 is connected to the second ground electrode for applying a ground voltage from the outside in the probe test. Used as a dummy pad electrode. At this time, the second ground pad 24 has 25 after the probe touched by the probe in the probe test, and it can be seen that it was used in the probe test.

  Since there are 25 after the probe and no bonding wire 11, the first dummy pad electrode and the second dummy pad electrode were used as margin terminals for supplying the power supply voltage and the ground voltage in the probe test. That is, after being packaged, it is not connected as an LSI lead terminal and cannot be used. However, since the metal wiring 10 is connected to the pad electrode connected by the bonding wire 11, it can be used to supply a power supply voltage and a ground voltage to the wear 1.

  This is because the supply capacity of the bonding wire 11 is higher than the supply capacity from the pad electrode 2 to the I / O cell 3 and cannot be transmitted from the pad electrode 2 to the I / O cell 3. This is because the signal can be transmitted from the dummy pad electrode to the wafer 1. As a result, it is possible to effectively use the power supply voltage and the ground voltage, not just the dummy pad electrode.

  Although the best mode for carrying out the invention has been described above, the above embodiment is intended to facilitate understanding of the present invention and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  For example, in the above description, the first dummy pad electrode and the second dummy pad electrode are arranged adjacent to each other, but they are not necessarily adjacent to each other, and a plurality of them may be provided. In the embodiment, the pad electrode and the pad electrode are connected by metal wiring. However, if the power supply ring in the I / O cell is strengthened and has the same effect as the metal wiring, the metal wiring is eliminated. A power ring can be substituted. At this time, the power ring needs to be strengthened more than usual.

1 wafer 2 pad electrode 3 I / O cell
4 probe needle 5 probe card 6 LSI tester 7 power supply line 8 ground line 9 inverter 10 metal wiring 11 bonding wire 12 LSI terminal 21 first power supply pad electrode 22 second power supply pad electrode 23 first ground pad electrode 24 second The ground pad electrode

Claims (3)

A semiconductor device,
Adjacent first and second power pad electrodes formed on a semiconductor substrate of the semiconductor device and supplying power to an internal circuit;
Adjacent first and second ground pad electrodes formed on a semiconductor substrate of the semiconductor device and supplying ground to an internal circuit;
One of the first and second power pad electrodes is connected by a bonding wire, and one of the first and second ground pad electrodes is connected by a bonding wire. A connected lead frame,
The first power pad electrode and the second power pad electrode are connected by a metal wiring, and the first ground pad electrode and the second ground pad electrode are connected by a metal wiring. A featured semiconductor device. The semiconductor device according to claim 1,
Of the first and second power supply pad electrodes, the other power supply pad is a first dummy pad electrode used for applying a power supply voltage from the outside in a probe test, and the first and second power supply pad electrodes. The other power pad among the ground pad electrodes is a second dummy pad used for applying a ground voltage from the outside in a probe test. The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the first dummy pad electrode and the second dummy pad electrode have a probe contacted by a probe in a probe test.