JP2011222085A - Nonvolatile semiconductor memory and method for testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of easily identifying a memory cell in a state of excessive writing, and a method for testing the same.SOLUTION: A nonvolatile semiconductor memory comprises: a plurality of series-connected memory cell transistors by sharing a source and a drain; a plurality of word lines connected to control gates of the memory cell transistors; a first power supply for non-selection generating a non-selective word line voltage applied to non-selective word lines at the time of reading operation; a second power supply for non-selection capable of generating a second non-selective word line voltage higher than the first non-selective word line voltage; and a control circuit applying the second non-selective word line voltage to one of the word lines, and applying the first non-selective word line voltage to other word lines.

Description

  The present invention relates to a nonvolatile semiconductor memory device and a test method thereof.

  Conventionally, a NAND flash memory in which a plurality of memory cell transistors are connected in series so as to share their sources and drains is known as a nonvolatile semiconductor memory. The NAND type flash memory utilizes the fact that the threshold voltage fluctuates by injecting electrons into the floating gates constituting the memory cell transistors or releasing the electrons from the floating gates. Memorize. Therefore, it is important to measure the threshold distribution of each memory cell transistor in evaluating the write characteristics of the NAND flash memory.

  In a nonvolatile semiconductor memory typified by a NAND flash memory, as a technique for evaluating the threshold distribution of individual memory cell transistors, for example, a test circuit including a threshold detection circuit unit that detects a current change in a bit line is used. A method for detecting the minimum value of the threshold or detecting the maximum value is disclosed (for example, see Patent Document 1).

  Further, in a nonvolatile semiconductor memory typified by a NAND flash memory, an overwriting failure is known as a phenomenon that occurs due to variations in writing characteristics of individual memory cell transistors. If there is an overwritten memory cell transistor in the NAND string, the memory cell transistor is always in an off state even when the memory cell transistor is not selected, and therefore data of the selected memory cell transistor may not be read correctly ( For example, see Patent Document 2.)

JP 2002-117699 A JP 2009-151919 A

  The present invention provides a nonvolatile semiconductor memory device and a test method thereof that can easily specify an overwritten memory cell.

A nonvolatile semiconductor memory device according to an embodiment of the present invention includes:
A plurality of memory cell transistors connected in series sharing a source and drain; and
A plurality of word lines connected to a control gate of the memory cell transistor;
A first unselected power supply for generating a first unselected word line voltage applied to the unselected word line during a read operation; and a second unselected word line voltage equal to or higher than the first unselected word line voltage A second non-selection power source capable of generating the second non-selection power supply, applying the second non-selection word line voltage to one of the plurality of word lines, and applying the first non-selection word line to the other word lines And a control circuit for applying a non-selected word line voltage.

A test method for a nonvolatile semiconductor memory device according to an embodiment of the present invention includes a plurality of memory cell transistors connected in series sharing a source and a drain, and a plurality of word lines connected to a control gate of the memory cell transistor A first unselected power supply for generating a first unselected word line voltage applied to the unselected word line during a read operation, and a second unselected word greater than or equal to the first unselected word line voltage And a second non-selection power source capable of generating a line voltage, wherein the second non-selection is applied to a word line connected to a memory cell to be inspected. Applying a word line voltage and applying the first unselected word line voltage to word lines connected to other memory cells;
Determining whether a threshold value of the test target memory cell transistor is equal to or greater than a predetermined value; and overwriting the test target memory cell when the threshold value of the test target memory cell transistor is determined to be equal to or greater than a predetermined value. And determining the state.

  A test method for a nonvolatile semiconductor memory device according to an embodiment of the present invention includes a plurality of memory cell transistors connected in series sharing a source and a drain, and a plurality of word lines connected to a control gate of the memory cell transistor A first unselected power supply for generating a first unselected word line voltage applied to the unselected word line during a read operation, and a second unselected word greater than or equal to the first unselected word line voltage And a second non-selection power source capable of generating a line voltage, wherein the second non-selection is applied to a word line connected to a memory cell to be inspected. Applying a word line voltage, raising the second unselected word line voltage, and applying the first unselected word line voltage to word lines connected to other memory cells; Measuring the threshold of the inspection target memory cell transistors, characterized in that it comprises a.

  ADVANTAGE OF THE INVENTION According to this invention, the non-volatile semiconductor memory device which can identify the memory cell of an overwriting state easily, and its test method can be provided.

1 is a block diagram showing a functional configuration of a NAND flash memory. FIG. 3 is an equivalent circuit diagram illustrating a configuration example of one block in the memory cell array. The figure which shows the example of a setting of the threshold value distribution of a memory cell transistor. The figure which shows the operation | movement principle in the case of performing reading of a memory cell transistor. The conceptual diagram explaining the overwriting phenomenon. The conceptual diagram explaining the reading defect. The figure which shows the circuit structure of the CG driver which concerns on a comparative example. The logic circuit figure which concerns on the comparative example for controlling the gate voltage of a transfer switch. The wave form diagram which shows the level of each signal at the time of reading. The figure which shows the voltage relationship of each word line in the case of implementing the overwriting state analysis method which concerns on a comparative example. The figure which shows the example of a setting of the threshold value distribution of a memory cell transistor. The figure which shows the circuit structure of the CG driver which concerns on a present Example. The logic circuit figure concerning the Example for controlling the gate voltage of a transfer switch. The figure which shows the voltage relationship of each word line in the case of implementing the 1st overwriting state analysis method. The wave form diagram which shows the level of each signal in the case of implementing the 1st overwriting state analysis method. The flowchart which shows the 1st overwriting state analysis method. The figure which shows the voltage relationship of each word line in the case of implementing the 2nd overwriting state analysis method. The wave form diagram which shows the level of each signal in the case of implementing the 2nd overwriting state analysis method. The flowchart which shows the 2nd overwriting state analysis method.

  Embodiments of the present invention will be described below with reference to the drawings. As a nonvolatile semiconductor memory device according to this embodiment, for example, a NAND flash memory will be described.

  FIG. 1 is a block diagram showing a functional configuration of the NAND flash memory 100. The NAND flash memory 100 includes an input / output control circuit 10, an operation logic control circuit 11, a ready / busy control circuit 12, a status register 13, an address register 14, a command register 15, a high voltage generation circuit 16, a row address buffer 17, a row It includes an address decoder 18, a column address buffer 19, a column address decoder 20, a data register 21, a sense amplifier 22, a memory cell array 23, a control circuit 24, and a ROM fuse 25.

  The input / output control circuit 10 controls transfer of commands and addresses input via the eight input / output terminals I / O1 to I / O8. The input / output control circuit 10 controls data input / output via the eight input / output terminals I / O1 to I / O8. The input command is, for example, a write command, a read command, an erase command, a status read command, or the like.

  The operation logic control circuit 11 includes various control signals input from the outside, such as a chip enable signal / CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, a read enable signal / RE, and a write protect. In response to the signal / WP, the input / output control circuit 10 and the control circuit 24 are controlled based on the combination of these signals.

  The ready / busy control circuit 12 outputs a ready / busy signal from the ready / busy terminal based on the operation state of the control circuit 24 (operation states such as writing, reading, and erasing). For example, during the period in which the NAND flash memory 100 performs internal operations such as writing, reading, and erasing, the signal level of the ready / busy terminal is “low”, and when the internal operation ends, the signal of the ready / busy terminal The level is “high”.

  The status register 13 is controlled by the control circuit 24, and as a result of the NAND flash memory 100 performing internal operations such as writing, reading, and erasing, the internal operations have been completed normally (Pass) or have been completed normally. Information corresponding to whether or not (Fail) has been taken in is fetched and temporarily stored.

  The address register 14 temporarily holds an address input via the input / output control circuit 10 and transfers a row address to the row address buffer 17 and a column address to the column address buffer 19.

  The command register 15 temporarily holds commands (write command, read command, erase command, status read command, etc.) input via the input / output control circuit 10 and transfers them to the control circuit 24.

  The high voltage generation circuit 16 generates a high voltage necessary for each operation such as writing, reading, and erasing based on the state of the control circuit 24 and transfers the high voltage to the row address decoder 18, the sense amplifier 22, and the memory cell array 23. .

  The row address buffer 17 temporarily holds a row address input via the address register 14 and transfers it to the row address decoder 18.

  The row address decoder 18 controls the word line based on the row address input via the row address buffer 17 and selectively applies a voltage to the word line in the write and read operations.

  The column address buffer 19 temporarily holds a column address input via the address register 14 and transfers it to the column address decoder 20.

  The column address decoder 20 controls the bit line based on the column address input through the column address buffer 19 and selectively applies a voltage to the bit line in the write and read operations.

  The data register 21 temporarily holds a certain amount of write data input via the input / output control circuit 10 or a certain amount of read data determined by the sense amplifier 22.

  The sense amplifier 22 determines and amplifies data read from the memory cell array 23. The sense amplifier 22 has, for example, a sense amplifier circuit corresponding to each bit line.

  The memory cell array 23 is composed of a plurality of blocks, and has a structure in which a plurality of memory cell transistors (hereinafter referred to as memory cells) are arranged in a matrix. Each block is a minimum unit of data erasure. The memory cell holds binary data or multi-value data depending on, for example, a difference in threshold voltage of transistors that is determined according to the amount of charge stored in the floating gate. The memory cell may have a MONOS structure that traps charges in a nitride film as a charge storage layer.

  FIG. 2 shows a configuration example of one block in the memory cell array 23. Each block includes (p + 1) NAND strings arranged in order along the X direction (p is an integer of 0 or more). The selection transistors ST1 included in each of the (p + 1) NAND strings have drains connected to the bit lines BL0 to BLp and gates commonly connected to the selection gate line SGD. The selection transistor ST2 has a source commonly connected to the source line SL and a gate commonly connected to the selection gate line SGS.

  Each memory cell MT is composed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a semiconductor substrate. The stacked gate structure includes a charge storage layer (floating gate) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the charge storage layer with an inter-gate insulating film interposed therebetween. . In the memory cell MT, the threshold voltage changes according to the number of electrons stored in the floating gate electrode, and data is stored according to the difference in the threshold voltage.

  In each NAND string, (q + 1) memory cells MT are arranged such that respective current paths are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. That is, the plurality of memory cells MT are connected in series in the Y direction such that adjacent memory cells share a diffusion region (source region or drain region).

  In order from the memory cell MT located closest to the drain, the control gate electrodes are connected to the word lines WL0 to WLq, respectively. Therefore, the drain of the memory cell transistor MT connected to the word line WL0 is connected to the source of the selection transistor ST1, and the source of the memory cell MT connected to the word line WLq is connected to the drain of the selection transistor ST2.

  The word lines WL0 to WLq connect the control gate electrodes of the memory cells MT in common between the NAND strings in the block. That is, the control gate electrodes of the memory cells MT in the same row in the block are connected to the same word line WL. The (p + 1) memory cells MT connected to the same word line WL are handled as a page, and reading / writing is performed for each page.

  The bit lines BL0 to BLp connect the drains of the selection transistors ST1 in common between the blocks. That is, NAND strings in the same column within a plurality of blocks are connected to the same bit line BL.

  FIG. 3 shows an example of setting the threshold distribution of memory cells capable of storing binary data. The data written to the memory cell MT defines whether the threshold voltage is a value smaller than 0V or larger than 0V, corresponding to data “1” and “0”, respectively. “1” data corresponds to an erased memory cell at the initial level. The “0” data is set by injecting electrons into the floating gate of the memory cell at the address corresponding to the “0” data based on the externally input write command, write address, and write data. It is done by raising.

  Here, at the time of data reading, the selected word line voltage VSEL applied to the selected word line specified by the read command and the read address input from the outside is, for example, 0 V, and the non-selected word lines other than the selected word line The unselected word line voltage VUSEL applied to is set to 5V, for example. The threshold definition of “0” data has an upper limit, and writing must be performed so as not to exceed the non-selection voltage VUSEL.

  FIG. 4 shows the voltage setting at the time of data reading for one NAND string. The voltage SRC applied to the source line SL is fixed at 0V, for example. The selection transistors ST1 and ST2 function as switches that open and close the current path of the NAND string selected by the external input address. The voltage VSG applied to the selection gate lines SGD, SGS of the selected NAND string is, for example, about 3V. Each of the memory cells MT0 to MT3 stores information by being set within either “1” or “0” of the threshold definition in FIG.

  The word lines WL0 to WL3 connected to the control gates of the memory cells MT0 to MT3 are driven by a control gate driving circuit (CG driver) corresponding to each word line, which is common in the memory cell array 23. The CG driver is included in the row address decoder 18, for example. The voltages applied to the word lines WL0 to WL3 by the CG driver are denoted as CG0 to CG3, respectively. The CG driver applies VSEL (0 V) when it corresponds to the selected word line, and applies VUSEL (5 V) when it corresponds to the non-selected word line.

  Here, FIG. 4 shows an operation principle when the memory cell MT2 is selected and read. Since all the threshold voltages of the memory cells MT0 to MT3 are less than the unselected word line voltage VUSEL (5V), the memory cells MT0, MT1, and MT3 are turned on. On the other hand, the memory cell MT2 is turned on when the threshold voltage is smaller than the selected word line voltage VSEL (0 V), and turned off when larger than VSEL (0 V), and the cell current flowing through the NAND string with only the threshold voltage of the memory cell MT2 Icell is determined. Reading is performed by determining the cell current Icell with the sense amplifier 22 connected to each bit line. For example, the sense amplifier 22 determines “0” data when Icell≈0, and “1” data when Icell> 0.

  FIG. 5 illustrates an overwriting phenomenon that occurs in writing to a memory cell. Here, a state is shown in which the threshold value of the memory cell MT1 exceeds VUSEL (5V) and becomes 6V. As described above, a state where there is a memory cell having a threshold voltage exceeding the unselected word line voltage VUSEL at the time of reading is defined as an overwriting state. Normally, various conditions (unselected word line voltage during reading, word line voltage during writing, pulse width setting, word line voltage step-up width, etc.) are used to prevent such memory cells from being generated. The optimum conditions are set together with viewpoints such as power consumption, reliability, and chip area. However, electrons are injected little by little into memory cells in the memory cell array 23 having billions or more due to weak writing at the time of writing including singular cells that are fast written or reading of other memory cells and also including themselves. May be overwritten.

  FIG. 6 illustrates a read defect when the memory cell MT1 exceeds the unselected word line voltage VUSEL (5V), which is the upper limit of the threshold definition of “0” data, and becomes 6V as shown in FIG. To do. In this case, the memory cell MT1 is always turned off regardless of which of the memory cells MT0 to MT3 is read, so that the cell current Icell≈0, and the read result is always “0”. Accordingly, when the memory cells MT0, MT2, and MT3 hold “1” data, a read failure occurs.

  FIG. 7 shows a configuration of a circuit called a CG driver for generating a voltage to be applied to one word line in the comparative example. The high voltage generation circuit 16 includes, for example, three types of power sources shown in FIG. 7, that is, a selection power source (VCGRV) 30, a non-selection power source (VREAD) 31, and a reset power source (VRST) 32. In FIG. 7, only the CG driver corresponding to one word line is shown, but the power source is common to a plurality of CG drivers. In the power supply configuration according to the comparative example, only one non-selection power supply is prepared.

  The selection power source 30 is a selected word line driving power source, and has a variable width of, for example, 0 V when performing binary storage, and, for example, about 0 to 4 V when performing multi-value storage. The threshold voltage of the memory cell has a temperature characteristic, and it is a complicated power supply circuit to correct the temperature characteristic and to correct a slight deviation of the threshold distribution depending on the word line. The voltage variable width is narrower than that of the non-selected word line driving power supply, but the step interval is fine. For example, the voltage of the selection power source 30 can be set in increments of 50 mV. In this comparative example, the selection power supply 30 generates, for example, 0 V as the selected word line voltage VSEL.

  On the other hand, the power supply 31 for non-selection is a power supply for driving a non-selected word line, and has a variable width of, for example, 3 to 8 V when performing binary storage, and 3 to 10 V, for example, when performing multi-value storage. The non-selection power supply 31 is a power supply circuit that can output a voltage higher than that of the selection power supply 30, but the voltage accuracy is not as high as that of the selection power supply 30, so that the step interval is coarse. There is a feature. For example, the non-selection power supply 31 can be set in steps of 200 mV. In this comparative example, the non-selection power source 31 generates, for example, 5 V as the non-select word line voltage VUSEL.

  The reset power source 32 is a power source for resetting the word line voltage to the ground potential VSS. The control circuit 24 determines the voltage CGn applied to the word line WLn by controlling the gate signal G_VSEL, the gate signal G_VUSEL, and the gate signal G_VSS applied to the gates of the transfer switches S1, S2, and S3, respectively. The transfer switches S1, S2, and S3 are included in, for example, a CG driver.

  FIG. 8 is a logic circuit according to a comparative example for controlling the gate signals G_VSEL, G_VUSEL, and G_VSS of the transfer switches S1, S2, and S3 included in the row address decoder 18, for example, and is provided for each CG driver. . The logic circuit according to the comparative example includes NAND circuits 200-1, 200-2, 200-3, NOT circuits 300-1, 300-2, 300-3, 300-4, level shifter (L / S) 400-1, 400-2 and an OR circuit 500-1. Row address signals A0 and A1 are input to the NAND circuit 200-1.

  Here, the row address signals A0 and A1 are input in combination to each of the CG drivers. That is, / A0 and / A1 are provided for the CG driver provided for WL0, A0 and / A1 are provided for the CG driver provided for WL1, and / A0 and A1 are provided for the CG driver provided for WL2. In the CG driver provided for WL3, A0 and A1 are respectively input to the first input terminal and the second input terminal of the NAND circuit 200-1, and correspond to the row address input from the outside. Only in this case, the output of the NAND circuit 200-1 becomes "L".

  The activation signal ACT_VSEL is input to the first input terminal of the NAND circuit 200-2, and the output signal of the NAND circuit 200-1 is input to the second input terminal via the NOT circuit 300-1. An output signal of the NAND circuit 200-1 is input to the first input terminal of the NAND circuit 200-3, and an activation signal ACT_VUSEL is input to the second input terminal. The activation signal ACT_VUSEL is input to the first input terminal of the OR circuit 500-1, and the activation signal ACT_VSEL is input to the second input terminal.

  The activation signals ACT_VSEL and ACT_VUSEL are common to a plurality of CG drivers, and are signals for activating the gate voltages G_VSEL and G_VUSEL, respectively, and are input from the control circuit 24, for example. The NOT circuit 300-4 inverts the output signal of the OR circuit 500-1 and outputs a gate signal G_VSS. When the activation signals ACT_VSEL and ACT_VUSEL are both “L”, the gate signal G_VSS = “H”, the transfer switch S3 is turned on, and the CG driver supplies the ground potential VSS supplied from the reset power supply 32 to the voltage CGn. And reset the word line WLn.

  The output signal of the NAND circuit 200-2 is input to the level shifter 400-1 via the NOT circuit 300-2. The level shifter 400-1 outputs a gate signal G_VSEL. The output signal of the NAND circuit 200-3 is input to the level shifter 400-2 via the NOT circuit 300-3. The level shifter 400-2 outputs a gate signal G_VUSEL. The level shifters 400-1 and 400-2 are circuits for setting the gate voltages of the transfer switches S1 and S2 to a high voltage that can sufficiently transfer the selected word line voltage VSEL or the unselected word line voltage VUSEL.

  FIG. 9 is a waveform diagram showing the level of each signal at the time of reading. Here, the word line WL1 is selected and the word lines WL0, WL2, and WL3 are not selected. In order to activate the CG driver of the word line WL1, row address signals A0 = “H” and A1 = “L” are input. Since the activation signal ACT_VSEL = “H” and the activation signal ACT_VUSEL = “H”, the CG driver corresponding to the word line WL1 outputs the selection voltage VSEL (0V) and corresponds to the word lines WL0, WL2, WL3. The CG driver outputs a non-selection voltage VUSEL (5V). The selection voltage VSEL is applied only to the selected word line WL1 selected by the row address, and the non-selection voltage VUSEL is applied to the other word lines WL0, WL2, WL3, so that the memory connected to the word line WL1. It is possible to read data held in the cell MT1.

  FIG. 10 shows an analysis method according to a comparative example when detecting an overwritten memory cell. According to the analysis method according to the comparative example, the maximum threshold value of the memory cells MT0 to MT3 can be checked by simultaneously boosting all the word lines as the unselected word line voltage VUSEL. However, the analysis method according to the comparative example cannot check which memory cell has the maximum threshold value. This is because as the unselected word line voltage VUSEL is raised, all the memory cells are turned on at a certain voltage and the cell current Icell> 0, but it is impossible to detect which memory cell is turned on last. In the logic circuit according to the comparative example shown in FIG. 8, the selected word line voltage VSEL is applied to the word line selected by the row address, and the unselected word line voltage VUSEL is applied to the other word lines. As shown in FIG. 10, it is difficult to apply the unselected word line voltage VUSEL to all the word lines.

  Hereinafter, a power supply configuration and an analysis method according to the present embodiment for specifying a memory cell in an overwritten state will be specifically described with reference to the drawings.

  FIG. 11 shows an example of setting the threshold distribution of memory cells capable of storing binary data. Here, the selected word line voltage VSEL applied to the selected word line at the time of data reading is 0 V, for example, and the first unselected word line voltage VUSEL applied to the unselected word line at the time of data reading is, for example, Set to 5V. Further, in this embodiment, in order to specify the overwritten memory cell, in addition to the first unselected word line voltage VUSEL, the second unselected word line voltage VUSELH is set to 7V, for example. . The second unselected word line voltage VUSELH sets a voltage having a margin with respect to the worst overwritten cell threshold that can be assumed.

  FIG. 12 shows a configuration of a circuit called a CG driver for generating a voltage to be applied to one word line in the present embodiment. The high voltage generation circuit 16 has, for example, three types of power supplies, that is, a selection power supply (VCGRV) 40, a non-selection power supply (VREAD) 42, and a reset power supply, similarly to the circuit configuration according to the comparative example shown in FIG. A power supply (VRST) 43 is included. The selection power source 40, the non-selection power source 42, and the reset power source 43 are the same as the selection power source 30, the non-selection power source 31, and the reset power source 32 in the comparative example. However, in FIG. 12, a non-selection power supply (VREADK) 41, which is the same power supply circuit as the non-selection power supply (VREAD) 42, is newly provided so that the word line can be driven with this voltage.

  The control circuit 24 controls the gate signal G_VSEL, the gate signal G_VUSELH, the gate signal G_VUSEL, and the gate signal G_VSS that are applied to the gates of the transfer switches S10, S20, S30, and S40, respectively, thereby applying the voltage CGn applied to the word line WLn. decide. The transfer switches S10, S20, S30, and S40 are included in the CG driver, for example.

  FIG. 13 shows a logic circuit according to this embodiment for controlling the gate signals G_VSEL, G_VUSEL, G_VUSELH, G_VSS of the transfer switch included in the row address decoder 18, for example, and is provided for each CG driver. In this embodiment, the gate signal G_VSELH and the activation signal ACT_VUSELH are added to the comparative example, and when all of the activation signals ACT_VSEL, ACT_VUSELH, and ACT_VUSEL are “L”, the gate signal G_VSS = “H”. The CG driver resets the word line to the ground potential VSS.

  The logic circuit according to this embodiment includes NAND circuits 600-1, 600-2, 600-3, 600-4, NOT circuits 700-1, 700-2, 700-3, 700-4, 700-5, and a level shifter. (L / S) 800-1, 800-2, 800-3, and OR circuit 900-1. Row address signals A0 and A1 are input to the NAND circuit 600-1. The row address signals A0 and A1 are input in combination to each of the CG drivers, as in the comparative example.

  The activation signal ACT_VSEL is input to the first input terminal of the NAND circuit 600-2, and the output signal of the NAND circuit 600-1 is input to the second input terminal via the NOT circuit 700-1. The output signal of the NAND circuit 600-1 is input to the first input terminal of the NAND circuit 600-3 via the NOT circuit 700-1, and the activation signal ACT_VUSELH is input to the second input terminal. The output signal of the NAND circuit 600-1 is input to the first input terminal of the NAND circuit 600-4, and the activation signal ACT_VUSEL is input to the second input terminal. The activation signal ACT_VUSEL is input to the first input terminal of the OR circuit 900-1, the activation signal ACT_VUSEL is input to the second input terminal, and the activation signal ACT_VSEL is input to the third input terminal. .

  The activation signals ACT_VSEL, ACT_VUSEL, and ACT_VUSELH are common to a plurality of CG drivers, and are signals that activate the gate voltages G_VSEL, G_VUSEL, and G_VUSELH, and are input from the control circuit 24, for example. The NOT circuit 700-5 inverts the output signal of the OR circuit 900-1 and outputs a gate signal G_VSS. When the activation signals ACT_VSEL, ACT_VUSEL, and ACT_VUSEL are all “L”, the gate signal G_VSS = “H” and the transfer switch S40 is turned on. The CG driver transfers the ground potential VSS supplied from the reset power supply 43 as CGn, and resets the word line WLn.

  The output signal of the NAND circuit 600-2 is input to the level shifter 800-1 via the NOT circuit 700-2. The level shifter 800-1 outputs a gate signal G_VSEL. The output signal of the NAND circuit 600-3 is input to the level shifter 800-2 via the NOT circuit 700-3. The level shifter 800-2 outputs a gate signal G_VUSELH. The output signal of the NAND circuit 600-4 is input to the level shifter 800-3 via the NOT circuit 700-4. The level shifter 800-3 outputs a gate signal G_VUSEL. The level shifters 800-1, 800-2, and 800-3 use the gate voltages of the transfer switches S10, S20, and S30 as the selected word line voltage VSEL, the first unselected word line voltage VUSEL, or the second unselected word line. This is a circuit for setting the voltage VUSELH to a high voltage that can be sufficiently transferred.

  According to the logic circuit, by controlling the activation signals ACT_VSEL, ACT_VUSEL, and ACT_VUSELH, the second unselected word line voltage VUSEH is applied to the word line selected by the row address, and the other word lines are applied. Thus, the CG driver can be controlled to apply the first unselected word line voltage VUSEL.

(First overwriting state analysis method)
14 to 16 are for explaining a first overwriting state analyzing method according to the present embodiment.

  FIG. 14 shows the voltage relationship of each word line when the first overwriting state analysis method is carried out. In the first overwrite state analysis method, for example, in order to identify a memory cell in an overwrite state, for example, a word line (inspection target word line) WL0 connected to a memory cell (inspection target memory cell) MT0 of interest as an analysis target 7V is applied as the second unselected word line voltage VUSELH, and 5V is applied as the first unselected word line voltage VUSEL to the other word lines WL1, WL2 and WL3.

  Further, the memory cell to be inspected is changed from MT0 to MT1, MT2, and MT3 in this order, that is, the inspection target word line to which the second unselected word line voltage VUSELH is applied is changed from WL0 to WL1, WL2, and WL3 in this order. In this way, by changing the word line to which the second unselected word line voltage VUSELH is applied and applying the first unselected word line voltage VUSEL to the other word lines, the cell current becomes Icell≈ It can be known that the memory cell connected to the inspection target word line selected when 0 changes to Icell> 0 is in the overwrite state.

  FIG. 15 is a waveform diagram showing the level of each signal when the first overwriting state analysis method is performed. In this case, since the word line WL0 is an inspection target, A0 = “L” and A1 = “L” are input as row addresses. Further, the selection voltage VSEL = 3V, the first unselected word line voltage VUSEL = 5V, and the second unselected word line voltage VUSELH = 7V are set. Since the selection voltage VSEL is not used, the activation signal ACT_VSEL = “L”. Since the power supply 40 for selection is not used, the voltage to be generated is arbitrary, but is 3 V, for example.

  Since the activation signal ACT_VUSEL = “H” and the activation signal ACT_VUSEL = “H”, the inspection target word line WL0 selected by the row address is supplied from the non-selection power supply 41 as the second non-selection voltage VUSEL. 7V is applied, and 5V is applied to the other word lines WL1, WL2, WL3 from the non-selection power supply 42 as the first non-selection power supply VUSEL.

  FIG. 16 is a flowchart showing the first overwriting state analysis method. Each step shown in FIG. 16 may be performed by inputting a test command and an address from an external tester connected to the NAND flash memory 100, or a BIST (not shown) provided in the NAND flash memory 100. The built-in self test) circuit may be implemented by the control circuit 24. Here, it is assumed that the control circuit 24 performs the first overwriting state analysis method.

  The control circuit 24 initializes the number n of the memory cell to be inspected to n = 0. (Step S100).

  The control circuit 24 sets the inspection target memory cell to MTn. (Step S101).

  The control circuit 24 controls the CG driver, applies the second unselected word line voltage VUSELH to the test target memory cell MTn, and applies the first unselected word line voltage VUSEL to the other memory cells (step). S102).

  The control circuit 24 determines whether or not the cell current Icell flowing through the bit line BL is greater than 0 by the sense amplifier 22 (step S103).

  When it is determined in step S103 that the cell current Icell> 0, the control circuit 24 specifies that the currently selected memory cell MTn to be inspected is an overwritten memory cell, and ends the analysis (step S104). ).

  On the other hand, if it is determined in step S103 that the cell current Icell> 0 is not satisfied, the control circuit 24 determines whether or not the test target memory cell MTn is the last memory cell MTq in the NAND string, that is, n = q. It is determined whether or not there is (step S105).

  If it is determined in step S105 that it is not the last memory cell, the control circuit 24 sets n = n + 1 and changes the memory cell to be inspected to the next memory cell (step S106).

  On the other hand, if it is determined in step S105 that it is the last memory cell, the control circuit 24 determines that an overwritten memory cell cannot be specified in the NAND string, and ends the analysis. In this case, although not shown, the same steps may be retried by setting the first unselected word line voltage VUSEL and the second unselected word line voltage VUSEL to higher voltages.

  As described above, according to the first overwriting state analysis method, a plurality of power supplies for generating a voltage to be applied to the non-selected word lines are provided, so that an overwritten state memory cell transistor can be easily formed. It is possible to specify.

(Second overwriting state analysis method)
FIGS. 17 to 19 are for explaining a second overwriting state analyzing method according to the present embodiment. The first overwriting measurement method can be applied only when the number of overwritten memory cells is one in the NAND string, but the second overwriting state analysis method has no such limitation. It is characterized by that.

  FIG. 17 shows the voltage relationship of each word line when the second overwrite state analysis method is performed. The second overwrite state analysis method is an improvement of the first overwrite state analysis method. For example, a word line (inspection target word) connected to a memory cell (inspection target memory cell) MT0 of interest as an analysis target. Line) The voltage of WL0 is gradually raised as the second unselected word line voltage VUSELH, and 7V is applied as the first unselected word line voltage VUSEL to the other word lines WL1, WL2, WL3.

  Here, when the second overwriting state analysis method is performed, the first unselected word line voltage VUSEL is set to a voltage having a margin with respect to the worst possible overwriting cell threshold. . In this way, by setting the voltage applied to the word lines other than the inspection target word line high, even if there are a plurality of overwritten memory cells, if the threshold is equal to or lower than the first unselected word line voltage VUSEL. The first unselected word line voltage VUSEL can be raised as required.

  FIG. 18 is a waveform diagram showing the level of each signal when the second overwriting state analysis method is performed. In this case, since the word line WL0 is an inspection target, A0 = “L” and A1 = “L” are input as row addresses. Further, the selection voltage VSEL = 3V, the first unselected word line voltage VUSEL = 7V, and the second unselected word line voltage VUSEL = 7V are set. Since the selection voltage VSEL is not used, the activation signal ACT_VSEL = “L”. Since the power supply 40 for selection is not used, the voltage to be generated is arbitrary, but is 3 V, for example.

  Since the activation signal ACT_VUSEL = “H” and the activation signal ACT_VUSEL = “H”, the second non-selection voltage VUSEH is supplied from the non-selection power supply 41 to the inspection target word line WL0 selected by the row address. 7 V is applied to the other word lines WL1, WL2, WL3 from the non-selection power supply 42 as the first non-selection power supply VUSEL. The non-selection power supply 41 can generate a voltage of about 3 to 8 V, for example. Therefore, the control circuit 24 sets the second non-selection voltage VUSELH to 0 to 7 V, for example, within this setting range. Increase the pressure at every variable interval.

  FIG. 19 is a flowchart showing the second overwriting state analysis method.

  The control circuit 24 initializes the number n of the memory cell to be inspected to n = 0. (Step S200).

  The control circuit 24 sets the inspection target memory cell to MTn. (Step S201).

  The control circuit 24 controls the CG driver, applies the second unselected word line voltage VUSELH to the test target memory cell MTn, and raises it from 0V to 7V. 7 V is applied as the first unselected word line voltage VUSEL to the other memory cells (step S202).

  The control circuit 24 detects the cell current Icell> 0 flowing through the bit line BL by the sense amplifier 22. (Step S203).

  When the control circuit 24 detects that the cell current Icell> 0 in step S203, the control circuit 24 stores the threshold value of the memory cell MTn that is currently selected in the predetermined storage area as the set value of VUSEL at that time. Alternatively, the threshold value of the inspection target memory cell MTn is output to the external tester (step S204).

  When the cell current Icell> 0 is not satisfied in step S203, or when the threshold value registration of the memory cell MTn is completed in step S204, the control circuit 24 determines that the memory cell MTn to be inspected is the last memory cell MTq in the NAND string. Whether or not n = q is determined (step S205).

  If it is determined in step S205 that it is not the last memory cell, the control circuit 24 sets n = n + 1 and changes the memory cell to be inspected to the next memory cell (step S206). On the other hand, if it is determined in step S205 that it is the last memory cell, the control circuit 24 ends the analysis.

  As described above, according to the second overwriting state analysis method, by providing a plurality of power supplies for generating a voltage to be applied to the non-selected word line, each memory cell is brought into an overwriting state. Regardless, since the threshold value of each memory cell transistor can be measured, it is possible to easily identify an overwritten memory cell transistor. Further, even when there are two or more overwritten memory cells in the NAND string, the identification can be made.

  In this embodiment, a power supply for generating a voltage to be applied to unselected word lines is newly provided. However, a plurality of power supplies for unselected word lines are provided in advance in the NAND flash memory. If so, you may use this. In this case, it is possible to implement the first and second overwriting state analysis methods according to the present embodiment by modifying the logic circuit for controlling the gate signal of the transfer switch included in the CG driver.

  Although the invention of the present application has been described above, the invention of the present application is not limited to the above-described embodiments, and may be appropriately combined with modifications, and various modifications may be made without departing from the scope of the invention at the implementation stage. Is possible. Further, the present embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the present embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

DESCRIPTION OF SYMBOLS 100 NAND type flash memory 10 Input / output control circuit 11 Operation logic control circuit 12 Ready / busy control circuit 13 Status register 14 Address register 15 Command register 16 High voltage generation circuit 17 Row address buffer 18 Row address decoder 19 Column address buffer 20 Column address Decoder 21 Data register 22 Sense amplifier 23 Memory cell array 24 Control circuit WL Word line BL Bit line SGS, SGD Selection gate line SL Source line 30, 40 Selection power supply 31, 41, 42 Non-selection power supply 32, 43 Reset power supply S1 , S2, S3, S10, S20, S30, S40 Transfer switch 200-1, 2, 3, 600-1, 2, 3, 4 NAND circuit 300-1, 2, 3, 4 700-1,2,3,4,5 NOT circuit 400-1,2,800-1,2,3 level shifter 500-1,900-1 OR circuit

Claims (7)

A plurality of memory cell transistors connected in series with a common source and drain; and
A plurality of word lines connected to a control gate of the memory cell transistor;
A first non-selection power supply for generating a first non-selection word line voltage applied to the non-selection word line during a read operation;
A second non-selection power supply capable of generating a second non-selection word line voltage equal to or higher than the first non-selection word line voltage;
A control circuit for applying the second unselected word line voltage to one of the plurality of word lines and applying the first unselected word line voltage to the other word lines;
A non-volatile semiconductor memory device comprising: A power supply for a selected word line that generates a selected word line voltage applied to the selected word line during a read operation;
2. The nonvolatile semiconductor memory device according to claim 1, wherein the first and second unselected word line power supplies can generate a higher voltage than the selected word line power supply. 3.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the first unselected word line power source and the second unselected word line power source have substantially the same configuration. A plurality of memory cell transistors connected in series sharing a source and a drain, a plurality of word lines connected to the control gate of the memory cell transistor, and a first non-selected word line applied to a non-selected word line during a read operation A first non-selection power source for generating a selected word line voltage; and a second non-selection power source capable of generating a second non-selection word line voltage equal to or higher than the first non-selection word line voltage; A test method for a nonvolatile semiconductor memory device comprising:
Applying the second unselected word line voltage to a word line connected to a memory cell to be tested, and applying the first unselected word line voltage to word lines connected to other memory cells; ,
Determining whether a threshold value of the memory cell transistor to be inspected is a predetermined value or more;
When the threshold value of the memory cell transistor to be inspected is determined to be a predetermined value or more, determining the memory cell to be inspected as being overwritten;
A test method for a nonvolatile semiconductor memory device, comprising:   5. The test method for a nonvolatile semiconductor memory device according to claim 4, wherein the second unselected word line voltage is higher than the first unselected word line voltage. A plurality of memory cell transistors connected in series sharing a source and a drain, a plurality of word lines connected to the control gate of the memory cell transistor, and a first non-selected word line applied to a non-selected word line during a read operation A first non-selection power source for generating a selected word line voltage; and a second non-selection power source capable of generating a second non-selection word line voltage equal to or higher than the first non-selection word line voltage; A test method for a nonvolatile semiconductor memory device comprising:
The second non-selected word line voltage is applied to the word line connected to the memory cell to be inspected, the second non-selected word line voltage is raised, and the word line connected to the other memory cells Applying the first unselected word line voltage;
Measuring a threshold value of the memory cell transistor to be inspected;
A test method for a nonvolatile semiconductor memory device, comprising:   7. The nonvolatile semiconductor memory device according to claim 6, wherein the second unselected word line voltage is increased from 0 V to a voltage at least equal to a set value of the first unselected word line voltage. Test method.

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