JP2011211274A - Image display apparatus, projector, and data acquiring method in the image display apparatus - Google Patents

Abstract

An object of the present invention is to improve the efficiency of distortion correction processing in an image display device.
An image display device includes a frame video storage unit, a block video storage unit that includes a plurality of block areas and stores block video data, and a correction processing unit that generates post-correction pixel data using the block video data. A display unit that displays the corrected frame image, a determination unit that issues an acquisition request for acquiring the block image data used to generate the first corrected pixel data, and the generation after the first corrected pixel data When the acquisition request is issued by the block video prediction unit that issues an acquisition request for acquiring the block video data used to generate the second corrected pixel data, and issued by the block video prediction unit A block video acquisition unit that acquires block video data designated in preference to the acquisition request.
[Selection] Figure 5

Description

  The present invention relates to an image display device, a projector, and a data acquisition method in the image display device.

  In an image display device such as a projector, when an image is displayed on a display surface such as a screen, the image displayed on the display surface may be distorted due to, for example, the relative positional relationship between the projector and the display surface. In order to solve this problem, trapezoidal distortion correction is known in which an image distorted in a trapezoidal shape is corrected to a rectangular shape by using a projective transformation technique.

JP 2007-150531 A

  However, there is still room for improvement in the efficiency of distortion correction processing in the image display apparatus.

  The present invention has been made to solve at least a part of the above-described problems, and an object thereof is to improve the efficiency of distortion correction processing in an image display apparatus.

  A first aspect of the present invention provides an image display device. An image display apparatus according to a first aspect of the present invention includes a frame video storage unit that stores video data representing a frame video, and a plurality of block areas for storing block video data including a predetermined number of pixels, Using the block video storage unit that stores a part of the video data stored in the frame video storage unit as block video data in each block area, and the block video data stored in each block area, the frame video A correction processing unit that generates a plurality of corrected pixel data respectively representing a plurality of pixels constituting a corrected frame image that has been subjected to distortion correction, and the corrected pixel data generated by the correction processing unit A display unit for displaying the corrected frame image and the correction processing unit are included in the plurality of corrected pixel data; It is determined whether block video data necessary for generating one corrected pixel data is stored in the block area of the block video storage unit, and the block video data is stored in the block area of the block video storage unit. If not stored, the determination unit that issues an acquisition request for acquiring the block video data and the corrected pixel data that is generated after the first corrected pixel data by the correction processing unit Block image data necessary for generating the corrected pixel data of 2 is predicted, and when the predicted block image data is not stored in the block area of the block image storage unit, the predicted block data A block video prediction unit that issues an acquisition request for acquiring video data, and an acquisition request is issued by the block video prediction unit The block video data designated in each acquisition request is acquired from the video data stored in the frame video storage unit and stored in the block area of the block video storage unit in the issued order, and the determination unit When the acquisition request is issued by the block, the block video data specified by the acquisition request is acquired from the video data in preference to the block video data specified in the acquisition request issued by the block video prediction unit A video acquisition unit.

  According to the image display device according to the first aspect, the block video data specified by the acquisition request issued by the determination unit has priority over the block video data specified by the acquisition request issued by the block video prediction unit. Therefore, the distortion correction processing efficiency can be improved.

  In the image display device according to the first aspect, the block video acquisition unit is issued from the determination unit and a first buffer unit that stores acquisition requests issued from the block video prediction unit in the order of issue. When the acquisition request is stored in the second buffer unit, the second buffer unit that stores the acquisition request, and the acquisition request stored in the first buffer unit are read in the stored order, and the second buffer unit stores the acquisition request. A reading unit that reads out the acquisition request from the second buffer in preference to reading out the acquisition request from one buffer unit, and a block image specified in each acquisition request according to the order of reading out by the reading unit And an acquisition unit that acquires data. In this case, in order to read out the acquisition request issued from the determination unit in priority to reading out the acquisition request issued from the block video prediction unit, and to acquire the block video data specified in each acquisition request in the order of reading, The efficiency of distortion correction processing can be improved.

  In the image display device according to the first aspect, when the block video acquisition unit receives the acquisition request issued by the buffer unit that stores the acquisition request at each address of the storage area and the block video prediction unit, When the acquisition request received at the address read after the acquisition request stored in the buffer unit is stored and the acquisition request issued by the determination unit is received, the acquisition request stored in the buffer unit first Among them, the storage control unit that stores the received acquisition request at an address read before the acquisition request issued by the block video prediction unit, and the acquisition request are sequentially read from the buffer unit according to the address, and specified in each acquisition request An acquisition unit that acquires the block video data that has been recorded. In this case, the acquisition request issued by the block video prediction unit is read after the acquisition request previously stored in the buffer unit, and the acquisition request issued by the determination unit is acquired first by the buffer unit. Among the requests, reading is performed before the acquisition request issued by the block video prediction unit, and the block video data specified in each acquisition request is acquired in the order of reading, so that the efficiency of distortion correction processing can be improved. .

  A second aspect of the present invention provides a projector that projects and displays an image on a projection surface. A projector according to a second aspect of the present invention includes an image light output unit that generates and outputs image light representing the image, a frame image storage unit that stores image data representing a frame image, and a predetermined number of pixels. A plurality of block areas for storing block video data, and a block video storage unit for storing a part of the video data stored in the frame video storage unit in each block area as block video data, and each of the blocks A plurality of pixels constituting the corrected frame image obtained by performing processing for correcting the distortion of the image projected on the projection surface with respect to the frame image using the block image data stored in the area A plurality of post-correction pixel data respectively representing a correction processing unit that outputs the corrected pixel data to the image light output unit, and the correction processing unit includes the plurality of correction processing units. It is determined whether block video data necessary for generating the first corrected pixel data included in the corrected pixel data is stored in the block area of the block video storage unit, and the block video data is When not stored in the block area of the block video storage unit, a determination unit that issues an acquisition request for acquiring the block video data, and the correction processing unit are generated later by the first corrected pixel data When block video data necessary for generating second corrected pixel data that is corrected pixel data to be predicted is predicted, and the predicted block video data is not stored in the block area of the block video storage unit Includes a block video prediction unit that issues an acquisition request for acquiring the predicted block video data, and the block When the acquisition request is issued by the image prediction unit, the block video data specified in each acquisition request is acquired from the video data stored in the frame video storage unit in the issued order, and the block video storage unit When the acquisition request is issued by the determination unit, the block video data specified by the acquisition request has priority over the block video data specified in the acquisition request issued by the block video prediction unit. And a block video acquisition unit that acquires from the video data.

  According to the projector of the second aspect, the block video data specified by the acquisition request issued by the determination unit has priority over the block video data specified by the acquisition request issued by the block video prediction unit. Since the data is acquired from the data, it is possible to improve the efficiency of the processing for correcting the distortion of the image projected on the projection surface in the projector.

  Note that the present invention can be realized in various modes, and can be realized by, for example, a projector television, a monitor, a block video storage device, a projection conversion processing device, an image processing device, or the like. Further, a data acquisition method, an image processing method, and a computer program for realizing the functions of these methods or apparatuses, a recording medium on which the computer program is recorded, and data embodied in a carrier wave including the computer program It can be realized in the form of a signal or the like.

It is explanatory drawing which shows a trapezoid distortion correction | amendment notionally. It is explanatory drawing which shows notionally the production method of the image data after correction | amendment. It is a figure which shows notionally the method of pixel interpolation. 1 is a block diagram schematically showing a configuration of a projector as an embodiment of the present invention. 3 is a functional block diagram illustrating a configuration of a trapezoidal distortion correction unit 120. FIG. FIG. 6 is a process diagram schematically showing an operation flow of a trapezoidal distortion correction unit 120. It is explanatory drawing which shows the timing of each process when the trapezoid distortion correction part 120 calculates the pixel value of 1 pixel of the image | video after correction | amendment. 3 is a diagram schematically showing a relationship between a frame buffer 150 and a cache block storage unit 122. FIG. It is a figure which shows notionally the relationship between the cache block memory | storage part 122 and the tag information storage part 123 for cache blocks. It is a figure which shows the relationship between a cache block and an interpolation block. It is explanatory drawing for demonstrating the prefetch determination in the prefetch request issuing part. It is explanatory drawing for demonstrating the order in which the cache block stored in the cache block memory | storage part 122 is updated. It is explanatory drawing which shows the example of the hit determination using tag information. It is process drawing which shows the process of a hit determination process typically. It is process drawing which shows the process of a hit determination process typically. It is a functional block diagram which shows the structure of the cache block control part 121 in a 1st Example. It is explanatory drawing for demonstrating the read order of the prefetch request | requirement by the buffer read control part 138, and a miss hit request. It is explanatory drawing for demonstrating the reading position of the interpolation block in Fig.17 (a). It is explanatory drawing for demonstrating the reading position of the interpolation block in FIG.17 (b). It is explanatory drawing for demonstrating the reading position of the interpolation block in FIG.17 (c). It is explanatory drawing for demonstrating the reading position of the interpolation block in FIG.17 (d). It is explanatory drawing for demonstrating the reading order of the pixel value of each pixel which comprises the cache block by the cache block acquisition part 139. FIG. It is a functional block diagram which shows the structure of the cache block control part 121 in a 2nd Example. It is explanatory drawing for demonstrating the storage order of the prefetch request | requirement by the buffer state determination part 137, and a miss hit request.

Hereinafter, a projector which is one embodiment of the present invention will be described in the following order based on embodiments with reference to the drawings.
A. First embodiment:
A-1. Keystone correction:
A-2. Projector configuration:
A-3. Keystone distortion correction section:
A-4. Prefetch determination:
A-5. Hit judgment:
A-6. Cache block controller:
B. Second embodiment:
B-1. Cache block controller:
C. Variations:

A. First embodiment:
A-1. Keystone correction:
The projector 100 as one embodiment of the present invention projects image light representing an image and displays the image on a projection surface such as a screen SC. The projector 100 is a projector capable of correcting a trapezoidal distortion of a video displayed on the screen SC and displaying a rectangular video when a rectangular video is input. Here, the trapezoidal distortion means that an image displayed on the projection surface is distorted into a trapezoid, a parallelogram, other quadrilaterals, or the like due to the relative positional relationship between the projector and the projection surface. Prior to the description of the configuration of the projector 100, trapezoidal distortion correction in the projector 100 of the present embodiment will be briefly described.

  FIG. 1 is an explanatory diagram conceptually showing trapezoidal distortion correction. As shown in the figure, when the projector 100 is arranged with an inclination in the horizontal direction (left-right direction) and the vertical direction (up-down direction) with respect to the screen SC, it is displayed on the liquid crystal panel unit 192. The video (pre-correction video IG0) is rectangular, whereas the video PIG0 projected on the screen SC has a trapezoidal distortion in each of the horizontal and vertical directions. In FIG. 1, for convenience of explanation, the liquid crystal panel unit 192 included in the projector 100 is displayed outside the projector 100.

  The projector 100 uses a projective transformation technique to form an image (corrected image IG1) distorted in the opposite direction to the image projected on the screen SC on the liquid crystal panel unit 192, thereby forming the image on the screen SC. A rectangular image PIG1 is displayed (FIG. 1). Here, correction that is performed in order to make an image having trapezoidal distortion appear rectangular (the shape of an image that should be originally displayed) is referred to as “trapezoidal distortion correction”. The trapezoidal distortion correction in this embodiment corresponds to “distortion correction” in the claims.

  FIG. 2 is an explanatory diagram conceptually showing a method of creating corrected video data. FIG. 2A shows a pre-correction image IG0. FIG. 2B shows the corrected image IG1. The broken line in FIG. 2B shows the outer shape of the pre-correction image IG0. Since the pre-correction video IG0 has been subjected to video processing so as to be displayed on the full frame of the liquid crystal panel unit 192, the broken line in FIG. 2B indicates the frame of the liquid crystal panel unit 192.

  In this embodiment, the coordinates of the pre-correction video IG0 and the post-correction video IG1 refer to pixel coordinates when the pre-correction video IG0 and the post-correction video IG1 are displayed on the liquid crystal panel unit 192. Hereinafter, the pixel coordinates of the liquid crystal panel unit 192 when the corrected image IG1 is displayed are referred to as corrected coordinates. Of the pixel coordinates of the liquid crystal panel unit 192, the pixel coordinates of the area where the corrected image IG1 is not displayed are also referred to using the corrected coordinates. The coordinates obtained by converting the corrected coordinates to the coordinate positions (pixel coordinates of the liquid crystal panel) in the pre-correction video IG0 by reverse projection conversion are referred to as pre-correction coordinates.

  An outline of a method of creating corrected video data representing the corrected video IG1 will be described with reference to FIG. The projector 100 generates post-correction video data by obtaining pixel values (R, G, and B values) of all pixel coordinates constituting the post-correction video IG1 based on the pixel values of the pre-correction video IG0. To do. As an example, a method of obtaining the pixel value of the coordinate P1 (X, Y) surrounded by the middle square of the corrected image IG1 shown in FIG.

  First, the projector 100 converts the corrected coordinates P1 (X, Y) of the pixel whose pixel value is to be obtained into the uncorrected coordinates P0 (x, y). At this time, since the pre-correction video IG0 and the post-correction video IG1 do not have an integer multiple correspondence, the calculated pre-correction coordinates P0 (x, y) include decimals. Therefore, the projector 100 estimates the pixel value of the pre-correction coordinates P0 (x, y) using the pixel values of 16 coordinates in the vicinity of the corresponding pre-correction coordinates P0 (x, y). This estimation of the pixel value is also called pixel interpolation. Accordingly, the projector 100 reads out the pixel block near the pre-correction coordinate P0 (x, y) based on the converted pre-correction coordinate P0 (x, y) including the decimal point, and applies a filter coefficient to the read pixel block. Is used to perform pixel interpolation. Thereby, the projector 100 calculates the pixel value of the coordinate P1 (X, Y) of the corrected image IG1. That is, the projector 100 calculates the pixel values of all the pixels (coordinates) constituting the corrected image IG1 by performing the pixel interpolation for each pixel, and the corrected image data representing the corrected image IG1. Is generated.

  FIG. 3 is a diagram conceptually illustrating a pixel interpolation method. FIG. 3 illustrates a method of obtaining a pixel value corresponding to the pre-correction coordinate P0 (x, y) obtained by converting the post-correction coordinate P1 (X, Y) by pixel interpolation. In the figure, the position of the pre-correction coordinates P0 (x, y) is indicated by hatched circles, and the positions of the surrounding 16 coordinates are indicated by white circles. Since the pixel value corresponding to the pre-correction coordinate P0 (x, y) is obtained by pixel interpolation, the pixel value corresponding to the pre-correction coordinate P0 (x, y) is set to “interpolated pixel” and the pre-correction coordinate P0 (x, y). ) The pixel values of the surrounding 16 pixels are pre-correction video data and are known, so they are also referred to as “known pixels”.

  In FIG. 3, pixel values of 16 pixels that are known pixels are represented by DATA [m] [n] (m = 0, 1, 2, 3 (x direction); n = 0, 1, 2, 3 (y direction). ). The interpolation pixel is obtained by a convolution operation of the pixel value of 16 pixels and the filter coefficient. The filter coefficient takes into account the influence of the distance between the interpolation pixel and the known pixel (for example, the distance between the known pixel of DATA [1] [1] and the interpolation pixel is dx in the x direction and dy in the y direction). It is a coefficient and is determined for each known pixel. In FIG. 3, the filter coefficients are indicated as COEF [m] [n] (m = 0, 1, 2, 3 (x direction); n = 0, 1, 2, 3 (y direction)). In this embodiment, a two-dimensional filter coefficient is used, but the filter coefficient may be decomposed into one dimension.

A-2. Projector configuration:
FIG. 4 is a block diagram schematically showing a configuration of a projector as an embodiment of the present invention. As illustrated, the projector 100 includes a video input unit 110, an IP conversion unit 112, a resolution conversion unit 114, a video synthesis unit 116, a trapezoidal distortion correction unit 120, a liquid crystal panel drive unit 140, and a frame buffer 150. A high-speed bus control unit 160, a low-speed bus control unit 162, a processor unit 170, an imaging unit 180, a sensor unit 182, an illumination optical system 190, a liquid crystal panel unit 192, and a projection optical system 194. Prepare. Each component other than the illumination optical system 190, the liquid crystal panel unit 192, and the projection optical system 194 is connected to each other via the high-speed bus 102 or the low-speed bus 104.

  The video input unit 110 performs A / D conversion on an input video signal input from a DVD player or personal computer (not shown) via a cable, if necessary, and supplies the digital video signal to the IP conversion unit 112.

  The IP conversion unit 112 executes processing for converting the format of the video data supplied from the video input unit 110 from the interlace method to the progressive method, and supplies the obtained video data to the resolution conversion unit 114.

  The resolution conversion unit 114 performs a size enlargement process or a reduction process (that is, resolution conversion process) on the video data supplied from the IP conversion unit 112, and supplies the obtained video data to the video synthesis unit 116. To do.

  The video composition unit 116 synthesizes the video data supplied from the resolution conversion unit 114 and an OSD (On Screen Display) such as a menu screen, and writes the resultant data in the frame buffer 150 as pre-correction video data.

  The frame buffer 150 can store data of one frame or a plurality of frames. In this embodiment, an inexpensive and large-capacity DRAM (Dynamic Random Access Memory) is used as the frame buffer 150. The frame buffer 150 in this embodiment corresponds to a “frame video storage unit” in the claims.

  The trapezoidal distortion correction unit 120 corrects trapezoidal distortion that occurs when projection is performed with the projection axis of the projector 100 tilted with respect to the screen SC. Specifically, in order to display the pre-correction video represented by the pre-correction video data stored in the frame buffer 150 on the liquid crystal panel unit 192 in a shape that compensates for trapezoidal distortion, the correction processing is performed on the pre-correction video data. The corrected video data is supplied to the liquid crystal panel driving unit 140. The trapezoidal distortion correction unit 120 will be described in detail later with reference to FIG.

  The liquid crystal panel drive unit 140 drives the liquid crystal panel unit 192 based on the digital video signal input through the trapezoidal distortion correction unit 120. The liquid crystal panel unit 192 includes a transmissive liquid crystal panel in which a plurality of pixels are arranged in a matrix. The liquid crystal panel unit 192 is driven by the liquid crystal panel driving unit 140, and changes the light transmittance in each pixel arranged in a matrix, thereby changing the illumination light emitted from the illumination optical system 190 to an effective image. An image for modulation into a new image light is formed. In this embodiment, the mode of the liquid crystal panel unit 192 is WUXGA, and the resolution is 1920 × 1200 dots. In this embodiment, the liquid crystal panel pixel coordinates are defined as x = 0 to 1919 and y = 0 to 1199. The liquid crystal panel unit 192 may have a resolution different from that of this embodiment.

  The illumination optical system 190 includes, for example, lamps such as a high pressure mercury lamp and an ultrahigh pressure mercury lamp, and other light emitters. The projection optical system 194 is attached to the front surface of the housing of the projector 100, expands the light modulated into the image light by the liquid crystal panel unit 192, and projects it onto the screen SC. The projection optical system 194 includes a zoom lens (not shown), and can change the degree of enlargement (zoom state) when projecting light transmitted through the liquid crystal panel unit 192. The liquid crystal panel driving unit 140, the liquid crystal panel unit 192, the illumination optical system 190, and the projection optical system 194 in this embodiment correspond to an “image light output unit” and a “display unit” in the claims.

  The processor unit 170 controls the operation of each unit in the projector 100 by reading and executing a control program stored in a storage unit (not shown). Further, corrected coordinates (X0 to X3, Y0 to Y3) described later based on the captured image captured by the imaging unit 180, the tilt of the projector 100 detected by the sensor unit 182 and the instruction from the user (FIG. 2), a conversion coefficient (described in detail later) of the coordinate conversion matrix is calculated and output to the trapezoidal distortion correction unit 120. In this embodiment, the processor unit 170 is configured to receive an instruction from the user through an operation panel (not shown) provided in the main body of the projector 100. For example, the instruction from the user through a remote control is controlled by the remote controller. The processor unit 170 may receive the instruction from the user via the low-speed bus 104.

  The imaging unit 180 includes a CCD camera, and captures an image displayed on the screen SC by the projector 100 to generate a captured image. The captured image generated by the imaging unit 180 is stored in a captured image memory (not shown). Note that the imaging unit 180 may have another imaging device instead of the CCD camera.

  The sensor unit 182 can detect the tilt angle formed by the CCD optical axis of the imaging unit 180 and the horizontal plane by detecting the tilt of the projector 100 from the vertical direction.

A-3. Keystone distortion correction section:
As described above, the trapezoidal distortion correction unit 120 generates post-correction video data in which the pre-correction video represented by the pre-correction video data stored in the frame buffer 150 is corrected to a shape that compensates for trapezoidal distortion. FIG. 5 is a functional block diagram illustrating a configuration of the trapezoidal distortion correction unit 120. The trapezoidal distortion correction unit 120 includes a cache block control unit 121, a cache block storage unit 122, a cache block tag information storage unit 123, an interpolation block reading unit 124, a pixel interpolation unit 125, a FIFO unit 126, and a register. A unit 127, a control unit 128, a coordinate conversion unit 129, a filter coefficient calculation unit 130, a hit determination unit 131, and a prefetch request issuing unit 132.

  The cache block control unit 121 acquires part of the pre-correction video data stored in the frame buffer 150 in units of cache blocks including 8 × 8 pixels and stores the acquired data in the cache block storage unit 122. Hereinafter, the cache block represents video data including a pixel value of 8 × 8 pixels. In addition, the cache block control unit 121 updates tag information described later stored in the cache block tag information storage unit 123. The cache block control unit 121 acquires the cache block specified by the hit determination unit 131 or the prefetch request issuing unit 132 from the frame buffer 150. Specific processing for acquiring the cache block designated by the hit determination unit 131 or the prefetch request issuing unit 132 from the frame buffer 150 will be described later with reference to FIGS. The cache block control unit 121 in this embodiment corresponds to a “block video acquisition unit” in the claims.

  The cache block storage unit 122 stores a part of the pre-correction video data for one frame stored in the frame buffer 150 in units of cache blocks each including 8 × 8 pixels. The cache block storage unit 122 includes a plurality of block areas that can store one cache block. In this embodiment, as will be described in detail later, the cache block storage unit 122 includes a block area of 240 columns × 4 rows. In the present embodiment, the cache block storage unit 122 is configured by a small-capacity and high-speed SRAM (Static Random Access Memory), and the SRAM uses a 1-port RAM to read and write as will be described in detail later. Can be performed simultaneously. The cache block storage unit 122 in this embodiment corresponds to a “block video storage unit” in the claims. In this embodiment, a block area group of 1 column × 4 rows in the cache block storage unit 122 is also referred to as a block area column. That is, the cache block storage unit 122 in the present embodiment has a configuration in which block region columns are arranged in 240 columns in parallel.

  The cache block tag information storage unit 123 includes information on whether or not a cache block is stored for each block area constituting the cache block storage unit 122, information for specifying the stored cache block, etc. Stores tag information which is information for managing the block area. Specific contents of the tag information will be described later with reference to FIG.

  The interpolation block reading unit 124 reads out an interpolation block composed of 4 × 4 pixels necessary for pixel interpolation in the pixel interpolation unit 125 from the cache block storage unit 122 and supplies it to the pixel interpolation unit 125. The position where the interpolation block reading unit 124 reads the interpolation block from the cache block storage unit 122 will be described later with reference to FIG.

  The pixel interpolation unit 125 performs pixel interpolation processing based on the interpolation block supplied from the interpolation block reading unit 124 and the filter coefficient supplied from the filter coefficient calculation unit 130 to obtain the pixel value of the interpolation pixel. The method by which the pixel interpolation unit 125 calculates the pixel value of the interpolation pixel is as described above with reference to FIGS. The pixel interpolation unit 125 calculates the pixel value of one interpolation pixel from one interpolation block and the filter coefficient. In the present embodiment, the pixel interpolation unit 125 first calculates the pixel value of the most upstream pixel (upper left in FIG. 2B) in both the x direction and the y direction of the corrected video, and thereafter, FIG. The pixel values are sequentially calculated for the pixels on the downstream side in the x direction according to the arrow direction. When the pixel value of the pixel on the most downstream side in the x direction is calculated, the pixel value is calculated in order from the pixel on the most upstream side in the x direction in the same way for a column on the downstream side in the y direction. This is sequentially repeated, and the corrected video data representing the corrected video is generated by calculating up to the pixel value of the most downstream pixel in both the x and y directions. The generated corrected video data is output to the liquid crystal panel driving unit 140 (FIG. 4) via the FIFO unit 126. The interpolation block reading unit 124 and the pixel interpolation unit 125 in this embodiment correspond to a “correction processing unit” in the claims.

  The register unit 127 stores parameters supplied from the processor unit 170. Specifically, the register unit 127 stores parameters such as the frame width and frame height of one frame of the pre-correction video, and the transformation coefficients A to H of the coordinate transformation matrix. The conversion coefficients A to H are calculated by the processor unit 170 using the following determinant (formula 1) of projective transformation. Specifically, the processor unit 170 converts the uncorrected coordinates (x0 to x3, y0 to y3) (see FIG. 2) into the corrected coordinates (X0 to X3, Y0 to Y3) (see FIG. 2) by projective transformation. As converted, the four coordinates (X0 to X3, Y0 to Y3) of the corrected image IG1 are input to the determinant (Formula 1) to derive the coefficients A to H.

  In this embodiment, before the correction image data generation process is started, the image PIG0 displayed on the screen SC before the trapezoidal distortion correction is imaged by the imaging unit 180. The processor unit 170 (FIG. 4) obtains the coordinates (X0 to X3, Y0 to Y3) (FIG. 2B) of the four vertices in the corrected image IG1 after the trapezoidal distortion correction based on the captured image. Yes.

  Note that the sensor unit 182 may detect the inclination of the projector 100 from the vertical direction, and obtain corrected coordinates (X0 to X3, Y0 to Y3) based on the detected angle. Also, the keystone distortion correction may be performed manually by the user operating the remote controller. In such a case, the processor unit 170 obtains corrected coordinates (X0 to X3, Y0 to Y3) based on an instruction from the user received via the remote control unit.

  The control unit 128 performs overall control of the trapezoidal distortion correction unit 120. For example, a frame start signal indicating the start of a frame is output to the coordinate conversion unit 129 in accordance with the synchronization signal input to the control unit 128. For example, when 60 frames are displayed per second, the synchronization signal is input every 1/60 seconds.

  The coordinate conversion unit 129 uses the coordinate conversion coefficients A to H supplied from the register unit 127 and the following (Expression 2) and (Expression 3) to correct the coordinates of the corrected image IG1 after performing the trapezoidal distortion correction. The value (coordinate after correction) is converted into the coordinate value (coordinate before correction) of the pre-correction video IG0 (rectangular video). Since the pre-correction video IG0 and the post-correction video IG1 do not have an integer multiple correspondence, the pre-correction coordinates calculated by the coordinate conversion unit 129 include decimals. The coordinate conversion unit 129 divides the coordinates before correction into an integer part and a decimal part, supplies the integer part to the hit determination unit 131 and the prefetch request issuing unit 132, and supplies the decimal part to the filter coefficient calculation unit 130.

  Here, the above-described calculation method of the pre-correction coordinates will be described. Since the corrected image IG1 is considered to be an image obtained by projective transformation of the uncorrected image IG0, the uncorrected coordinates are based on the following (Expression 2) and (Expression 3) with respect to the corrected coordinates. Then, it is calculated by reverse projective transformation. It is assumed that the uncorrected coordinates (x, y) are converted to corrected coordinates (X, Y) by projective transformation.

上記（式２）、（式３）中の係数Ａ〜Ｈは、レジスター部１２７に記憶されている。

The coefficients A to H in the above (Expression 2) and (Expression 3) are stored in the register unit 127.

  Based on the decimal part supplied from the coordinate conversion unit 129, the filter coefficient calculation unit 130 selects a filter coefficient used when executing the pixel interpolation process from the filter coefficient table, and selects the selected filter coefficient as a pixel. This is supplied to the interpolation unit 125. The filter coefficient table is a table showing the relationship between the distance between the interpolation pixel and the known pixel shown in FIG. 3 and the filter coefficient, and a result calculated in advance is stored in a memory included in the filter coefficient calculation unit 130.

  The hit determination unit 131 determines whether the pixel value of the coordinates used for pixel interpolation in the pixel interpolation unit 125 is stored in the cache block storage unit 122 based on the integer part of the coordinates before correction supplied from the coordinate conversion unit 129. Determine whether. Hereinafter, this determination is referred to as “hit determination”. If the pixel value necessary for pixel interpolation is not stored in the cache block storage unit 122 as a result of the hit determination, the cache block control unit 121 receives a necessary cache block read request (hereinafter, “miss hit request”). Is also issued). As a result of the hit determination, when a pixel value necessary for pixel interpolation is stored in the cache block storage unit 122, the read position in the cache block storage unit 122 is supplied to the interpolation block reading unit 124. The flow of the hit determination process will be described later with reference to FIGS. The hit determination unit corresponds to the “determination unit” in the claims.

  The prefetch request issuing unit 132 predicts a cache block necessary for the subsequent pixel interpolation processing based on the integer part of the coordinates before correction supplied to the coordinate conversion unit 129. The prefetch request issuing unit 132 stores the predicted cache block in the cache block storage unit 122 by issuing a predicted cache block read request (hereinafter also referred to as “prefetch request”) to the cache block control unit 121. Let The prefetch request issuing unit 132 predicts a cache block necessary for the subsequent pixel interpolation process when the interpolation block reading unit 124 reads an interpolation block from a predetermined cache block. Specific processing by the prefetch request issuing unit 132 will be described later. The cache block prediction described above is also referred to as “prefetch determination”. The prefetch request issuing unit 132 corresponds to a “block video prediction unit” in the claims.

  The flow of the operation of each of the constituent parts constituting the trapezoidal distortion correcting part 120 will be briefly described. FIG. 6 is a process diagram schematically showing an operation flow of the trapezoidal distortion correction unit 120. First, the coordinate conversion unit 129 (FIG. 5) of the trapezoidal distortion correction unit 120 stands by until a frame start signal is input (step S102: NO), and when a frame start signal is input (step S102: YES). Then, the coordinates of the corrected image (corrected coordinates) are converted to obtain the coordinates before correction (step S104). The method for calculating the coordinates before correction by converting the coordinates after correction is as described above.

  The hit determination unit 131 (FIG. 5) supplies the interpolation block readout position to the interpolation block readout unit 124 based on the integer part of the coordinates before correction calculated by the coordinate conversion unit 129. The interpolation block reading unit 124 (FIG. 5) reads the interpolation block from the cache block storage unit 122 based on the supplied reading position (step S106). On the other hand, the filter coefficient calculation unit 130 (FIG. 5) selects a filter coefficient from the filter coefficient table based on the decimal part of the coordinates before correction obtained in step S104. The interpolation block readout process (also referred to as “block read”) in step S106 and the filter coefficient calculation process in step S108 are performed simultaneously. When both processes are completed, the process proceeds to the next process (step S110).

  The pixel interpolation unit 125 (FIG. 5) calculates the pixel value of the corrected coordinates using the interpolation block and the filter coefficient (step S110). Specifically, the pixel interpolation unit 125 uses the interpolation block supplied from the interpolation block reading unit 124 and the filter coefficient supplied from the filter coefficient calculation unit 130 to calculate the pixel value of the corrected coordinate by a convolution operation. calculate.

  The trapezoidal distortion correction unit 120 repeats the above steps S104 to S110 from the corrected coordinates (X, Y) = (0, 0) to (frame width−1, frame height−1). Generate corrected video data. In this embodiment, since the frame width is 1920 and the frame height is 1200, steps S104 to S110 are repeated until the corrected coordinates (X, Y) = (0, 0) to (1919, 1199). When the frame width and the frame height are different from those of the present embodiment, the steps S104 to S110 are performed after the corrected coordinates (X, Y) = (0, 0) to (frame width−1, frame height− By repeating the process up to 1), the corrected video data can be generated.

  FIG. 7 is an explanatory diagram showing the timing of each process when the trapezoidal distortion correction unit 120 calculates the pixel value of one pixel of the corrected image. When the coordinate conversion unit 129 receives the frame start signal output from the control unit 128, the coordinate conversion unit 129 starts coordinate conversion processing. When the coordinate conversion process is completed and the pre-correction coordinates are calculated, the filter coefficient calculation unit 130 starts the filter coefficient calculation process, and the hit determination unit 131 performs a tag information read process for hit determination. Start.

  When the hit determination unit 131 determines that the cache block including the area to be read by the interpolation block reading unit 124 is not stored in the cache block storage unit 122 as a result of performing the hit determination by reading the tag information, It waits for a cache block including an area to be read by the interpolation block reading unit 124 to be stored in the cache block storage unit 122 (hereinafter also referred to as “block write wait”).

  On the other hand, at the same time as the filter coefficient calculation process and the tag information read process, the prefetch request issuing unit 132 determines whether or not the cache block is prefetched. If necessary, the cache block read request (prefetch request) ). When a cache block read request is issued from the hit determination unit 131 or the prefetch request issuing unit 132, the cache block control unit 121 reads the cache block from the requested position in the frame buffer 150 and stores it in the cache block storage unit 122. To do. When the cache block including the area to be read by the interpolation block is stored in the cache block storage unit 122, the hit determination unit 131 stores the cache block including the area to be read by the interpolation block in the cache block storage unit 122. The interpolation block reading unit 124 reads the interpolation block from the newly stored cache block.

  When the calculation of the filter coefficient and the reading of the interpolation block are completed, the pixel interpolation unit 125 starts pixel interpolation. In FIG. 7, the solid line frame indicates that the processing time is fixed, and the broken line frame indicates that the processing time is variable. Further, the length of the frame does not represent the length of processing. In this embodiment, the block write waiting time in the hit determination unit is shortened by making a prefetch request.

A-4. Prefetch determination:
Prior to the description of the prefetch determination in the prefetch request issuing unit 132, the relationship between the frame buffer 150, the cache block storage unit 122, and the cache block tag information storage unit 123 in this embodiment, and the relationship between the cache block and the interpolation block. This will be described in detail.

  FIG. 8 is a diagram schematically illustrating the relationship between the frame buffer 150 and the cache block storage unit 122. FIG. 8 shows a state where the pre-correction video data for one frame stored in the frame buffer 150 is divided into cache block units each consisting of 8 × 8 pixels. In this embodiment, the pre-correction video data stored in the frame buffer 150 is composed of 1920 × 1200 pixels, and such pre-correction video data is divided into 240 × 150 cache blocks. The position of each cache block in the pre-correction video data stored in the frame buffer 150 shown in FIG. 8 is the position of the video (region) represented by each cache block in the pre-correction video represented by the pre-correction video data. It corresponds to. In FIG. 8, the character string (x, y) described in each cache block indicates the position (column number, line number) in the x direction and y direction of the cache block. In this embodiment, the direction in which the columns are arranged is the x direction, and the direction in which the rows are arranged is the y direction. In both the x-direction and the y-direction, the side of the cache block with the smaller character string (x, y) number is called the upstream side, and the side with the larger character string (x, y) number is called the downstream side.

  The cache block storage unit 122 includes 240 × 4 rows of block areas that can store one cache block. In FIG. 8, in order to identify each block area, numbers (column (0-239), row (0-3)) are given. That is, in the cache block storage unit 122, block region columns composed of four block regions (rows 0 to 3) arranged in the direction along the y direction are arranged in 240 columns (columns 0 to 239) in the direction along the x direction. It has a configuration. The cache block storage unit 122 can store 240 × 4 pieces of partial data (cache blocks) of pre-correction video data for one frame stored in the frame buffer 150.

  In this embodiment, when the trapezoidal distortion correction process is started, first, the cache blocks (0, 0) to (239, 3) are read from the frame buffer 150 and stored in the cache block storage unit 122. . The cache block is stored in the block area having the same column number as the column number of each cache block in the cache block storage unit 122. Therefore, when the trapezoidal distortion correction process is started, first, in each block area of the cache block storage unit 122, a cache block having a column number and a row number identical to the column number and line number of the block area is stored. (FIG. 8). The width of the cache block storage unit 122 is the same as the width of the frame buffer 150. The height of the cache block storage unit 122 is 4 cache blocks, and pixel data for 32 lines (4 cache blocks × 8 px) of one frame is stored. In the cache block storage unit 122, the cache blocks are sequentially stored in the order of the column numbers of the frame buffer 150, that is, from the upstream side to the downstream side in the x direction. Can do.

  The cache block tag information storage unit 123 stores tag information that is management information when the cache block storage unit 122 is managed in units of block areas. FIG. 9 is a diagram conceptually illustrating the relationship between the cache block storage unit 122 and the cache block tag information storage unit 123. As shown in the figure, the cache block tag information storage unit 123 stores 240 × 4 tag information corresponding to the 240 × 4 block areas of the cache block storage unit 122.

  Specifically, as tag information, (1) information indicating whether or not to wait for writing from the frame buffer 150 to the cache block storage unit 122 (WRITING = 1 in the case of waiting for writing), and (2) data in the block area is valid. (Valid = 1 when valid, valid = 0 when invalid), and (3) a coordinate Y_ADR indicating where in the frame buffer 150 the cache block stored in the block area is located Stored. The coordinate Y_ADR in (3) holds information in which the y coordinate in the frame buffer 150 of the upper left pixel of the cache block is 1/8. In this embodiment, the line number shown in FIG. 8 is set as the coordinate Y_ADR. In (2), “valid” indicates that the cache block is stored in the cache block storage unit 122, and “invalid” indicates that the cache block is not stored in the cache block storage unit 122. In this embodiment, at the start of the trapezoidal distortion correction process, before the cache blocks (0, 0) to (239, 3) are stored in the cache block storage unit 122, all tag information includes “invalid ( VALID = 0) ”.

  FIG. 10 is a diagram illustrating the relationship between the cache block and the interpolation block. In FIG. 10, the interpolation block is indicated by hatching. In this embodiment, since the cache block is composed of 8 × 8 pixels and the interpolation block is composed of 4 × 4 pixels, the interpolation block becomes a part of the cache block.

  As will be described later, the cache blocks stored in the cache block storage unit 122 are sequentially updated for each block area column as the trapezoidal distortion correction process proceeds. Therefore, during the trapezoidal distortion correction process, the cache blocks of the frame buffer 150 corresponding to the cache blocks stored in the cache block storage unit 122 are stepped as shown in FIG. 10, for example.

  FIG. 11 is an explanatory diagram for explaining prefetch determination in the prefetch request issuing unit 132. In FIG. 11, the cache block (u, v), the cache block (u, v + 1), the cache block (u, v + 2), and the cache block (u, v + 3) of the video data before correction are the block areas of the cache block storage unit 122. It is assumed that (u, 0), block area (u, 1), block area (u, 2), and block area (u, 3) are stored.

  The prefetch request condition is that the integer part Int (x, y) of the coordinates before correction input to the prefetch request issuing unit 132 is a row of cache blocks stored in each block area column of the cache block storage unit 122. This means that the cache block with the highest number has been entered. When a prefetch request is issued, the cache block control unit 121 reads out from the frame buffer 150 a cache block having one row number larger than the cache block having the largest row number in each block area column, and the cache block storage unit Of the cache blocks stored in 122, the block area in which the cache block with the smallest row number is stored is overwritten.

  A specific example of the prefetch determination will be described with reference to FIG. The prefetch request issuing unit 132 has the input integer part Int (x, y) of the coordinates before correction, among the plurality of cache blocks stored in the block area column, the cache block (u, It is determined whether it is included in v + 3). When the integer part Int (x, y) is included in the cache block (u, v + 3), the prefetch request issuing unit 132 stores the cache block (u, v + 3) next to the cache block (u, v + 3) with the largest row number ( A read request for reading u, v + 4) from the frame buffer 150 is issued to the cache block control unit 121. In the read request, the coordinates in the frame buffer 150 of the block to be prefetched, that is, the row number and column number of the cache block, and the coordinate position of the cache block storage unit 122 that stores the cache block, that is, the row number and column of the block area Numbers etc. are included. When the cache block control unit 121 receives the read request, the block area (u, 0) in which the cache block (u, v) having the smallest row number among the cache blocks stored in the block area column is stored. In addition, the previously read cache block (u, v + 4) is overwritten.

  In this embodiment, the prefetch request issuing unit 132 and the cache block (u, v + 3) representing the most downstream area in the y direction of the frame buffer 150 among the cache blocks stored in the block area column and the pre-correction video , The cache block (u, v + 4) representing an adjacent area on the downstream side is predicted as a cache block from which the interpolation block reading unit 124 later acquires the interpolation block video data.

  Note that the prefetch request issuing unit 132 updates the tag information corresponding to the designated block area as well as issuing a read request. Specifically, WRITEING = 1 and Y_ADR is set to the coordinates (line number) of the cache block to be prefetched. Further, when the designated cache block is stored in the block area designated by the prefetch request, the prefetch request issuing unit 132 sets the corresponding tag information in the cache block tag information storage unit 123 to VALID = 1 and WRITEING = 0. Update.

  FIG. 12 is an explanatory diagram for explaining the order in which cache blocks stored in the cache block storage unit 122 are updated. FIG. 12 illustrates a cache block stored in the second block area column in the cache block storage unit 122. In FIG. 12, each cache block stored in the block area column is identified using the coordinates in the pre-correction video of the upper left pixel of each cache block. For example, a cache block whose coordinates in the pre-correction image of the upper left pixel are (16, 0) is indicated as a cache block (16, 0).

  FIG. 12A illustrates a cache block stored in each block area of the block area sequence at the start of the trapezoidal distortion correction process. Here, cache block (16, 0) is stored in block area (2, 0), cache block (16, 8) is stored in block area (2, 1), and block area (2, 2). The cache block (16, 16) is stored in, and the cache block (16, 24) is stored in the block area (2, 3). When the integer part Int (x, y) of the coordinates before correction input to the prefetch request issuing unit 132 enters the cache block (16, 24), that is, the integer part of the input y coordinate is 24 to 31. In the case where the pre-read request is issued, the cache block (16, 32) is read from the frame buffer 150. Then, among the cache blocks stored in the second block area column of the cache block storage unit 122, the block area (2, 0) in which the cache block (16, 0) having the smallest y coordinate is stored. ) Is overwritten with the read cache block (16, 32) (FIGS. 12A and 12B).

  Thereafter, when the integer part Int (x, y) of the coordinates before correction input to the prefetch request issuing unit 132 enters the cache block (16, 32), that is, the integer part of the input y coordinate is 32 to 32. If it is 39, the next prefetch request is issued and the cache block (16, 40) is read from the frame buffer 150. Then, among the cache blocks stored in the second block area column of the cache block storage unit 122, the block area (2, 1) in which the cache block (16, 8) having the smallest y coordinate is stored. ) Is overwritten with the read cache block (16, 40) (FIGS. 12B and 12C).

A-5. Hit judgment:
FIG. 13 is an explanatory diagram illustrating an example of hit determination using tag information. FIG. 13 illustrates tag information corresponding to the cache block stored in the cache block storage unit 122 illustrated in FIG. That is, tag information related to the block area (2, 0) in the cache block storage unit 122 is stored in 2 columns and 0 rows of the cache block tag information storage unit 123. The 16 pixels used for pixel interpolation are (x [0], y [0]), (x [1], y [1]), (x [2], y [2]), ..., (x [15], y [15]), hit determination is performed pixel by pixel in order from (x [0], y [0]). For example, hit determination when (x [0], y [0]) = (16, 40) will be described with reference to FIG.

  When determining whether or not a cache block including (x [0], y [0]) = (16, 40) is stored in the cache block storage unit 122, first, the hit determination unit 131 uses the cache block The tag of the corresponding column is extracted from the tag information storage unit 123. Since one cache block is composed of 8 × 8 pixels, the corresponding column can be obtained by dividing the x coordinate of the pixel used for pixel interpolation by 8. Since (x [0], y [0]) = (16, 40) corresponds to the second column, the tag in the second column is extracted.

  In FIG. 13, the extracted tag information is described on the right side of the page. The hit determination unit 131 performs hit determination in ascending order of tag line numbers. Hereinafter, tag information is represented by TAG [line number]. TAG [0] is WRITEING = 0, VALID = 1, and Y_ADR = 4. WRITEING = 0 indicates that prefetching is not being performed, and VALID = 1 indicates that the data is valid. When Y_ADR = 4 is converted to the y coordinate of the pre-correction video, 4 × 8 = 32. That is, according to TAG [0], it can be seen that a block of y-coordinate = 32 of the pre-correction video exists in the cache block storage unit 122.

  TAG [1] is WRITEING = 1, VALID = 0, and Y_ADR = 5. WRITEING = 1 indicates that prefetching is in progress, and VALID = 0 indicates that the data is invalid. When Y_ADR = 5 is converted into the y coordinate of the pre-correction video, 5 × 8 = 40. That is, according to TAG [1], it can be seen that the block of y-coordinate = 40 in the pre-correction video is being pre-read and can be read after a while.

  TAG [2] is WRITEING = 0, VALID = 1, and Y_ADR = 2. WRITEING = 0 indicates that prefetching is not being performed, and VALID = 1 indicates that the data is valid. When Y_ADR = 2 is converted to the y coordinate of the pre-correction video, 2 × 8 = 16. That is, according to TAG [2], it can be seen that the block of y coordinate = 16 of the pre-correction video exists in the cache block storage unit 122.

  TAG [3] is WRITEING = 0, VALID = 1, and Y_ADR = 3. WRITEING = 0 indicates that prefetching is not being performed, and VALID = 1 indicates that the data is valid. When Y_ADR = 3 is converted into the y coordinate of the pre-correction video, 3 × 8 = 24. That is, according to TAG [3], it can be seen that the block of y coordinate = 24 of the pre-correction video exists in the cache block storage unit 122.

  That is, as a result of determining whether or not a cache block including (x [0], y [0]) = (16, 40) is stored in the cache block storage unit 122, (x [0], y [0 ]) = (16, 40) is included in the prefetch, and after a while, it is determined that the cache block can be read.

  14 and 15 are process diagrams schematically showing the process of hit determination processing in the hit determination unit 131 (FIG. 5). When the integer part Int (x, y) of the coordinates before correction is input from the coordinate conversion unit 129 to the hit determination unit 131, the hit determination process in the hit determination unit 131 is started. Based on the integer part Int (x, y) of the uncorrected coordinates input from the coordinate conversion unit 129, the hit determination unit 131 coordinates (x [0], y [0]), (x [1], y [1]), (x [2], y [2]),..., (X [15], y [15]) are calculated (step S202). Subsequent processing includes coordinates (x [0], y [0]), (x [1], y [1]), (x [2], y [2]),. 15], y [15]).

  When the calculation of the coordinates of the surrounding 16 pixels is completed, the hit determination unit 131 reads the tag information (TAG [0], [1], [2], [3]) from the cache block tag information storage unit 123 (Step S1). In S204, it is determined whether Y_ADR of TAG [0] (that is, the line number of the cache block) is equal to y [0] / cache block height (8 px) (step S206). If they are the same (YES in step S206), the hit determination unit 131 determines whether or not WRITE [1] of TAG [0] is 1 (step S208). On the other hand, if they are not the same (NO in step S206), the process proceeds to step S216.

  If WRITEING = 1 in step S208, the process returns to step S204. If WRITEING = 0, the hit determination unit 131 determines whether VALID = 1 of TAG [0] is set (step S210). When VALID = 1, the hit determination unit 131 calculates the coordinates (column, row) of the cache block corresponding to the hit tag (step S212). On the other hand, if VALID = 0, the hit determination unit 131 reads the cache block (x [0] / cache block width (8 px), y [0] / cache block height (8 px)). Is output to the cache block control unit 121 (step S214).

  In steps S216, S226, and S236, processing similar to that in step S206 is performed for TAG [1], TAG [2], and TAG [3], respectively. In steps S218, S228, and S238, processing similar to that in step S208 is performed for TAG [1], TAG [2], and TAG [3], respectively. In steps S220, S230, and S240, processing similar to that in step S210 is performed for TAG [1], TAG [2], and TAG [3], respectively.

  That is, if the line number of the cache block included in the tag information is not the same as y [0] / 8, the first processing is performed from the tag information on the 0th line so that the same processing is performed on the next tag information. The tag information is determined in order of the line, the second line, and the third line. In steps S208, S218, S228, and S238, WRITEING = 1 means that the cache block is being written to the block area corresponding to the tag information, so that writing is completed, that is, WRITEING = 0. Until it is, reading and determination of tag information are repeated. If VALID = 1 in steps S210, S220, S230, and S240, it can be said that the cache block including the pixel value of the target coordinate exists (hits) in the cache block storage unit 122. The coordinates (column, row) of the corresponding cache block are calculated.

A-6. Cache block controller:
As described above, the cache block control unit 121 acquires from the frame buffer 150 the cache block specified in the miss hit request issued by the hit determination unit 131 or the prefetch request issued by the prefetch request issue unit 132. FIG. 16 is a functional block diagram showing the configuration of the cache block control unit 121 in the first embodiment. The cache block control unit 121 includes a prefetch request buffer 134, a miss hit request buffer 135, a buffer management tag unit 136, a buffer state determination unit 137, a buffer read control unit 138, and a cache block acquisition unit 139. ing.

  The prefetch request buffer 134 includes a storage area for storing a prefetch request issued from the prefetch request issuing unit 132. The miss hit request buffer 135 includes a storage area for storing a miss hit request issued from the hit determination unit 131. The buffer management tag unit 136 stores management information for managing read requests such as prefetch requests and miss hit requests stored in the storage areas of the prefetch request buffer 134 and the miss hit request buffer 135. The management information is, for example, read request address information stored in the respective storage areas of the prefetch request buffer 134 and the miss hit request buffer 135, or the read request is stored in each of the prefetch request buffer 134 and the miss hit request buffer 135. Order information indicating the order stored in the area, information indicating whether the request is read out by the buffer read control unit 138, and the like are included. The prefetch request buffer 134 corresponds to the “first buffer unit” in the claims. Further, the miss hit request buffer 135 corresponds to a “second buffer unit” in the claims. As shown in FIG. 10, since the interpolation block spans up to four cache blocks, the miss hit request buffer 135 has a storage area capable of storing at least four miss hit requests simultaneously.

  When the buffer state determination unit 137 receives the prefetch requests issued from the prefetch request issuing unit 132, the buffer state determination unit 137 stores the prefetch requests in the order in which they are issued. In addition, when the buffer state determination unit 137 receives a miss hit request issued from the hit determination unit 131, the buffer state determination unit 137 stores it in the miss hit request buffer 135 in the issued order. The buffer status determination unit 137 refers to the management information of the buffer management tag unit 136, and in each of the prefetch request buffer 134 and the miss hit request buffer 135, a read request (not yet read by the buffer read control unit 138) ( The received read request (prefetch request or mishit request) is stored in an area other than the area where the prefetch request or mishit request is stored. The buffer state determination unit 137 updates the management information of the buffer management tag unit 136 when the received prefetch request or miss hit request is stored in the prefetch request buffer 134 or the miss hit request buffer 135, respectively.

  The buffer read control unit 138 reads the prefetch request stored in the prefetch request buffer 134 and the miss hit request stored in the miss hit request buffer 135. The buffer read control unit 138 reads the read-ahead request and the miss-hit request from the read-ahead request buffer 134 and the miss-hit request buffer 135 with reference to the buffer management tag unit 136, respectively. The data is output to the acquisition unit 139. The order in which the buffer read control unit 138 reads the prefetch request and the miss hit request from the prefetch request buffer 134 and the miss hit request buffer 135 (hereinafter also referred to as “read order”) will be described later with reference to FIG. The buffer read control unit 138 updates the management information of the buffer management tag unit 136 when reading the prefetch request and the miss hit request. The buffer read control unit 138 corresponds to a “read unit” in the claims.

  The cache block acquisition unit 139 reads the cache block specified in the prefetch request and the miss hit request from the frame buffer 150 according to the order read by the buffer read control unit 138, and stores the cache block in the block area of the cache block storage unit 122. . The cache block acquisition unit 139 stores the pixel value of each pixel constituting the cache block in the frame buffer 150 from the position information indicating the position to read the cache block included in the prefetch request and the miss hit request. The cache block is read by reading the pixel value of each pixel from the generated address. The cache block acquisition unit 139 corresponds to an “acquisition unit” in the claims.

  FIG. 17 is an explanatory diagram for explaining the read order of the prefetch request and the miss hit request by the buffer read control unit 138. FIG. 17A is an explanatory diagram showing a state in which a prefetch request is stored in the prefetch request buffer 134. FIG. 17B is an explanatory diagram showing a state in which a miss hit request is stored in the miss hit request buffer 135. FIG. 17C is an explanatory diagram for explaining a state in which a miss hit request is read. FIG. 17D is an explanatory diagram for explaining a state in which a prefetch request is read. FIG. 18 is an explanatory diagram for explaining the reading position of the interpolation block in FIG. FIG. 19 is an explanatory diagram for explaining a reading position of the interpolation block in FIG. FIG. 20 is an explanatory diagram for explaining the reading position of the interpolation block in FIG. FIG. 21 is an explanatory diagram for explaining the reading position of the interpolation block in FIG.

  FIG. 17 shows the prefetch request and the miss hit request stored in the prefetch request buffer 134 and the miss hit request buffer 135 in the order in which they are issued. The prefetch request and the miss hit request are stored side by side at the addresses of the storage areas constituting the prefetch request buffer 134 and the miss hit request buffer 135 in the order in which they are stored. “Column” and “Row” described in the prefetch request and the miss hit request in FIG. 17 request reading from each cache block constituting the uncorrected video data for one frame stored in the frame buffer 150. Position information for specifying the cache block to be read, and represents the column address and row address of the cache block to be read. For example, a prefetch request and a miss hit request including position information of “Column: 0 Row: 7” have a coordinate position of “0” in the Column direction (x direction) and a Row direction (y This is a request for reading out the cache block with the coordinate position of (direction) “7”, that is, the cache block (0, 7) from the frame buffer 150 and storing it in the block area of the cache block storage unit 122. As the column address and row address, for example, as shown in FIG. 12, the address of a storage area in which the pixel value of the upper left pixel of each cache block in the frame buffer 150 is stored may be used. The numbers 1 to 9 described on the right side of the prefetch request and the miss hit request indicate the order in which they are stored in the prefetch request buffer 134 or the miss hit request buffer 135.

  18 to 21 correspond to the frame buffer 150 and the cache block storage unit 122 shown in FIG. 10, and the rectangles indicated by hatching indicate the interpolation blocks. Numbers 1 to 15 described in the respective interpolation blocks indicate the order in which the interpolation blocks are acquired from the cache block storage unit 122. As illustrated in FIG. 18, when the first, second, fourth to ninth interpolation blocks are acquired from the cache block storage unit 122, the prefetch request issuing unit 132 performs cache block (0, 7), (1 , 7), (3, 6), (4, 6), (5, 6), (6, 5), (7, 5), (8, 5), a prefetch request is issued. . FIG. 17A shows a state in which the prefetch requests (No. 1 to No. 8) issued by the prefetch request issuing unit 132 are stored in the prefetch request buffer 134.

  The buffer read control unit 138 reads the prefetch requests in order from the prefetch request stored in the prefetch request buffer 134 in the order of the oldest stored time. In this embodiment, since the prefetch request with the earliest time stored in the prefetch request buffer 134 is the first prefetch request “Column: 0 Row: 7”, the buffer read control unit 138 first reads the prefetch request “ “Column: 0 Row: 7” is read. The read prefetch request is output to the cache block acquisition unit 139. The cache block acquisition unit 139 reads the cache block (0, 7) designated by the first prefetch request from the frame buffer 150 and stores it in the block area of the cache block storage unit 122.

  After reading the first prefetch request, the buffer read control unit 138 reads the second prefetch request “Column: 1 Row: 7” and outputs it to the cache block acquisition unit 139. Similarly, the cache block acquisition unit 139 reads the cache block (1, 7) designated by the second prefetch request from the frame buffer 150 and stores it in the block area of the cache block storage unit 122. By repeating the above, the buffer read control unit 138 sequentially reads the prefetch requests stored in the prefetch request buffer 134 from the oldest time, and the cache block acquisition unit 139 stores the cache block specified in the read prefetch request. The data is sequentially stored in the block area of the cache block storage unit 122.

  In FIG. 19, prefetch requests No. 1 to No. 4 are read out as described above, and the cache blocks (0, 7), (1, 7), (3, 6), (4, 4) designated in the prefetch request are read. 6) shows the state stored in the cache block storage unit 122. At this time, the 10th to 12th interpolation blocks are read in parallel with the reading of the 1st to 4th prefetch requests. At this time, for the 10th and 11th interpolation blocks, the cache blocks (0, 7) and (1, 7) are stored in the cache block storage unit 122 by reading the first and second prefetch requests. Therefore, the interpolation block is read out. However, for the 12th interpolation block, the cache block (2, 7) is not stored in the cache block storage unit 122. ) Is issued for obtaining a hit. FIG. 17B shows a state where the ninth miss-hit request for acquiring the cache block (2, 7) is stored in the miss-hit request buffer 135.

  As shown in FIG. 17B, the buffer read control unit 138 reads the prefetch request from the prefetch request buffer 134, and if a miss hit request is stored in the miss hit request buffer 135, the prefetch is read. Instead of reading the prefetch request from the request buffer 134, the miss hit request is read from the miss hit request buffer. That is, the buffer read controller 138 reads from the miss-hit request buffer in preference to reading from the prefetch request buffer 134. In the present embodiment, as shown in FIG. 17C, the buffer read control unit 138 interrupts the reading of the prefetch request from the prefetch request buffer 134 and reads the fifth prefetch request “Column: 5 Row: 6”. Before No. 9, the ninth miss hit request “Column: 2 Row: 7” stored in the miss hit request buffer 135 is read. The cache block acquisition unit 139 stores the cache block (2, 7) specified in the read mishit request in the block area of the cache block storage unit 122. FIG. 20 shows a state in which the cache block (2, 7) is stored in the cache block storage unit 122. When the cache block (2, 7) is stored in the cache block storage unit 122, the 12th interpolation block is read.

  The buffer read control unit 138 reads the prefetch request from the prefetch request buffer 134 again when there is no mishit request in the mishit request buffer 135 by reading the ninth miss hit request “Column: 2 Row: 7”. Do it. In this embodiment, as illustrated in FIG. 17C, the buffer read control unit 138 resumes reading from the prefetch request “Column: 5 Row: 6” stored in the prefetch request buffer 134. In FIG. 21, the prefetch requests No. 5 to No. 7 are read by the buffer read control unit 138, and the cache blocks (5, 6), (6, 5), and (7, 5) are read by the cache block acquisition unit 139. The state stored in the cache block storage unit 122 is shown. At this time, the 13th to 15th interpolation blocks are read in parallel with the reading of the 5th to 7th prefetch requests. FIG. 17D shows the state of the prefetch request buffer 134 after the prefetch requests No. 5 to No. 7 are read. In this embodiment, the prefetch request issued by the prefetch request issuing unit 132 when the 10th to 15th interpolation blocks are acquired from the cache block storage unit 122 is not shown. The read control unit 138 sequentially reads prefetch requests newly stored in the prefetch request buffer 134 when the 10th to 15th interpolation blocks are acquired from the cache block storage unit 122. As described above, the buffer read control unit 138 reads the prefetch request and the miss hit request from the prefetch request buffer 134 and the miss hit request buffer 135.

  The cache block acquisition unit 139, for example, No. 1 and No. 2 or No. 3 to No. 5 for the cache blocks specified by the prefetch request or the miss hit request shown in Nos. 1 to 9 in FIG. When the coordinate positions in the row direction of the cache blocks in which the acquisition order is continuous are the same, the address specified for acquiring the pixel value of each pixel constituting the cache block is straddled across the cache blocks for each row direction. An address is generated so as to read out the pixel value. That is, in the case where cache blocks having the same coordinate position in the Row direction are continuously acquired, the most upstream line in the Row direction (y direction) among the 8 × 8 pixels constituting each cache block is configured. The respective addresses for acquiring the pixel values of the eight pixels are continuously generated. Thereafter, the respective addresses for acquiring the pixel values of the eight pixels constituting one column downstream in the row direction (y direction) are successively generated. Similarly, the respective addresses are continuously generated for the third to eighth stages in the row direction (y direction). The reading order of pixel values using addresses generated in the above order will be described with reference to FIG.

  FIG. 22 is an explanatory diagram for explaining the reading order of the pixel values of each pixel constituting the cache block by the cache block acquisition unit 139. FIG. 22A shows the readout order of pixel values according to the present invention, and FIG. 22B shows a comparative example. 22A and 22B, the direction in which the pixel value of each pixel constituting the cache block is read out is indicated by an arrow in each cache block. As shown in FIG. 22 (a), the cache block acquisition unit 139 reads back a plurality of cache blocks having the same row direction (y direction) and having a continuous read order, for each cache block. Instead, pixel values are continuously read across the cache blocks for pixels having the same position in the row direction (y direction). When the reading of the pixel values for one line in the most downstream cache block in the Column direction (x direction) is completed, it is folded back in the Row direction (y direction) of the most upstream cache block in the Column direction (x direction). The pixel values of the pixels constituting one row downstream are read. By repeating this for the third to eighth stages in the Row direction (y direction), reading of a plurality of cache blocks having the same Row direction (y direction) is completed.

  The cache block acquisition unit 139 in the comparative example generates an address so as to read out the pixel value for each cache block with respect to an address designated for acquiring the pixel value of each pixel constituting the cache block. Therefore, as shown in FIG. 22B, the cache block acquisition unit 139 reads out the pixel value while turning back the line to be read out for each cache block. Specifically, the cache block acquisition unit 139 reads from each pixel constituting one row on the most upstream side in the row direction (y direction) of the cache block (0, 0), and then continuously reads the cache block ( (1, 0) Row direction (y direction) Rather than reading from each pixel constituting one row on the most upstream side, the first row in the row direction (y direction) of the cache block (0, 0) is folded. Read out from each pixel constituting the. The cache block acquisition unit 139 reads the pixel values of the pixels constituting the cache block (1, 0) after reading each pixel of all the pixels constituting the cache block (0, 0) by repeating the above. . The cache block acquisition unit 139 reads pixel values of the cache blocks (2, 0) and (4, 0) in the same manner after reading the pixel values of the pixels constituting the cache block (1, 0). Thus, reading of the cache block is completed.

  As described above, according to the projector 100 in the present embodiment, the cache block specified by the miss hit request issued by the hit determination unit 131 is specified in the prefetch request issued by the prefetch request issuing unit 132. Since the priority is obtained from the frame buffer 150 over the cache block, the efficiency of the distortion correction processing can be improved. Specifically, the cache block required for reading the interpolation block to be read next is read from the frame buffer 150 in preference to the cache block required for reading the interpolation block to be read next, and the cache block storage unit By storing in 122, it is possible to avoid the continuation of the state in which the cache block necessary for reading the interpolation block is not stored in the cache block storage unit 122 and to improve the efficiency of reading the interpolation block. That is, as shown in FIG. 19, after the 11th interpolation block is read out, the cache designated by the miss-hit request to acquire the cache block necessary for reading out the next 12th interpolation block. The frame buffer is prioritized over the cache block (5, 6) designated by the prefetch request in order to acquire the cache block necessary for reading the 15th interpolation block after the next block (2, 7). By reading from 150, it is possible to read the interpolation block efficiently while suppressing the waiting time for block writing.

  According to the projector 100 in the present embodiment, the buffer read control unit 138 reads the prefetch requests stored in the prefetch request buffer 134 in the order in which they are stored, and when the mishit request is stored in the mishit request buffer 135. The cache block acquisition unit 139 reads the miss-hit request from the miss-hit request buffer 135 in preference to reading the pre-read request from the pre-read request buffer 134, and the cache block acquisition unit 139 reads the pre-fetch according to the order read by the buffer read control unit 138. Since the cache block specified in the request and the miss-hit request is acquired, the efficiency of the distortion correction processing can be improved. Specifically, the buffer read control unit 138 reads the prefetch request stored in the prefetch request buffer 134 and the mishit request stored in the mishit request buffer 135 from each according to one reading order. Therefore, the efficiency of the distortion correction process can be improved.

  According to the projector 100 in the present embodiment, when the position information included in the prefetch request and the miss hit request includes position information in which the coordinate positions in the row direction of the frame buffer 150 are equal to each other, these position information Since the cache blocks corresponding to each of these are continuously acquired from the frame buffer 150, the efficiency of the distortion correction processing can be improved. Specifically, the frame buffer 150 constituted by a DRAM has a feature that when reading data from a storage area, the reading speed in the Row direction is slower than the reading speed in the Column direction. That is, when a column address and a row address are specified for the frame buffer 150 and data stored at the specified position is read, the specified row is compared with a case where the specified column address is changed and data is read. It takes longer to read data when the address is changed. According to the projector 100 according to the present invention, when the position information included in the read request includes position information having the same coordinate position in the row direction of the frame buffer 150, the position information corresponds to the position information. By continuously acquiring cache blocks from the frame buffer 150, the number of times to change the Row address can be reduced. As a result, the time required for reading the cache block can be suppressed, so that the efficiency of the distortion correction processing can be improved.

  According to the projector 100 in the present embodiment, the cache block acquisition unit 139 determines the cache direction in the row direction (y direction) for a plurality of cache blocks having the same coordinate position in the row direction (y direction) and the reading order is continuous. The pixel values are continuously read out across the cache blocks for the pixels having the same coordinate position, and when the reading of the pixel values for one line in the cache block on the most downstream side in the column direction (x direction) is completed, the pixel values are returned. Since pixel values of pixels constituting one row on the downstream side in the direction (x direction) are read, it is possible to improve the efficiency of the distortion correction processing. Specifically, the cache block acquisition unit 139 continuously reads cache blocks having the same coordinate position in the row direction (y direction) in the prefetch request and the miss hit request read by the buffer read control unit 138. In such a case, when generating an address for acquiring the pixel value of each pixel constituting the cache block, for the pixels having the same Row address and different Column addresses, the addresses are continuously acquired. Is generated. Thereby, since the number of times of changing the Row address can be reduced, the efficiency of the distortion correction processing can be improved.

B. Second embodiment:
In the first embodiment, the prefetch request and the miss hit request are stored in different buffers, and the projector 100 in which the reading order is controlled by the buffer read control unit 138 has been described. In the second embodiment, the prefetch request is described. The projector 100 that stores the mishit requests in the same buffer and controls the order of reading by the buffer read control unit 138 by rearranging the stored prefetch requests and mishit requests will be described. Since the configuration of the projector 100 in the second embodiment is the same as that of the first embodiment except for the cache block control unit 121, the description thereof is omitted.

B-1. Cache block controller:
FIG. 23 is a functional block diagram showing the configuration of the cache block control unit 121 in the second embodiment. The cache block control unit 121 according to the second embodiment includes a read request buffer 234, a buffer management tag unit 136, a buffer state determination unit 137, a buffer read control unit 138, and a cache block acquisition unit 139. ing. Descriptions of the buffer management tag unit 136, the buffer state determination unit 137, the buffer read control unit 138, and the cache block acquisition unit 139 are omitted for the portions having the same functions and configurations as those in the first embodiment.

  The read request buffer 234 includes a storage area for storing a prefetch request issued from the prefetch request issuing unit 132 and a miss hit request issued from the hit determination unit 131. Each address in the storage area of the read request buffer 234 corresponds to the order of reading by the buffer read control unit 138. The buffer management tag unit 136 stores management information for managing read requests such as prefetch requests and miss hit requests stored in the storage area of the read request buffer 234. The read request buffer 234 corresponds to a “buffer unit” in the claims.

  When the buffer state determination unit 137 receives the prefetch request issued from the prefetch request issuing unit 132, the buffer state determination unit 137 stores the read state in each address of the read request buffer 234 so that the prefetch requests are read in the order of issue. In addition, when the buffer status determination unit 137 receives the miss hit request issued from the hit determination unit 131, the buffer status determination unit 137 receives the received miss hit at the address of the read request buffer 234 that is read before the previously stored prefetch request. Store the request. The specific contents when the prefetch request and the miss hit request received by the buffer state determination unit 137 are stored in the read request buffer 234 will be described later with reference to FIG. When the buffer state determination unit 137 stores the received prefetch request or mishit request in the read request buffer 234, the buffer state determination unit 137 updates the management information of the buffer management tag unit 136. The buffer state determination unit 137 corresponds to a “storage control unit” in the claims.

  The buffer read control unit 138 reads the prefetch request and the miss hit request stored in the read request buffer 234. The buffer read control unit 138 refers to the buffer management tag unit 136, reads out the prefetch request and the miss hit request in order according to the order of the addresses in the read request buffer 234, and stores the read prefetch request and the miss hit request in the cache block acquisition unit. To 139. The cache block acquisition unit 139 reads the cache block specified in the prefetch request and the miss hit request from the frame buffer 150 according to the order read by the buffer read control unit 138, and stores the cache block in the block area of the cache block storage unit 122. .

  FIG. 24 is an explanatory diagram for explaining the storage order of the prefetch request and the miss hit request by the buffer state determination unit 137. FIG. 24A corresponds to FIG. 17A and is an explanatory diagram showing a state in which a prefetch request is stored in the read request buffer 234. FIG. 24B corresponds to FIG. 17B and is an explanatory diagram showing a state where a miss hit request is stored in the read request buffer 234. FIG. 24C corresponds to FIG. 17C and is an explanatory diagram for explaining a state in which a miss hit request is being read. FIG. 24D corresponds to FIG. 17D and is an explanatory diagram for explaining a state in which a prefetch request is being read.

  When the prefetch request is issued by the prefetch request issuing unit 132, the buffer state determination unit 137 reads the read request so that the read request is read from the read request buffer 234 in the order in which the prefetch requests are issued, as shown in FIG. Stored in each address of the buffer 234. Note that when only the prefetch request is stored, the read request buffer 234 becomes full with a storage area that can store at least four miss hit requests. This is because four mishit requests can be stored even when the read request buffer 234 becomes full due to the prefetch request. The necessity of securing a storage area for four mishit requests is as described above with reference to FIG.

  As shown in FIG. 24B, when a prefetch request stored in the read request buffer 234 is being read by the buffer read control unit 138, a hit request is issued from the hit determination unit 131. The buffer state determination unit 137 stores the received miss-hit request at the address that is read with the highest priority in the read request buffer 234. In other words, the buffer state determination unit 137 stores the miss hit request at an address that is read out in preference to the previously stored prefetch request. In order to store the miss-hit request at the address that is read with the highest priority, the buffer status determination unit 137 moves to the address with the lowest priority in order from the pre-read request stored at the address that is read with the highest priority first. Let As a result, as shown in FIGS. 24C and 24D, when the buffer read control unit 138 reads the prefetch request or the miss hit request sequentially stored in the read request buffer 234 in accordance with the address, the read request buffer first. The ninth miss hit request is read in preference to the fifth to eighth prefetch requests stored in H.234.

  As described above, according to the projector 100 in the second embodiment, the distortion correction processing can be performed even if the buffer for storing the prefetch request and the buffer for storing the miss hit request are not provided. The efficiency can be improved. That is, even if the prefetch request and the miss hit request are stored in the same read request buffer 234, the cache block acquisition unit 139 is read next by rearranging the order in which the buffer state determination unit 137 is read. A cache block required for reading an interpolation block can be read from the frame buffer 150 in preference to a cache block required for reading an interpolation block to be read next time and stored in the cache block storage unit 122. Accordingly, it is possible to improve the efficiency of reading the interpolation block while suppressing the state where the cache block necessary for reading the interpolation block is not stored in the cache block storage unit 122.

  According to the projector 100 in the second embodiment, the buffer read control unit 138 improves the efficiency of the distortion correction processing even when the prefetch request and the miss hit request stored in the buffer are read according to one read order. Improvements can be made. In other words, even if the buffer state determination unit 137 stores the prefetch request and the miss hit request in the buffer according to one storage order, the same effect can be obtained. Even in this case, by rearranging the order in which the buffer state determination unit 137 is read out, the cache block acquisition unit 139 performs the interpolation in which the cache block necessary for reading the interpolation block to be read next is read from the next time onward. It can be read from the frame buffer 150 in preference to the cache block required for reading the block and stored in the cache block storage unit 122.

C. Variations:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

C1. Modification 1:
In the present embodiment, the cache block acquisition unit 139, for a plurality of cache blocks having the same row direction (y direction) and having a continuous read order, for each pixel having the same coordinate position in the row direction (y direction). Although pixel values are continuously read across blocks, even in the case where the reading order is continuous for cache blocks having the same coordinate position in the Row direction (y direction), the cache direction is changed in the Row direction (y direction). ), The pixel values of the pixels constituting one row on the most upstream side are read, and when the reading for one row is completed, the pixel values of the pixels constituting the second column in the Row direction (y direction) are read back. After the second cache block is read, the second cache block is read Out it may be configured to perform. Even in this case, after reading the first cache block, the bus right that controls the high-speed bus 102 is held without passing it to other functional units, and the second cache block is continuously held. By performing reading, the block write waiting time shown in FIG. 7 can be shortened, so that the efficiency of distortion correction processing can be improved.

C2. Modification 2:
In the second embodiment, when a hit request is issued from the hit determination unit 131, the buffer state determination unit 137 stores the received miss hit request at the address that is read with the highest priority in the read request buffer 234. As described above, when the hit determination unit 131 issues a miss-hit request, the buffer state determination unit 137 receives the received miss-hit request other than the address that is read with the highest priority in the read request buffer 234. It may be configured to store the address. For example, the buffer state determination unit 137 receives an address read continuously with a prefetch request for reading a cache block that specifies a coordinate position equal to the coordinate position in the row direction of the cache block specified by the received miss-hit request. The mis-hit request may be stored. Even in this case, the efficiency of the distortion correction processing can be improved.

C3. Modification 3:
In this embodiment, when a hit request is issued by the hit determination unit 131, the cache block specified by the issued miss-hit request is acquired in preference to the reading of the cache block specified by the prefetch request. Although described, the cache block acquisition unit 139 may be configured to continue reading the cache block specified in the prefetch request even after the hit determination unit 131 issues a miss hit request. . For example, when read-ahead requests that specify cache blocks having the same coordinate position in the Row direction are continuously read, the cache blocks specified by the miss-hit request are read out from a plurality of cache blocks specified by the read-ahead request. It may be configured to be performed after the completion.

C4. Modification 4:
The number of pixels of the frame buffer 150, the number of pixels of the cache block storage unit 122, the number of pixels of the cache block, and the number of pixels of the interpolation block (the number of pixels used for pixel interpolation) are not limited to the above-described embodiments, and are arbitrarily set. can do.

C5. Modification 5:
In this embodiment, the projector 100 modulates the light from the illumination optical system 190 using the transmissive liquid crystal panel unit 192, but is not limited to the transmissive liquid crystal panel unit 192. The light from the illumination optical system 190 is modulated using a micromirror device (DMD (registered trademark): Digital Micro-Mirror Device), a reflective liquid crystal panel (LCOS (registered trademark): Liquid Crystal on Silicon), or the like. You may make it the structure to carry out. Also, a CRT projector that projects an image on a small CRT (cathode ray tube) onto a projection surface may be used.

C6. Modification 6:
In the projector 100 according to the present embodiment, a part of the configuration realized by the hardware in the above embodiment may be replaced with software. Conversely, a part of the configuration realized by the software is replaced with the hardware. It may be replaced with wear.

C7. Modification 7:
The present invention can be realized in various modes, and can be realized by, for example, a projector television, a monitor, a block video storage device, a projection conversion processing device, an image processing device, or the like. Further, a data acquisition method, an image processing method, and a computer program for realizing the functions of these methods or apparatuses, a recording medium on which the computer program is recorded, and data embodied in a carrier wave including the computer program It can be realized in the form of a signal or the like.

DESCRIPTION OF SYMBOLS 100 ... Projector 102 ... High speed bus 104 ... Low speed bus 110 ... Video input part 112 ... IP conversion part 114 ... Resolution conversion part 116 ... Video composition part 120 ... Trapezoid distortion correction part 121 ... Cache block control part 122 ... Cache block memory | storage part 123 ... tag information storage unit for cache block 124 ... interpolation block reading unit 125 ... pixel interpolation unit 126 ... FIFO unit 127 ... register unit 128 ... control unit 129 ... coordinate conversion unit 130 ... filter coefficient calculation unit 131 ... hit determination unit 132 ... prefetching Request issuing unit 134 ... Prefetch request buffer 135 ... Miss hit request buffer 136 ... Buffer management tag unit 137 ... Buffer state determination unit 138 ... Buffer read control unit 139 ... Cache block acquisition unit 140 ... Liquid crystal panel drive unit 1 0 ... Frame buffer 160 ... high-speed bus controller 162 ... low-speed bus control unit 170 ... processor 180 ... imaging unit 182 ... sensor unit 190 ... illumination optical system 192 ... liquid crystal panel unit 194 ... projection optical system 234 ... read request buffer

Claims (5)

An image display device,
A frame video storage unit for storing video data representing a frame video;
A block video storage unit comprising a plurality of block areas for storing block video data composed of a predetermined number of pixels, and storing a part of the video data stored in the frame video storage unit as block video data in each block area When,
Using the block video data stored in each of the block areas, a plurality of corrected pixel data respectively representing a plurality of pixels constituting a corrected frame video obtained by correcting distortion of the frame video is generated. A correction processing unit;
A display unit for displaying the corrected frame image using the corrected pixel data generated by the correction processing unit;
Determining whether block video data necessary for the correction processing unit to generate first corrected pixel data included in the plurality of corrected pixel data is stored in a block area of the block video storage unit When the block video data is not stored in the block area of the block video storage unit, a determination unit that issues an acquisition request for acquiring the block video data;
The correction processing unit predicts block video data necessary for generating second corrected pixel data which is corrected pixel data generated after the first corrected pixel data, and the predicted block video If the data is not stored in the block area of the block video storage unit, a block video prediction unit that issues an acquisition request for acquiring the predicted block video data;
When an acquisition request is issued by the block video prediction unit, the block video storage unit acquires block video data specified in each acquisition request from the video data stored in the frame video storage unit in the order of issue When the acquisition request is issued by the determination unit, the block video data specified by the acquisition request is obtained from the block video data specified by the acquisition request issued by the block video prediction unit. A block video acquisition unit that preferentially acquires the video data from the video data. The image display device according to claim 1,
The block video acquisition unit
A first buffer unit that stores acquisition requests issued from the block video prediction unit in the order in which they are issued;
A second buffer for storing an acquisition request issued from the determination unit;
When the acquisition requests stored in the first buffer unit are read in the order in which they are stored, and the acquisition request is stored in the second buffer unit, priority is given to reading of the acquisition requests from the first buffer unit. A reading unit that reads out the acquisition request from the second buffer;
An image display apparatus comprising: an acquisition unit that acquires block video data specified in each acquisition request in the order read by the reading unit. The image display device according to claim 1,
The block video acquisition unit
A buffer unit for storing an acquisition request at each address of the storage area;
When the acquisition request issued by the block video prediction unit is received, the received acquisition request is stored at an address read after the acquisition request previously stored in the buffer unit, and the acquisition request issued by the determination unit A storage control unit that stores the received acquisition request at an address read earlier than the acquisition request issued by the block video prediction unit among the acquisition requests previously stored in the buffer unit;
An image display device comprising: an acquisition unit that sequentially reads out acquisition requests from the buffer unit in accordance with the addresses and acquires block video data specified in each acquisition request. A projector that projects and displays an image on a projection surface,
An image light output unit for generating and outputting image light representing the image;
A frame video storage unit for storing video data representing a frame video;
A block video storage unit comprising a plurality of block areas for storing block video data composed of a predetermined number of pixels, and storing a part of the video data stored in the frame video storage unit as block video data in each block area When,
Using the block image data stored in each of the block areas, a corrected frame image is formed by performing processing for correcting distortion of the image projected on the projection surface with respect to the frame image. A plurality of corrected pixel data respectively representing a plurality of pixels, and a correction processing unit that outputs the corrected pixel data to the video light output unit;
Determining whether block video data necessary for the correction processing unit to generate first corrected pixel data included in the plurality of corrected pixel data is stored in a block area of the block video storage unit When the block video data is not stored in the block area of the block video storage unit, a determination unit that issues an acquisition request for acquiring the block video data;
The correction processing unit predicts block video data necessary for generating second corrected pixel data which is corrected pixel data to be generated later by the first corrected pixel data, and the predicted block video If the data is not stored in the block area of the block video storage unit, a block video prediction unit that issues an acquisition request for acquiring the predicted block video data;
When an acquisition request is issued by the block video prediction unit, the block video storage unit acquires block video data specified in each acquisition request from the video data stored in the frame video storage unit in the order of issue When the acquisition request is issued by the determination unit, the block video data specified by the acquisition request is obtained from the block video data specified by the acquisition request issued by the block video prediction unit. A block video acquisition unit that preferentially acquires the video data from the video data. An image processing method in an image display device,
Storing video data representing a frame video;
Storing a part of the video data in a block area as block video data;
Using the block video data stored in the block area to generate corrected pixel data representing a corrected frame video that has been subjected to a predetermined correction on the frame video;
It is determined whether or not the block video data used to generate the first corrected pixel data is stored in the block area. If the block video data is not stored in the block area, the block video data is Issuing a first acquisition request for acquisition;
When block video data used to generate second corrected pixel data generated after the first corrected pixel data is predicted, and the predicted block video data is not stored in the block area, Issuing a second acquisition request for acquiring the predicted block video data;
When the second acquisition request is issued, the block video data specified in each acquisition request is acquired from the video data in the issued order and stored in the block area. When the first acquisition request is issued, Obtaining the block video data specified by the first acquisition request from the video data in preference to the block video data specified by the second acquisition request.

Images