JP2011205393A - Solid-state imaging apparatus, and method of driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that the power consumption of a drive circuit of an inputted counter data signal increases when a clock frequency is raised in a latch circuit with an SRAM structure or a DRAM structure, in a column-parallel AD conversion circuit constituted of a comparator and a latch circuit that takes a counter value therein.SOLUTION: An imaging apparatus has a latch circuit structure in which differential input transistors M11a and M21a to which differential data signals D1 and D1x are given and switching transistors M31a and M41a controlled by an output of a comparator are provided in series to each inverter of a latch circuit configured by two pairs of CMOS inverters with positive feedback constitution. In addition, a data signal amplitude is reduced.

Description

  The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device capable of reducing power consumption of a CMOS image sensor having a column parallel analog-digital conversion circuit (column parallel AD conversion circuit) and a driving method thereof. .

  A CMOS image sensor is known as a line sensor in which pixels are arranged in a one-dimensional manner or a two-dimensional area sensor in which pixels are arranged in a two-dimensional manner. In this CMOS image sensor, a peripheral circuit can be formed on the same chip, and a CMOS image sensor having a column parallel AD conversion circuit that is provided with an AD conversion circuit for each column and enables AD conversion in parallel in units of rows. Is realized.

  As a typical column parallel AD conversion circuit, a comparator compares a pixel signal with a reference signal linked to a counter value, and takes in a counter value when the comparator output is inverted by a multi-bit latch circuit, and latches it. A single slope AD conversion method has been developed in which data held in a circuit is a digital signal. In addition, as an application of the method, the AD conversion operation is performed twice for the reset signal in which the pixel is reset and the integration signal in which the photodiode signal is accumulated, and the difference between the two digital signals is obtained. A method has also been realized.

  As a latch circuit used in such an AD converter circuit, an SRAM (static random access memory) configuration latch circuit shown in FIG. 11A or a non-patent document 1 shown in FIG. A latch circuit having a DRAM (dynamic random access memory) configuration is known.

  In the circuits of FIGS. 11A and 11B, when the timing control terminal Cin connected to the comparator is an ON signal, the switch transistors M51, M52 or M61 are turned on, and are supplied from the data input terminals D and Dx. The state of the latch circuit is rewritten to the data signal, and the state when the timing control terminal Cin is inverted from the on signal to the off signal is maintained. Here, the data input terminal Dx represents an inverted signal of the data input terminal D.

The transistor M63 to which the control signal Sel is applied to the gate in FIG. 11B is selected when the held data is read, and data can be output from the data input terminal D to which the data input line is connected. The configuration of FIG. 11A can also be output from the data input terminals D and Dx.
However, when the same data signal line is shared for writing and reading, data reading cannot be performed simultaneously with AD conversion. Therefore, it is necessary to provide two sets of latch circuits and perform writing (AD conversion) and reading alternately. There is also known a configuration in which a latch circuit and a read circuit are provided separately, and data input signal lines and data output signal lines are separated.

  The comparator output connected to the timing control terminal Cin of the latch circuit is a step-like signal that is inverted from the on signal to the off signal. However, in the configuration shown in Patent Document 1, the D-type flip-flop is combined. The clock synchronous circuit converts the stepped comparator output waveform into a pulsed output waveform and applies it to the latch circuit. With this configuration, it is possible to shorten the time during which the timing control terminal Cin of the latch circuit is turned on.

JP 2000-349638

K. Findlater, R. Henderson, D. Baxter, JED Hurwitz, L. Grant, Y. Cazaux, F. Roy, D. Herault, and Y. Marcellier, "SXGA Pinned photodiode CMOS image sensor in 0.35μm technology," IEEE International Solid-State Circuits Conference, vol. XLVI, pp. 218-219, February 2003.

  In the single slope AD conversion method and the digital double sampling AD conversion method, the count value of the counter must be increased to increase the number of bits, and the clock frequency must be increased to perform AD conversion in the same time. There is. Furthermore, since the AD conversion time per row needs to be shortened as the number of pixel arrays increases, a higher clock frequency is required.

  When the clock frequency of the counter circuit is increased, there arises a problem that the power consumption of the driving circuit required for supplying the counter value with the input data signal to the latch circuit provided for each column increases. In particular, as the number of pixels increases, the parasitic capacitance that must be driven increases as the number of columns increases, so that the power consumption of the drive circuit becomes very large.

  In both of the latch circuits of FIGS. 11A and 11B, the switch transistors M51, M52, or M61 are turned on when the timing control terminal Cin is on, so that the input capacitances of the data input terminals D and Dx are large. Become.

  The input capacity of FIG. 11A is large because the input / output terminal of the CMOS inverter is connected to the data input terminal, and the through current of the CMOS inverter also flows whenever the data input is inverted. growing.

  In the dynamic type of FIG. 11B, the parasitic capacitance Cp must be increased to some extent in order to suppress the influence of the charge injection of the switch transistor M61, and the power consumption increases because the input capacitance increases.

  As described above, the latch circuits of FIGS. 11A and 11B have a problem that the input capacity of the data input terminal is large when the timing control terminal Cin is an ON signal, and the power consumption of the data signal driving circuit increases. . In addition, when the timing control terminal Cin is an ON signal and an OFF signal, the input capacitance of the data input terminal changes greatly. Therefore, the wiring delay time of the data signal line depends on the state of the timing control terminal Cin of the latch circuit provided on the same data line. Has the problem of changing.

  This problem of changing the wiring delay time of the data signal line is caused by the wiring delay in the case of a method in which a difference is obtained by two AD conversions of a pixel reset signal and an integration signal, such as a digital double sampling AD conversion method. There arises a problem that an error remains in a digital signal in which time fluctuations are differentiated.

  In the digital double sampling AD conversion method, not only the offset voltage variation of the column circuit, but also the delay time variation of the comparator, the wiring delay of the reference signal and the wiring delay of the counter data signal are corrected by the difference, so a high-speed clock can be used. It is said. However, if the wiring delay time of the data signal line is changed, it is difficult to increase the clock speed.

  Also, as shown in Patent Document 1, if the stepped comparator output is converted into a pulse shape and input to the timing control terminal Cin, the write state time of the latch circuit can be shortened. The increase time can be shortened and the fluctuation of the wiring delay time can be reduced. However, the higher the clock frequency, the higher the power consumption of the circuit that generates the pulse waveform and the more difficult it is to generate the pulse waveform with high accuracy. Therefore, the comparator output must be a step waveform at a high clock frequency. .

  When the clock frequency of the counter becomes high in this way, the comparator output must have a step waveform, and the latch circuit with the timing control terminal Cin turned on has a problem of increased current consumption of the drive circuit due to an increase in the input capacity of the data input terminal. It becomes. In addition, the input capacitance of the latch circuit changes depending on whether the timing control terminal Cin is on or off, and the wiring delay time of the data signal line changes, making it difficult to apply a high-speed clock frequency.

  In order to solve the above-described problems, the present invention has a matrix-like pixel array, reads signals of the pixel array in units of rows, and the voltage monotonously increases / decreases in conjunction with the pixel readout signal voltage and the counter value. In a solid-state imaging device in which an AD conversion circuit including a comparator for comparing a reference voltage and a multi-bit latch circuit for capturing and holding a counter value at a timing when the comparator is inverted is provided for each column The first and second data input terminals having a differential configuration in which the latch circuit per bit is connected to a timing control terminal to which the comparator output is connected and any one bit data signal of the counter value is connected. First and second transistors having a differential configuration in which the first and second data input terminals are connected to the gate and the source is connected to the first power source. And a first feedback circuit and a second feedback circuit configured in series between the first and second transistors and the second power source, each having one input terminal connected to the other output terminal. A CMOS inverter; a third transistor inserted in series in a series circuit comprising the first CMOS inverter and the first transistor; and a gate connected to the timing control terminal; and the second CMOS inverter And a fourth transistor having a gate connected to the timing control terminal, and an output terminal of the first CMOS inverter and the second power supply. A fifth transistor having a polarity opposite to that of the third transistor having a gate connected to the timing control terminal, and a second CMOS inverter A solid-state imaging device comprising a sixth transistor having a polarity opposite to that of the fourth transistor provided between an output terminal and the second power supply and having a gate connected to the timing control terminal It is said.

  In such a latch circuit configuration, only the gates of the first and second transistors are connected to the data input terminal, and the input capacitance can be minimized by minimizing the transistor size. The power consumption of the data signal line driving circuit can be reduced. Further, since the sources of the first and second transistors are always grounded, the input capacitance of the latch circuit is constant regardless of the state of the timing control signal, and the wiring delay time of the data signal line is also always constant. Therefore, the AD conversion error related to the wiring delay time of the data signal line can be accurately subtracted by a digital double sampling AD conversion method in which AD conversion is performed twice, and a high-speed clock frequency can be applied. It becomes.

  In the present invention according to claim 2, in the invention according to claim 1, the arrangement of the third and fourth transistors of the latch circuit per bit is, for example, the drains of the first and second transistors and the It is specified that each is provided between the first and second CMOS inverters.

  In the invention according to claim 2, it is desirable that the first and second transistors of the latch circuit per bit are shared by a plurality of columns of latch circuits provided on the same data input signal line. As a result, the number of input transistors connected on the data input signal line can be reduced and the input capacitance is reduced, so that the power consumption of the data signal line driving circuit can be further reduced.

  According to a fourth aspect of the present invention, in the first aspect of the present invention, the arrangement of the third and fourth transistors of the latch circuit per bit is different from the first and second CMOS inverters as another example. It is specified that each of the nMOS transistor, the pMOS, and the transistor is provided.

  5. The present invention according to claim 1, wherein a voltage amplitude of a data signal applied to the first and second data input terminals of the latch circuit is determined by a potential difference between the first and second power supplies. It is desirable that the amplitude be small. By reducing the amplitude in this way, the power consumption of the data signal line driver circuit can be further reduced.

  5. The present invention according to claim 1, wherein one input signal of the data signal input to the first or second data input terminal of the latch circuit is a fixed voltage and the other data It is desirable that the voltage amplitude of the signal is smaller than the potential difference between the first and second power sources. As a result, the data signal line drive circuit becomes one, so that the power consumption of the drive circuit can be further reduced.

  Since the input capacity of the latch circuit can be reduced, the power consumption of the data signal line driver circuit can be reduced. In addition, since the input capacitance of the data input terminal does not change depending on the state of the timing control terminal of the latch circuit, the wiring delay time of the data signal line is always constant and the wiring delay time can be easily corrected. It becomes possible to apply a frequency. Further, by reducing the amplitude of the data signal applied to the data input terminal, the power consumption of the drive circuit can be further reduced.

The circuit diagram of the latch circuit of a 1st embodiment to which the present invention is applied. 1 is a circuit diagram for two columns of a column AD conversion circuit having 2 bits of a latch circuit according to a first embodiment to which the present invention is applied; FIG. 6 is a circuit diagram of two columns of column AD conversion circuits each having 2 bits of a latch circuit according to a second embodiment to which the present invention is applied. The circuit diagram of the latch circuit of a 3rd embodiment to which the present invention is applied. The drive waveform of the data signal given to the data input terminal of the latch circuit which becomes 4th Embodiment to which this invention is applied. The drive waveform of the data signal given to the data input terminal of the latch circuit which becomes 5th Embodiment to which this invention is applied. 1 is a block diagram of a CMOS image sensor having a column parallel AD conversion circuit. The circuit diagram showing the pixel structure of a CMOS image sensor. The block diagram of a column parallel AD conversion circuit. 6 is a timing chart of a CMOS image sensor having a column parallel AD conversion circuit. The circuit diagram showing the example of the conventional latch circuit.

[First Embodiment]
First, the overall configuration of the solid-state imaging device according to the first embodiment to which the present invention is applied will be described. FIG. 7 is a block diagram of a CMOS image sensor having a column parallel AD conversion circuit to which the present invention is applied. For the pixels 101 arranged two-dimensionally, the pixel signal of the row selected by the row selection line 102 from the row selection circuit 104 constituted by a decoder or shift register is read out to the vertical readout line 103.

  The pixel signal output to the vertical readout line 103 is compared with a reference voltage provided by a reference voltage signal line 111 generated by a ramp signal generation circuit 108 by a comparator 106 provided for each column. This reference voltage has a waveform in which the voltage changes in conjunction with the counter value of the counter circuit 109. When the comparator 106 is inverted, that is, when the pixel signal matches the reference voltage, the counter value is the input data signal line. It is written and held in the latch circuit 107 via 112. When the counter value held in the latch circuit is selected by the column selection circuit 105, it is output as a digital signal via the output data signal line 113 and the sense amplifier circuit 110.

  FIG. 8 shows an example of the pixel indicated by 101 in FIG. The pixel includes a photodiode PD, a transfer transistor M71 that transfers a photoelectric conversion signal of the photodiode to a floating diffusion region (FD), a reset transistor M72 that resets the FD, and an amplification transistor M73 that amplifies and outputs the potential of the FD. And a row selection transistor M74 for connecting the amplified output signal to the vertical signal line 103. Here, the gates of the transistors M71, M72, and M74 are respectively connected to TX, RST, and READ that are control signal line groups constituting the row selection line 102 shown in FIG. 7, and as shown in the timing chart of FIG. Controlled.

  FIG. 9 shows a block diagram of a column AD conversion circuit composed of the comparator 106 and the latch circuit 107 of FIG. The comparator 106 is usually composed of a multi-stage amplifier, and in FIG. 9, it has a two-stage structure of amplifiers A1 and A2. A switch S1 controlled by a control signal RCOMP is provided between the input and output of the first stage amplifier A1, and the signal input terminal Vsig connected to the vertical signal line and the inverting input terminal of the amplifier A1 are connected via a capacitor C1. Has been. Further, the non-inverting input terminal of the comparator is connected to the reference voltage input terminal Vramp of the ramp waveform generating circuit 108 of FIG.

  The switch S1 and the capacitor C1 provided in the comparator 106 in FIG. 9 use the difference between the two readout signals of the reset signal immediately after resetting the pixel signal and the integration signal to which the photodiode signal is transferred to the comparator. It is provided for input. The configuration of the comparator 106 may be such that the switch S1 and the capacitor C1 are not provided, and the vertical signal line is directly connected to the comparator and the two readouts are AD-converted and then the difference is calculated with a digital signal. Is possible.

  The comparator output Cout is connected to the latch circuit 107. The latch circuit 107 is composed of a number of unit latch circuits corresponding to the number of bits of the counter value, and is indicated by 11-1, 11-2, and 11-3 for 3 bits in FIG. The counter value of the counter circuit 109 is given to each unit latch circuit via the data signal lines 112-1, 112-2, 112-3, and the respective data signals are represented as D1, D2, D3.

  The circuits shown in FIGS. 7, 8 and 9 operate according to the timing chart of FIG. In FIG. 10, T1 is a reset period, T2 is a first readout period, T3 is a pixel signal transfer period, and T4 is a second readout period. As indicated by Vsig, the pixel signal output is a reset signal output in the first readout period of T2, and the photodiode signal voltage in the negative direction with reference to the reset signal in the second readout period of T4. An integrated signal with Vs added is output. Therefore, the difference between the first and second readout signals is the photodiode signal voltage Vs integrated in the pixel.

  The switch S1 of the comparator 106 shown in FIG. 9 is turned on in the period T2, and the reset signal in the first reading period is sampled in the capacitor C1. In the second readout period T4, the photodiode signal voltage Vs is transmitted to the inverting input terminal of the amplifier A1 through the capacitor C1. In this state, the comparator output Cout is inverted when the reference voltage Vramp of the non-inverting input terminal is monotonously lowered to the same potential as the inverting input terminal. The data signal of the counter is given to the counter circuit 109 as indicated by D1, D2, and D3, and the data signal when the counter output Cout is inverted in response to the counter value sequentially in synchronization with a clock not shown in FIG. It is held in the latch circuit 107. This data signal becomes a digital signal corresponding to the photodiode signal voltage Vs.

  In this way, the AD conversion operation is performed. However, if the input capacity of the data input terminal of the latch circuit in FIG. 9 is large, the capacity of the data signal line increases, so that the drive circuit for driving the counter signals D1, D2, D3 There is a problem that power consumption increases. Therefore, in the present invention, the latch circuit shown in FIG. 1 is used to reduce the input capacitance of the data input terminal.

  FIG. 1 shows data input terminals D and Dx whose gates are connected to the data signal lines, and nMOS transistors M1 and M2 whose sources are connected to the first power supply VSS, and one input terminal via nMOS transistors M3 and M4. Is connected to the other output terminal in the basic configuration in which two sets of CMOS inverters INV1 and INV2 having a positive feedback configuration are provided, further between the output terminal Qx of the CMOS inverter INV1 and the second power supply VDD, and the CMOS. The pMOS transistors M5 and M6 are respectively provided between the output terminal Q of the inverter INV2 and the second power supply VDD.

  The gates of the transistors M3, M4, M5, and M6 are connected to the timing control terminal Cin to which the comparator output is connected. When the voltage of the timing control terminal Cin is VSS (Cin = 0), the transistors M3 and M4 are in the off state. The transistors M5 and M6 are turned on, and the output terminals Q and Qx of the CMOS inverters INV1 and INV2 are in a reset state in which the potential is the same as the power supply VDD.

  When the voltage of the timing control terminal Cin is VDD (Cin = 1), the transistors M3 and M4 are turned on, the transistors M5 and M6 are turned off, and the currents of the transistors M1 and M2 flow through the CMOS inverters INV1 and INV2. At this time, if the potential of the data input terminal D is larger than that of the data input terminal Dx, the current of the transistors M1 and M2 becomes lower than the potential of the output terminal Qx of the CMOS inverter INV1 because the current of the CMOS inverter INV1 becomes larger than INV2. The potential of the output terminal Q of the CMOS inverter INV2 increases. Since these inverters are positively fed back, a small potential difference is amplified, and finally the output terminal Qx becomes VSS (Qx = 0) and the output terminal Q becomes VDD (Q = 1). The output signals Q and Qx can be read by providing a read buffer circuit connected to the data output signal line.

  The latch circuit of FIG. 1 has a configuration in which the data input terminals D and Dx are connected only to the gates of the transistors M1 and M2, respectively, and the transistors M1 and M2 have no problem even if they have the minimum dimensions, so that the input capacitance can be reduced. Further, since the steady-state potential of both the sources and drains of the transistors M1 and M2 is VSS, the input capacitance of the gate is always constant and has no characteristics. In addition, since the magnitude of the current value of the transistors M1 and M2 only needs to be inverted by data input, the input signal amplitude at the data input terminal can be operated with a small amplitude that is larger than the offset voltage variation.

  FIG. 2 shows the connection of the input terminals of the latch circuit in the column parallel AD conversion circuit. FIG. 2 shows two columns of the column parallel AD conversion circuit with the latch circuit of FIG. 1 as 2 bits. The data signal lines of the counter are D1, D1x and D2, D2x having a differential configuration. The input signals of the first and second columns are Vsig1 and Vsig2, the comparators are 106-a and 106-b, respectively, and the comparator outputs of the first column are connected to the unit latch circuits 11-1a and 11-2a. The comparator outputs in the second column are connected to the unit latch circuits 11-1b and 11-2b. In each latch circuit, the data input transistors M11a and M11b are connected to the data signal line D1, the data input transistors M21a and M21b are connected to the data signal line D1x, the data input transistors M12a and M12b are connected to the data signal line D2, and the data input transistors M22a and M22b are connected. Are connected to the data signal line D2x, respectively. Note that the switch S1 and the capacitor C1 shown in FIG. 9 are omitted from the configuration of the comparator of FIG.

  In order to increase the resolution of the AD conversion circuit, the number of bits of the counter and the latch circuit may be increased. The read circuit for data held in the latch circuit is not shown in FIG. 2, but an SRAM or DRAM read circuit having a selection switch as shown in FIG. 11 is provided for each latch circuit to transfer the data signal. Then, reading may be performed.

  As can be seen from FIG. 2, since each data signal line is connected only to the gate of one transistor in each column, the gate size can be minimized, the capacity of the data signal line can be reduced, and the data signal driving circuit can be reduced in consumption. Electricity is possible. In addition, when the wiring resistance of the data signal line is large and the number of columns is large, the wiring delay depending on the arrangement of the columns becomes large. However, in the configuration of FIG. 2, the gate capacitance of the transistor connected to the data signal line is the comparator output. Therefore, it is easy to correct the error depending on the column arrangement due to the wiring delay. Therefore, it is possible to increase the resolution by applying a high clock frequency.

[Second Embodiment]
A circuit configuration that further reduces the capacitance of the data signal line and enables further reduction in power consumption of the drive circuit is shown in FIG. 3 as a second embodiment. The same components as those in FIG. 2 are given the same reference numerals.

  3 is different from the first embodiment of FIG. 2 only in that the transistors connected to the data signal line are shared in two columns. 2 is the transistor M11 in FIG. 3, the data signal line D1x is the transistor M21a, M21b in FIG. 3 and the data signal line D2 is the transistor M12a in FIG. , M12b in FIG. 3 and the data signal line D2x are changed in the latch circuit so as to share the two transistors M22a and M22b in FIG.

  Accordingly, the sources of the switch transistors M31a and M31b, M41a and M41b, M32a and M32b, and M42a and M42b are connected. For this reason, for example, the current of the differential transistors M11 and M22 flows in two rows of the latch circuits 11-1a and 11-1b when the switch transistor is turned on. Therefore, the data write operation is not affected at all. Even if two columns of comparators are simultaneously inverted, there is no problem if the differential current value for each column does not reverse with the data input terminal signal. .

  As can be seen from FIG. 3, the number of transistors in each data signal line is ½ when the input transistors are shared by two columns and becomes ¼ when the input transistors are shared by four columns, so that the capacity of the data signal line can be further reduced. In addition, lower power consumption is possible. Further, since the capacity of the data signal line is reduced, the wiring delay is also reduced. Even if the wiring delay becomes a problem, the input capacitance value of the latch circuit connected to the data signal line does not depend on the signal state of the comparator, as in the first embodiment, so that the error due to the wiring delay is corrected. It is easy.

[Third Embodiment]
As a third embodiment, FIG. 4 shows a configuration of a latch circuit different from FIG. The same components as those in FIG. 1 are given the same reference numerals. The only difference from FIG. 1 is that the transistors M3 and M7 and M4 and M8 are interchanged, respectively.

  Thus, the arrangement of the nMOS transistor M3 whose gate is connected to the timing control terminal Cin may be anywhere on the series circuit of the data input transistor M1 and the CMOS inverter INV1, or may be arranged between the transistor M1 and the first power supply VSS. Is possible.

  As described above, even if the arrangement of the switch transistors M3 and M4 is changed, the latch circuit of FIG. 4 has the same characteristics as the first embodiment, and each data signal line is connected only to the gate of one transistor in each column. Therefore, the gate size can be minimized, the capacity of the data signal line can be reduced, and the power consumption of the driving circuit can be reduced. Even if a wiring delay occurs, the delay time does not depend on the input signal of the timing control terminal Cin, so that it is easy to correct an error due to the wiring delay.

  The latch circuits shown in FIGS. 1, 2, 3 and 4 can operate similarly and have similar characteristics even when the polarity and power supply of the nMOS transistor and the pMOS transistor are switched.

[Fourth Embodiment]
In the embodiments described so far, the circuit configuration of the latch circuit has been described. However, it is possible to reduce the power consumption of the drive circuit by applying a drive method that reduces the amplitude of the data signal input to the latch circuit. is there. As a fourth embodiment, a driving method for reducing power consumption by reducing the amplitude of a driving circuit will be described with reference to a timing chart shown in FIG.

  FIG. 5 shows output signal waveforms for enabling the power consumption of the data signals D1, D2, D3 and their inverted signals D1x, D2x, D3x in the period T4 of the timing chart of FIG. Data signals D1, D2, and D3 are indicated by solid lines, and D1x, D2x, and D3x are indicated by broken lines. In FIG. 10, the counter signal is a binary code, but in FIG. 5, a gray code with a minimum frequency of inversion of the data signal is used. The counter signal driving circuit charges and discharges the signal line only when the signal is inverted and consumes power. Therefore, the power consumption can be reduced as compared with the binary code by using the Gray code.

  Further, as shown in FIG. 5, the voltage corresponding to 0 of the data signals 1 and 0 is Vos, the voltage corresponding to 1 is VDD, and the voltage of the 0 signal is higher than the power supply voltage VSS corresponding to the ground potential. . In a normal digital signal, the zero signal uses a full-scale amplitude as the ground potential, but the latch circuits shown in FIGS. 1, 2, 3 and 4 as the first, second and third embodiments In order to prevent malfunction due to variations in offset voltage as a data input signal, a full-scale signal amplitude is not necessarily required if the differential signal set is larger than the variation in offset voltage.

  Therefore, if the amplitude of the data input signal is reduced as shown in FIG. 5, the charge for charging / discharging the data signal line in the drive circuit when the data is inverted can be reduced in proportion to the amplitude. Thus, the application of the drive waveform with a small amplitude shown in FIG. 5 has an advantage that the power consumption of the drive circuit can be reduced.

[Fifth Embodiment]
FIG. 6 shows another signal waveform using a differential data signal set having a small amplitude as a fifth embodiment to which the present invention is applied. Data signals D1, D2, and D3 are indicated by solid lines, and their inverted signals D1x, D2x, and D3x are indicated by broken lines.

  In FIG. 6, the data signals D1, D2, and D3 have the same waveforms as those in FIG. 5, except that the inverted signals D1x, D2x, and D3x are substantially intermediate potentials between the voltage values of the 0 and 1 signals of the data signals D1, D2, and D3. The fixed voltage is. Even when such a non-symmetrical differential data signal set is used, the latch circuit shown so far can operate as long as the differential voltage set has a potential difference larger than the offset voltage variation.

  In the drive waveform shown in FIG. 6, one signal may be a fixed voltage, and the drive circuit can be reduced to half. Therefore, the application of the drive waveform shown in FIG. 6 has the advantage that the power consumption of the drive circuit can be further reduced.

11-1, 11-2, 11-3, 11-1a, 11-1b, 11-2a, 11-2b Unit latch circuit 101 Pixel 102 Row selection line 103 Column signal line 104 Vertical shift register 105 Horizontal shift register 106, 106-a, 106-b Comparator 107 Latch circuit 108 Ramp signal generation circuit 109 Counter circuit 110 Sense amplifier 111 Reference voltage signal line 112 Input data signal line 113 Output data signal line
M1, M2, M11a, M21a, M11b, M21b, M12a, M22a, M12b, M22b, M11, M12, M21, M22 Data input transistor
M3, M4, M5, M6, M31a, M41a, M31b, M41b, M32a, M42a, M32b, M42b, M51, M52, M61, M63 Switch transistor
M7, M8, M9, M10, M53, M54, M55, M56 CMOS inverter transistors
M62 Read transistor
INV1, INV2 CMOS inverter
PD photodiode
M71, M72, M73, M74 Pixel transistors
Vsig, Vsig1, Vsig2 Column signal line input port and input signal
Vramp Reference voltage terminal and reference voltage signal
VSS First power supply
VDD Second power supply
D, Dx, D1, D1x, D2, D2x, D3, D3x Data signal terminal and data signal
Cin timing control pin
Sel selection signal terminal
Q, Qx data signal output pin
S1 switch
C1 capacity
Cp parasitic capacitance

Claims (6)

A comparator having a matrix-like pixel array, reading out signals of the pixel array in units of rows, and comparing a readout signal voltage of the pixel with a reference voltage whose voltage monotonously increases or decreases in synchronization with a counter value; In a solid-state imaging device in which an AD conversion circuit including a plurality of bit latch circuits for capturing and holding a counter value at a timing at which the counter is inverted is provided for each column,
The latch circuit per bit includes a timing control terminal to which the comparator output is connected, and first and second data input terminals having a differential configuration to which any one bit data signal of the counter value is connected. The first and second transistors having a differential configuration in which the first and second data input terminals are connected to the gate and the source is connected to the first power source, the first and second transistors, and the second First and second CMOS inverters having a positive feedback configuration, each having one input terminal connected to the other output terminal, and the first CMOS inverter and the first CMOS inverter. A third transistor having a gate connected to the timing control terminal, a second CMOS inverter, and a second transistor. A gate connected between the output terminal of the first CMOS inverter and the second power source; and a fourth transistor having a gate connected to the timing control terminal. Connected to the timing control terminal, a fifth transistor having a polarity opposite to that of the third transistor, a gate provided between the output terminal of the second CMOS inverter and the second power source, and the timing control A solid-state imaging device comprising: a sixth transistor having a polarity opposite to that of the fourth transistor connected to a terminal.   The third and fourth transistors of the latch circuit per bit are provided between the drains of the first and second transistors and the first and second CMOS inverters, respectively. The solid-state imaging device according to claim 1, wherein   3. The solid state according to claim 2, wherein the first and second transistors of the latch circuit per bit are shared by a plurality of columns of latch circuits provided on the same data input signal line. Imaging device.   3. The third and fourth transistors of the latch circuit per bit are respectively provided between an nMOS transistor and a pMOS transistor that constitute the first and second CMOS inverters. Item 2. The solid-state imaging device according to Item 1.   5. The voltage amplitude of a data signal applied to the first and second data input terminals of the latch circuit is smaller than the potential difference between the first and second power supplies. The driving method of the solid-state imaging device according to any one of the above.   One input signal of the data signal input to the first or second data input terminal of the latch circuit is a fixed voltage, and the voltage amplitude of the other data signal is smaller than the potential difference between the first and second power supplies. The driving method of the solid-state imaging device according to any one of claims 1 to 4, wherein the amplitude is an amplitude.

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