JP2011199481A - Clock system - Google Patents

Abstract

A highly accurate clock signal is obtained from the output of a first oscillation circuit without waiting for the start of a second oscillation circuit.
A clock system includes a CR oscillation circuit, a crystal oscillation circuit, and a trimming circuit. The CR oscillation circuit 11 generates a clock CLK1 supplied to the internal circuit 17. The crystal oscillation circuit 12 is used for adjusting the oscillation frequency of the CR oscillation circuit 11. The trimming circuit 15 adjusts the oscillation frequency of the CR oscillation circuit 11 based on the detection result of the oscillation frequency difference between the CR oscillation circuit 11 and the crystal oscillation circuit 12.
[Selection] Figure 1

Description

  The present invention relates to a clock system including an oscillation circuit.

  In general, internal circuits such as a control circuit and a signal processor installed in devices such as a remote control device and AV-related products operate intermittently to reduce power consumption. When the operation of the internal circuit is stopped, the operation of the oscillation circuit that supplies a clock signal to the internal circuit is also stopped.

  However, it takes a finite time until the clock signal satisfying the desired quality is output after the start of the oscillation circuit. If only an oscillation circuit (crystal oscillation circuit) using a crystal resonator is used, a highly accurate clock signal can be finally obtained, but it takes time to stabilize the output. On the other hand, when a CR oscillation circuit is used instead of the crystal oscillation circuit, the rise to output stabilization is faster than that of the crystal oscillation circuit, but the oscillation accuracy (jitter and wander characteristics) is lower than that of the crystal oscillation circuit. There is.

  Therefore, Patent Document 1 discloses a technique that combines a crystal oscillation circuit and a CR oscillation circuit. Specifically, the clock system described in Patent Document 1 includes a crystal oscillation circuit and a CR oscillation circuit. The clock system described in Patent Document 1 selects a clock signal generated by a CR oscillation circuit that rises quickly and outputs it to an internal circuit at the time of startup immediately after the power is turned on. The clock system described in Patent Document 1 selects a clock signal generated by a crystal oscillation circuit with good oscillation accuracy after the output of the crystal oscillation circuit is stabilized, and outputs the selected clock signal to an internal circuit. Stops oscillation. That is, the clock system described in Patent Document 1 uses the CR oscillation circuit to output a clock at the time of startup immediately after turning on the power, and then switches from the CR oscillation circuit to the crystal oscillation circuit to output the clock.

JP-A-4-326802

  As described above, the oscillation frequency accuracy of the CR oscillation circuit is lower than that of the crystal oscillation circuit. Therefore, when the frequency accuracy of the CR oscillation circuit is not sufficient and a clock signal with higher accuracy is required, the technique of Patent Document 1 cannot be applied. In other words, if the quality of the output signal of the CR oscillation circuit immediately after turning on the power is not sufficient, the internal circuit (such as the control circuit) cannot start a desired operation unless the output of the crystal oscillation circuit is stabilized after all. There is a problem.

  The start-up time until the output of the crystal oscillation circuit is stabilized is about 4 ms. On the other hand, the operation time of the internal circuit that operates intermittently may be shorter than the startup time of the crystal oscillation circuit. For example, in a wireless key system of an automobile, the time required for transmitting key data is typically about 1 ms at most. However, transmission of key data cannot be started without waiting for activation of the crystal oscillation circuit. If the start-up waiting time of the crystal oscillation circuit can be shortened, the operation time of the system can be shortened and power saving can be achieved.

  The case where the above problem occurs is not limited to a clock system using a CR oscillation circuit and a crystal oscillation circuit in combination. That is, in a clock system that uses a first oscillation circuit with a relatively short start-up time but relatively low oscillation accuracy and a second oscillation circuit with a relatively long start-up time but relatively high oscillation accuracy Can be a broad problem. For example, a clock system that uses both an LC oscillation circuit and a crystal oscillation circuit may cause a problem. A clock system that uses a CR oscillation circuit or an LC oscillation circuit in combination with an oscillation circuit using another solid-state vibrator such as a ceramic vibrator may also cause a problem.

  A clock system according to one embodiment of the present invention includes first and second oscillation circuits and a trimming circuit. The first oscillation circuit generates a clock signal supplied to an internal circuit. The second oscillation circuit is used to adjust the oscillation frequency of the first oscillation circuit. The trimming circuit adjusts an oscillation frequency of the first oscillation circuit based on a detection result of an oscillation frequency difference between the first oscillation circuit and the second oscillation circuit.

  The clock system according to one aspect of the present invention described above refers to, for example, the detection result acquired at the past activation of the second oscillation circuit or the control value of the first oscillation circuit corresponding to the detection result. Thus, the first oscillation frequency may be adjusted when the first oscillation circuit is activated. Even if the oscillation frequency accuracy of the first oscillation circuit is lower than the oscillation frequency accuracy of the second oscillation circuit by using the stored past detection result or control value, the first oscillation circuit Without waiting for the start of the second oscillation circuit, the first clock signal generated by the first oscillation circuit can be quickly brought close to the desired accuracy. That is, since a highly accurate clock signal can be obtained using the first oscillation circuit without waiting for the start of the second oscillation circuit, a desired operation by the internal circuit (for example, transmission of key data in a wireless key system) Etc.) can be started immediately.

  According to the above-described aspect of the present invention, a highly accurate clock signal can be obtained from the output of the first oscillation circuit without waiting for the activation of the second oscillation circuit.

It is a block diagram which shows the structural example of the clock system concerning Embodiment 1 of this invention. FIG. 2 is a block diagram illustrating a specific configuration example of a part of the clock system illustrated in FIG. 1. 2 is a flowchart illustrating an example of a normal mode operation procedure of the clock system illustrated in FIG. 1. It is a flowchart which shows an example of the calibration mode operation | movement procedure of the clock system shown in FIG. 6 is a flowchart showing another example of the calibration mode operation procedure of the clock system shown in FIG. 1. FIG. 4 is a timing waveform diagram regarding a normal mode operation procedure shown in FIG. 3. FIG. 5 is a timing waveform chart relating to a normal mode operation procedure shown in FIG. 4. It is a block diagram which shows the structural example of the clock system concerning Embodiment 2 of this invention.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.

<Embodiment 1 of the Invention>
FIG. 1 is a block diagram illustrating a configuration example of a clock system 1 according to the present embodiment.
The clock system 1 includes two oscillation circuits, that is, a CR oscillation circuit 11 and a crystal oscillation circuit 12. The CR oscillation circuit 11 generates an operation clock CLK1 supplied to the internal circuit 17. On the other hand, the generated clock CLK2 of the crystal oscillation circuit 12 is not used as an operation clock for the internal circuit 17, but is used as a reference signal for calibration of the clock CLK1 (oscillation frequency correction). Below, each element shown in FIG. 1 is demonstrated in order.

  The CR oscillation circuit 11 oscillates the clock CLK1 with a configuration in which a CR circuit including a capacitor (C) and a resistor (R) is arranged in the feedback loop of the amplifier. The CR oscillation circuit 11 can change the oscillation frequency by changing at least one of the capacitance value and the resistance value. The crystal oscillation circuit 12 oscillates the clock CLK2 by the natural vibration of the crystal. The CR oscillation circuit 11 has a shorter start-up time required for the output to stabilize, compared to the crystal oscillation circuit 12, but the oscillation frequency accuracy is lower than that of the crystal oscillation circuit 12.

  The frequency difference detection circuit 13 detects the frequency difference between the two clock signals CLK1 and CLK2. The frequency difference detection circuit 13 may include, for example, two counters. The frequency difference can be detected by counting the number of pulses of CLK1 and CLK2 using these two counters and comparing the counter values.

  The storage circuit 14 holds the detection result obtained by the detection circuit 13. As the memory circuit 14, for example, a semiconductor memory element such as a register or a RAM (Read Only Memory) may be used. The storage circuit 14 may store a frequency difference detection result, for example, a counter value or a difference thereof, or may hold a control value for the CR oscillation circuit 11 determined according to the frequency difference detection result. The control value for the CR oscillation circuit 11 is a control value for the variable capacitor or variable resistance of the CR oscillation circuit 11.

  The trimming circuit 15 reads the detection result of the frequency difference between CLK1 and CLK2 held in the storage circuit 14 or a control value corresponding thereto, and controls the CR oscillation circuit 11 so that the oscillation frequency of CLK1 approaches CLK2.

  The oscillation control unit 16 intermittently activates the CR oscillation circuit 11 and the crystal oscillation circuit 12 in response to an external interrupt signal generated in response to the arrival of the operation start time by the timer and the user's button operation. In the present embodiment, the oscillation control unit 16 activates the CR oscillation circuit 11 and the crystal oscillation circuit 12 in either “normal mode (first operation mode)” or “calibration mode (second operation mode)”. Take control.

  In the calibration mode, both the CR oscillation circuit 11 and the crystal oscillation circuit 12 are activated, the frequency difference between CLK1 and CLK2 is detected, and a new detection result is held in the storage circuit 14. In contrast, the normal mode is an operation mode in which the CR oscillation circuit 11 is activated and the crystal oscillation circuit 12 is not activated. In the normal mode, the trimming circuit 15 corrects the frequency of the CR oscillation circuit 11 using the frequency difference between CLK1 and CLK2 held in the storage circuit 14 when the calibration mode has been executed in the past or a control value corresponding thereto. .

  For example, the oscillation control unit 16 may execute the calibration mode when the number of activations in the normal mode reaches a predetermined number, or when a predetermined time or more has elapsed since the previous calibration mode execution time. The power consumption of the clock system 1 can be reduced by reducing the number of executions of the calibration mode with the activation of the crystal oscillation circuit 12.

  The internal circuit 17 operates using the clock signal CLK1 generated by the CR oscillation circuit 11 as an operation clock. The internal circuit 17 is, for example, an MPU (Micro Processing Unit), an MCU (Micro Controller Unit), a DSP (Digital Signal Processing Unit), or a combination thereof.

  When the internal circuit 17 is an MPU, MCU, or the like, the oscillation control unit 16 may be disposed in the internal circuit 17 as shown in FIG. FIG. 2 is a block diagram illustrating a more specific configuration example of the CR oscillation circuit 11, the frequency difference detection circuit 13, the storage circuit 14, the trimming circuit 15, and the oscillation control unit 16 when the internal circuit 17 is an MCU. In the example of FIG. 2, the counter 170 included in the MCU 17 corresponds to the frequency difference detection circuit 13. Further, the register 171 or 172 corresponds to the memory circuit 14. The oscillation control unit 16 is realized by a program including an MCU 17 and a group of instructions related to oscillation control. Specifically, a program related to oscillation control is stored in the ROM 172 or the like, and the MCU 17 executes the program to control the operations of the CR oscillation circuit 11 and the crystal oscillation circuit 12 in the normal mode or the calibration mode. .

  2 includes a CMOS (Complementary Metal Oxide Semiconductor) inverter 110, a variable resistor R1, and a variable capacitor C1, and oscillates using the hysteresis characteristics of the CMOS inverter 110. The trimming circuit 15 in FIG. 2 includes a selection circuit 150. The selection circuit 150 operates according to the detection result of the frequency difference stored in the register 171 or the RAM 172 or a control value corresponding thereto, and switches the resistance value of the variable resistor R1 and the capacitance value of the variable capacitor C1.

  Subsequently, specific examples of the normal mode operation procedure and the calibration mode operation procedure will be described below with reference to the flowcharts of FIGS. FIG. 3 is a flowchart showing an example of the normal mode operation procedure of the clock system 1. In step S101, the oscillation control unit 16 starts activation of the CR oscillation circuit 11 in response to an external interrupt. In step S <b> 102, the trimming circuit 15 sets the oscillation frequency of the CR oscillation circuit 11 using the trimming data held in the storage circuit 14. Here, the trimming data means the detection result of the frequency difference between CLK1 and CLK2 or control corresponding thereto. In step S <b> 103, the clock CLK <b> 1 that has been calibrated with the trimming data is supplied to the internal circuit 17. In step S104, the internal circuit 17 operates using the clock CLK1 as an operation clock, and completes predetermined processing (for example, transmission of key data). In step S105, the oscillation control unit 16 stops the operation of the CR oscillation circuit 11 and shifts to the standby state.

  FIG. 4 is a flowchart showing an example of the calibration mode operation procedure of the clock system 1. 4, in step S201, the oscillation control unit 16 starts activation of the CR oscillation circuit 11 and the crystal oscillation circuit 12 in response to an external interrupt. Steps S202 to S204 are the same as steps S102 to S104 shown in FIG. In step S205, the frequency difference detection circuit 13 detects the frequency difference between CLK1 and CLK2 after the oscillation of the crystal oscillation circuit 12 is started (after the oscillation frequency is stabilized). In step S206, the frequency difference detection circuit 13 updates the trimming data by storing the newly obtained frequency difference detection result or the control value corresponding thereto in the storage circuit. In step S207, the oscillation control unit 16 stops the operations of the CR oscillation circuit 11 and the crystal oscillation circuit 12 and shifts to the standby state.

  FIG. 5 is a flowchart showing another example of the calibration mode operation procedure of the clock system 1. The procedure shown in FIG. 5 is preferably executed when the clock system 1 is powered on for the first time, that is, when the detection result by the frequency difference detection circuit 13 or the control value corresponding thereto is not stored in the storage circuit 14. In step S301, the oscillation control unit 16 starts activation of the CR oscillation circuit 11 and the crystal oscillation circuit 12 in response to an external interrupt. Steps S302 and S303 correspond to steps S205 and S206 in FIG. That is, in step S302, the frequency difference detection circuit 13 detects the frequency difference between CLK1 and CLK2 after the oscillation of the crystal oscillation circuit 12 is started (after the oscillation frequency is stabilized). In step S <b> 303, the frequency difference detection circuit 13 stores the obtained trimming data (frequency difference detection result or control value corresponding thereto) in the storage circuit 14. Steps S304 to S306 are the same as steps S202 to S204 in FIG. 4, and the calibration of the CR oscillation circuit 11 and the operation of the internal circuit 17 using the clock CLK1 as the operation clock are performed. In step S307, the oscillation control unit 16 stops the operations of the CR oscillation circuit 11 and the crystal oscillation circuit 12 and shifts to the standby state. Note that the oscillation of the crystal oscillation circuit 12 may be stopped immediately after the frequency difference is detected in step S302.

  Next, operations in the normal mode and the calibration mode will be described with reference to the timing waveforms in FIGS. FIG. 6 shows timing waveforms related to the normal mode operation shown in FIG. When the start signal (external interrupt) of FIG. 6A is given to the oscillation control unit 16, the standby signal (FIG. 6B) for the CR oscillation circuit 11 is canceled and CR oscillation starts (FIG. 6C). )). In the normal mode operation of FIG. 3, the crystal oscillation circuit 12 is not activated (FIG. 6 (d)). The internal circuit 17 performs a predetermined process (such as transmission of key data) using the operation clock CLK1 supplied from the CR oscillation circuit 11 (FIG. 6E).

  FIG. 7 shows timing waveforms related to the calibration mode operation shown in FIG. When the start signal (external interrupt) of FIG. 7A is given to the oscillation control unit 16, the standby signal (FIG. 7B) for the CR oscillation circuit 11 and the crystal oscillation circuit 12 is canceled, and CR oscillation starts quickly. (FIG. 7C). The internal circuit 17 performs a predetermined process (such as transmission of key data) using the operation clock CLK1 supplied from the CR oscillation circuit 11 (FIG. 7E). The crystal oscillation circuit 12 starts oscillating later than the CR oscillation circuit 11 (FIG. 7D), and the frequency difference between CLK1 and CLK2 is compared and trimming data is updated (FIG. 7E).

  As described above, the clock system 1 uses the trimming data (the detection result or control value of the frequency difference between CLK1 and CLK2) stored at the time of starting the crystal oscillation circuit 12 in the past, so that the crystal oscillation circuit 12 Without waiting for the activation of the clock CLK1, the clock CLK1 generated by the CR oscillation circuit 11 can be quickly brought close to the desired accuracy. That is, since the highly accurate clock CLK1 can be obtained using the CR oscillation circuit 11 without waiting for the crystal oscillation circuit 12 to be activated, a desired operation (for example, transmission of key data in the wireless key system, etc.) by the internal circuit 17 is performed. You can start quickly.

<Embodiment 2 of the Invention>
In the first embodiment of the invention, an example in which the CR controls the oscillation frequency by adjusting at least one of the variable capacitance and the variable resistance of the CR oscillation circuit 11 has been described. However, the power supply voltage of the CR oscillation circuit 11 also affects the CR oscillation frequency. In the present embodiment, an example will be described in which the output voltage of the regulator that supplies the power supply voltage to the CR oscillation circuit 11 is adjusted according to trimming data (the detection result or control value of the frequency difference between CLK1 and CLK2).

  Furthermore, the resistance value of the variable resistor included in the CR oscillation circuit 11 changes depending on the temperature. In other words, the oscillation frequency of the CR oscillation circuit 11 also changes according to the ambient temperature. Therefore, when the ambient temperature at the time of trimming data acquisition is different from the current ambient temperature, the trimming data held in the storage circuit 14 may not be an appropriate value. Therefore, in this embodiment, an example in which trimming data is corrected according to the ambient temperature will be described. The control of the CR oscillation frequency by the output voltage of the regulator and the correction of the trimming data based on the ambient temperature are not necessarily performed together, and only one of them may be performed.

  FIG. 8 is a block diagram showing a configuration example of a main part of the clock system according to the present embodiment, corresponding to FIG. The overall configuration of the clock system according to the present embodiment may be the same as that of the clock system 1 (for example, FIG. 1).

  In the example of FIG. 8, the oscillation control unit 16 is realized by a program including an MCU 17 and a group of instructions related to oscillation control. Specifically, a program related to oscillation control is stored in the ROM 172 or the like, and the MCU 17 executes the program to control the operations of the CR oscillation circuit 11 and the crystal oscillation circuit 12 in the normal mode or the calibration mode. .

  The regulator 152 supplies a power supply voltage to the CR oscillation circuit 11. The output voltage of the regulator 152 is changed according to the trimming data stored in the register 171 or the RAM 172 as the storage circuit 14.

  The temperature detection circuit 151 measures the ambient temperature. The measured ambient temperature is sent to the MCU 17 that functions as the oscillation control unit 16. The MCU 17 functioning as the oscillation control unit 16 refers to the temperature dependence characteristic of the resistance value of the variable resistor R1, and corrects the trimming data based on the difference between the ambient temperature at the time of acquiring past trimming data and the current ambient temperature. . The temperature dependence characteristic of the resistance value of the variable resistor R1 may be stored in advance in a memory (for example, ROM 172) accessible by the MCU.

<Other embodiments>
In the first and second embodiments described above, the example in which the oscillation frequency of the CR oscillation circuit 11 is brought close to the oscillation frequency of the crystal oscillation circuit 12 based on the frequency difference between CLK1 and CLK2 has been described. In other words, an example is shown in which the oscillation frequency of the CR oscillation circuit 11 is calibrated so that the frequency difference between CLK1 and CLK2 approaches zero. However, the oscillation frequency of the CR oscillation circuit 11 may be calibrated so that the frequency difference between CLK1 and CLK2 approaches a predetermined finite value. That is, the reference oscillation frequency of the CR oscillation circuit 11 and the crystal oscillation circuit 12 may not be the same.

  In the first and second embodiments described above, the clock system including the CR oscillation circuit 11 and the crystal oscillation circuit 12 has been described. However, the idea described in the first and second embodiments of the present invention may be applied to the case where another type of oscillation circuit is used. That is, the idea described in the first and second embodiments of the present invention is based on the first oscillation circuit having a relatively short start-up time but relatively low oscillation accuracy and a relatively long start-up time but relatively high oscillation accuracy. Therefore, the present invention can be widely applied to a clock system that uses a high second oscillation circuit. The idea described in the first and second embodiments of the present invention may be applied to, for example, a clock system that uses both an LC oscillation circuit and a crystal oscillation circuit, or a CR oscillation circuit or an LC oscillation circuit, a ceramic resonator, etc. You may apply to the clock system which uses together the oscillation circuit using another solid oscillator.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

DESCRIPTION OF SYMBOLS 1 Clock system 11 CR oscillation circuit 12 Crystal oscillation circuit 13 Frequency difference detection circuit 14 Memory circuit 15 Trimming circuit 16 Oscillation control part 17 Internal circuit 110 CMOS inverter 150 Selection circuit 151 Temperature detection circuit 152 Regulator 170 Counter 171 Register 172 RAM (Random Access Memory)
173 ROM (Read Only Memory)
R1 resistance C1 capacity

Claims (10)

A first oscillation circuit for generating a first clock signal supplied to the internal circuit;
A second oscillation circuit used to adjust the oscillation frequency of the first oscillation circuit;
A trimming circuit that adjusts the first oscillation frequency based on a detection result of an oscillation frequency difference between the first oscillation circuit and the second oscillation circuit;
A clock system comprising:   2. The trimming circuit adjusts the first oscillation frequency so that the first oscillation frequency of the first oscillation circuit approaches the second oscillation frequency of the second oscillation circuit. 3. Clock system. Both the first and second oscillation circuits are intermittently activated,
The trimming circuit refers to the detection result obtained when the second oscillation circuit was activated in the past or a control value of the first oscillation circuit corresponding to the detection result, thereby the first oscillation circuit. 3. The clock system according to claim 1, wherein the first oscillation frequency is adjusted at the time of starting up. A storage circuit capable of storing at least one of the detection result and the control value;
The trimming circuit refers to the detection result or the control value held in the storage circuit when the second oscillation circuit is activated in the past, so that the first oscillation circuit is activated when the first oscillation circuit is activated. The clock system according to claim 3, wherein the oscillation frequency is adjusted. The clock system is operable in normal mode and calibration mode;
In the normal mode, at least the first oscillation circuit is activated, and by referring to the detection result or the control value held in the storage circuit when the second oscillation circuit has been activated in the past, the first oscillation circuit is referred to. The first oscillation frequency is adjusted at the time of starting the oscillation circuit of
In the calibration mode, both the first and second oscillation circuits are activated, and a new detection result obtained by detecting the oscillation frequency difference after activation of the first and second oscillation circuits or corresponding to this The clock system according to claim 4, wherein the control value to be stored is stored in the storage circuit for the next operation in the normal mode. Further equipped with a temperature detection circuit for detecting the ambient temperature,
The trimming circuit corrects a control amount for the first oscillation circuit determined by the detection result or the control value held in the storage circuit according to the ambient temperature. The clock system described in the section. An operating voltage can be supplied to at least the first oscillation circuit, and further includes a variable regulator capable of changing the operating voltage,
7. The operating voltage according to claim 1, wherein the operating voltage is adjusted based on a detection result of the oscillation frequency difference so that the first oscillation frequency approaches the second oscillation frequency. Clock system.   The clock system according to any one of claims 1 to 7, wherein the clock signal supplied to the internal circuit is not switched between the first clock signal and the second clock signal.   The clock system according to any one of claims 1 to 8, wherein the first oscillation circuit has a shorter start-up time and lower oscillation frequency accuracy than the second oscillation circuit. The first oscillation circuit is a CR oscillation circuit or an LC oscillation circuit,
The clock system according to claim 1, wherein the second oscillation circuit is a crystal oscillation circuit or a ceramic oscillation circuit.

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