JP2011197870A - Programmable device mounting apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable device mounting apparatus for easily restoring a device without separation from a network even when writing is unsuccessfully performed in remote update of logic.SOLUTION: A CPU 1 writes update data of a FPGA 5 remotely transmitted from a LAN via an interface 4 into an SDRAM 2, subsequently writes the update data stored in the SDRAM 2 into a backup flash memory 7, and then writes the update data stored in the SDRAM 2 into a flash memory 6 being the memory for storing the update data of the FPGA 5. When writing the update data into the flash memory 6 is unsuccessfully performed, the CPU 1 writes the update data stored in the flash memory 7 into the flash memory 6.

Description

  The present invention relates to a programmable device mounting apparatus for remotely updating the logic of a programmable device such as a field programmable gate array (FPGA).

As a conventional method of remotely updating the logic of the FPGA, the CPU, the volatile memory, the nonvolatile memory, the FPGA and the FPGA data storage memory are connected by a local bus, and the logic update data is transferred to the FPGA by LAN communication or the like. There was a method of remotely writing to the data storage memory. (See Patent Document 1)
At this time, the CPU that has received an instruction to write to the FPGA data storage memory temporarily stores the FPGA update data received from the LAN communication in the volatile memory. Next, the CPU writes the FPGA update data stored in the volatile memory into the FPGA data storage memory. Finally, the CPU executes a device reboot (restart) command, and the update data is configured from the FPGA data storage memory to the FPGA at the next startup.
With this FPGA update method, local shipping devices connected via a network can be updated with logic by remote writing. Therefore, all shipping devices can be pulled up to write logic at the factory, No need to write.

Japanese Patent Laying-Open No. 2005-258996 (pages 5-7, FIG. 1)

In the conventional remote maintenance method, when the device is unexpectedly turned off at the site while the update data is being written, the update data write fails, and the device does not start up properly at the next startup. Depending on the configuration, the device could be disconnected from the network.
In such a case, since access is impossible remotely, it is necessary to pull up the device and write logic at the factory, or to write at the site, which increases cost and time.
For this reason, when logic writing fails, it is necessary to be able to easily perform writing again remotely.

  The present invention has been made to solve the above-described problems, and even when update data writing to the programmable device fails when the logic is updated remotely, the device is not disconnected from the network and can be easily recovered. It aims at obtaining the programmable device mounting apparatus which enabled it.

  The programmable device mounting apparatus according to the present invention is a programmable device mounting apparatus in which a programmable device is connected to a local bus connected to a network, the programmable device data being connected to the local bus and configured as a programmable device. When the update data for the programmable device is transmitted via the network, the second nonvolatile memory that is connected to the local bus and stores the backup data for the programmable device data. A CPU that writes the update data to the second nonvolatile memory and then writes the update data to the first nonvolatile memory. If the CPU fails to write the update data to the first nonvolatile memory, 2 It is intended to write the update data stored in the volatile memory to the first non-volatile memory.

  As described above, the present invention is a programmable device mounting apparatus in which a programmable device is connected to a local bus connected to a network, and the programmable device data connected to the local bus and configured in the programmable device is obtained. First nonvolatile memory to store, second nonvolatile memory connected to the local bus and storing backup data for programmable device data, when update data for programmable device is transmitted via the network, A CPU that writes the update data to the second nonvolatile memory and then writes the update data to the first nonvolatile memory is provided. When the CPU fails to write the update data to the first nonvolatile memory, the second data Stored in non-volatile memory Since writing new data into the first non-volatile memory, even if the write to the first non-volatile memory fails, device is not disconnected from the network, it is possible to easily recover.

It is a block diagram which shows the FPGA mounting apparatus by Embodiment 1- Embodiment 3 of this invention. It is a flowchart which shows the procedure of the remote maintenance system of the FPGA mounting apparatus by Embodiment 1 of this invention. It is a figure which shows the write-in path | route 1 of the FPGA mounting apparatus by Embodiment 1 of this invention. It is a figure which shows the write-in path | route 2 of the FPGA mounting apparatus by Embodiment 1 of this invention. It is a figure which shows the write-in path | route 3 of the FPGA mounting apparatus by Embodiment 1 of this invention. It is a figure which shows the write-in path | route at the time of the write-in failure of the FPGA mounting apparatus by Embodiment 1 of this invention.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an FPGA mounting apparatus according to Embodiment 1 of the present invention.
In FIG. 1, the CPU 1 controls the entire FPGA mounting apparatus 10 (programmable device mounting apparatus) and writes update data for updating the logic of the FPGA. The SDRAM 2 is a volatile memory used by the CPU 1. The flash memory 3 is a non-volatile memory in which software executed by the CPU 1 is stored. The interface 4 is connected to a LAN, a dedicated line, or another network.
The FPGA 5 (programmable device) configures (downloads) logic data when activated and operates according to the logic. The flash memory 6 (first non-volatile memory) is a non-volatile memory for storing update data of the logic of the FPGA 5, and the FPGA 5 configures the update data stored in the flash memory 6 at startup.
The flash memory 7 (second non-volatile memory) is a non-volatile memory that temporarily stores update data for backup of update data of logic of the FPGA 5.

Next, the configuration of the present invention will be described in more detail.
The CPU 1, SDRAM 2, flash memory 3, interface 4, FPGA 5, flash memory 6, and flash memory 7 are connected via a local bus to form an FPGA-equipped device 10, and LAN communication (network communication) via the interface 4 allows local bus Can be accessed remotely.
When the CPU 1 receives a write instruction and update data remotely from the interface 4, the CPU 1 controls the write procedure and instructs the write again when the write fails. The SDRAM 2 temporarily stores update data of the logic of the FPGA 5 received from the LAN communication. The flash memory 3 is also used as a memory for writing data of the CPU 1, and is used for storing logs in the present invention.
The FPGA 5 configures logic data from the flash memory 6 when the FPGA-equipped device 10 is activated, and activates it. The flash memory 6 is a memory for storing logic data of the FPGA 5. The flash memory 7 is a backup memory for the flash memory 6, and stores the logic update data of the FPGA 5 before the flash memory 6.

  FIG. 2 is a flowchart showing the procedure of the remote maintenance method for the FPGA-equipped device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing the write path 1 of the FPGA-equipped device according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a write path 2 of the FPGA-equipped device according to the first embodiment of the present invention, and shows a path following FIG.
FIG. 5 is a diagram showing the write path 3 of the FPGA-equipped device according to the first embodiment of the present invention, and shows the path following FIG.
FIG. 6 is a diagram showing a write path when writing fails in the FPGA-equipped device according to the first embodiment of the present invention.

Next, the procedure of the remote maintenance method according to the first embodiment will be described with reference to FIG.
In remote maintenance, the FPGA-mounted device 10 is accessed through LAN communication, an instruction to write FPGA logic data is given to the CPU 1 by a specific command or the like, and update data is transmitted.
2, the CPU 1 monitors data received from the LAN communication via the interface 4 and receives a write instruction to the flash memory 6 that is a data storage memory of the FPGA 5.
In step S2, the CPU 1 temporarily stores, in the SDRAM 2, the logic update data of the FPGA 5 received from the LAN communication via the interface 4 as shown in FIG.
Next, in step S3, the CPU 1 writes the logic update data of the FPGA 5 stored in the SDRAM 2 into the flash memory 7, as shown in FIG.

After writing to the flash memory 7, in step S4, the CPU 1 writes the logic update data of the FPGA 5 stored in the SDRAM 2 to the flash memory 6, as shown in FIG. At this time, a bit indicating that writing is in progress is provided in the flash memory 3, and that bit is set to 1 during writing. When writing is completed, the bit is set to 0.
After the write to the flash memory 6 is completed, after confirming 0 of the bit, in step S5, the CPU 1 performs a reboot process (reboot) of the FPGA-equipped device 10, and after the FPGA-equipped device 10 is rebooted, The FPGA 5 performs configuration from the flash memory 6 in which the update data is written. The remote updater confirms that the FPGA 5 has started up with the new version, and finishes the remote update operation.

Next, the operation when writing fails will be described.
As shown in FIG. 3, when the logic update data of the FPGA 5 received from the LAN communication is being written to the SDRAM 2 and the writing fails due to the power-off of the FPGA-equipped device 10 or the like, the next time the FPGA-equipped device 10 is started, Data that was being written to the SDRAM 2 is erased, and the FPGA 5 configures the data from the flash memory 6 that stores the previous version of the data.
Therefore, since the FPGA-equipped device 10 starts normally and is not disconnected from the network, the remote updater confirms that the FPGA 5 is not updated data, and again writes the updated data remotely. Can do.

  Similarly, as shown in FIG. 4, if the writing fails while the update data stored in the SDRAM 2 is being written to the flash memory 7, the FPGA 5 stores the flash memory storing the previous version data when the FPGA-equipped device 10 is started next time. Data is configured from the memory 6. Therefore, since the FPGA-equipped device 10 starts normally and is not disconnected from the network, the remote updater can confirm that the FPGA 5 is not updated data, and can remotely perform writing again. .

Next, as shown in FIG. 5, if the writing fails while the update data stored in the SDRAM 2 is being written to the flash memory 6, incorrect data is configured in the FPGA 5 at the next startup of the FPGA-equipped device 10. The FPGA mounting device 10 does not start up normally.
Depending on the network configuration, if access to the FPGA 5 fails several times, the CPU 1 may be disconnected from the network and cannot be accessed remotely. However, the access to the FPGA 5 fails after the FPGA-equipped device 10 is activated. When the CPU 1 confirms the bit being written in the flash memory 3 and confirms that it is 1, the update data of the logic of the FPGA 5 stored in the flash memory 7 is transferred to the flash memory 6 as shown in FIG. Write.
After the writing is completed, the bit is set to zero, the CPU 1 performs a reboot process, and the FPGA 5 configures the update data from the flash memory 6, so that the FPGA-mounted device 10 is restored and the logic update data is transferred to the FPGA-mounted device 10. Can write.

Note that if the logic update data of the FPGA 5 stored in the flash memory 7 is also in an error state, the flash memory 7 is rewritten remotely.
In addition, a bit indicating that writing to the flash memory 7 is being performed may be set to 1 during writing and set to 0 when writing is completed. In this way, the same control as that of the flash memory 6 can be performed for writing to the flash memory 7.

  According to the first embodiment, as described above, even if writing fails during remote logic data update, the FPGA-equipped device is prevented from being disconnected from the network, and the FPGA-equipped device is automatically restored or remotely You can write again.

Embodiment 2. FIG.
In the first embodiment, the flash memory 7 is not used when the logic data of the FPGA 5 is not updated remotely. For this reason, in the second embodiment, the flash memory 7 is shifted to a standby mode other than the normal mode or the like by the CPU until a data write instruction is received by LAN communication. In the standby mode, the flash memory 7 cannot be written or read.

  According to the third embodiment, this can save power and prevent erroneous writing from the flash memory 7 to the flash memory 6.

Embodiment 3 FIG.
If the local bus is configured as in the first embodiment, illegal data may be generated due to bit corruption of the flash memory 6. In this case as well, the FPGA-equipped device 10 cannot be activated. The third embodiment is for countermeasures in this case.

Next, the operation will be described.
As shown in FIG. 1, when the logic data stored in the normal flash memory 6 becomes illegal data due to bit corruption or the like, the illegal logic data is configured in the FPGA 5 when the FPGA-equipped device 10 is started up. The FPGA 5 cannot be accessed, resulting in an abnormal state in which the FPGA-equipped device 10 needs to be disconnected from the network.
In the third embodiment, when the CPU 1 accesses the FPGA 5 several times after the activation of the FPGA-equipped device 10 and the access fails, as shown in FIG. 6, the logic update data of the FPGA 5 stored in the flash memory 7 Is rewritten to the flash memory 6.
After the writing is completed, the CPU 1 performs a reboot process, and the FPGA 1 configures normal data from the flash memory 6 the next time the FPGA-equipped device 10 is activated.

  According to the third embodiment, as described above, in the configuration of FIG. 1, even when the flash memory 6 becomes invalid data due to bit corruption or the like, the logic update data of the FPGA 5 stored in the flash memory 7 is By rewriting to the flash memory 6, the FPGA-mounted device can be recovered from the abnormal state.

1 CPU
2 SDRAM
3 Flash memory 4 Interface 5 FPGA
6 Flash memory (for FPGA data storage)
7 Flash memory (for FPGA data storage and backup)

Claims (3)

A programmable device mounting apparatus in which a programmable device is connected to a local bus connected to a network,
A first non-volatile memory connected to the local bus and storing data for a programmable device configured in the programmable device;
A second non-volatile memory connected to the local bus and storing backup data of the programmable device data;
When update data for the programmable device is transmitted via the network, the CPU includes a CPU for writing the update data to the second nonvolatile memory and then writing the update data to the first nonvolatile memory.
If the CPU fails to write the update data to the first nonvolatile memory, the CPU writes the update data stored in the second nonvolatile memory to the first nonvolatile memory. Programmable device mounting apparatus characterized by this.   2. The programmable device mounting apparatus according to claim 1, wherein the CPU shifts the second nonvolatile memory to a mode other than the normal mode when the update data is not written. The CPU writes the update data stored in the second non-volatile memory into the first non-volatile memory when the update data stored in the first non-volatile memory is illegal data. The programmable device mounting apparatus according to claim 1 or 2, wherein the apparatus is mounted.

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