JP2011187683A - Wiring board and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration of signal transmission characteristics due to plating stub wiring without restriction by signal wiring layout.
A wiring board includes a signal wiring layer and a ground or power plane that is adjacent to the signal wiring layer with an insulating layer interposed therebetween. The signal wiring layer 130 includes a plurality of signal wirings 132 electrically connected to the electrode pads 111 a of the semiconductor element 111 and a plurality of plating stub wirings 133 connected to the plurality of signal wirings 132. The ground or power plane 140 has an opening 145 opposite to the starting point of each plating stub wiring that is a connection portion of each plating stub wiring 133 with the signal wiring 132, and the plating stub wiring 133 at that portion is formed. Increase characteristic impedance.
[Selection] Figure 6

Description

  The present invention relates to a wiring board having a plated stub wiring and a semiconductor device.

  In recent years, in the field of semiconductor devices, for example, an opportunity to use a BGA (Ball Grid Array) package using a wiring board such as a printed board instead of a package using a lead frame such as QFP (Quad Flat Package) has increased. Yes.

  FIG. 1 shows a schematic configuration of a typical BGA type semiconductor device 10. A semiconductor element 11 is mounted on a wiring board (package board) 20 via an adhesive layer 15, and electrode pads of the semiconductor element 11 are connected to bonding pads of the wiring board 20 by metal wires 12. The semiconductor element mounting surface side of the wiring board 20 is covered with the mold resin 13 so as to seal the semiconductor element 11 and the metal wire 12. Although a configuration using wire bonds for connecting electrodes of a semiconductor element is shown here, a configuration in which bumps are formed on the surface of the semiconductor element and flip-chip mounting is also used. The wiring board 20 has a plurality of bonding pads and signal wirings communicating with the bonding pads on the semiconductor element mounting surface, and an arrayed ball pad for mounting the solder balls 14 on the opposite surface. Each signal wiring and the corresponding ball pad are electrically connected by a through via 82.

  Typically, copper (Cu), which is a low resistance metal, is used for the bonding pad, signal wiring, and ball pad. Often, nickel (Ni) / gold (Au) plating is applied to the Cu surface of the ball pad. Since a thermal process is performed when the semiconductor element 11 is mounted and sealed with the mold resin 13, the surface is oxidized when Cu is exposed, and a problem such as a ball not being attached occurs when the solder ball 14 is mounted. Although Au is difficult to oxidize, this problem can be prevented. Similarly, a bonding pad that is wire-bonded to the semiconductor element 11 also requires Au on the surface for connection to the Au wire 12. Also, in the case of flip chip connection, Au is often required on the surface. When electroless plating is used, problems such as ball peeling occur due to problems such as aggregation of phosphorus (P) contained in the electroless Ni plating solution and oxidation of the underlying Ni from the porous (pinhole) portion of Au. It has been reported to obtain. Therefore, from the viewpoint of the bonding strength of the solder balls 14, electrolytic plating is required rather than electroless plating.

  In electrolytic plating, it is necessary to electrically connect each pad to a plating terminal and connect the terminal to a plating jig. Therefore, in addition to the signal wiring required for the semiconductor device, additional wiring for plating is provided. Here, the manufacture of the wiring board is not generally performed for each individual package substrate, but is performed in a large format so that a large number can be obtained.

  FIG. 2 shows, as an example, additional wiring for electrolytic plating for a large substrate 20 ′ including four package substrates 20. FIG. 3 shows one package substrate 20 cut out from the large substrate 20 ′ together with the semiconductor element 11 mounted and wire-bonded after the plating process.

  The signal wiring 32 of each package substrate 20 extends to the position of the corresponding via 82 on the semiconductor element mounting surface of the package substrate 20. A wiring referred to as a plating stub wiring 33 is provided that starts from the position of the via 82 and communicates with each signal wiring 32. Each plating stub wiring 33 extends to the plating wiring 21 that electrically connects all the plating stub wirings 33 of the four package substrates 20. The plating wiring 21 may have a widened plating terminal 22. The plating wiring 21 is not included in the package substrate 20 after being singulated because it is cut out as an individual package substrate 20 and formed outside the region that defines the outer size. However, if a part of each plating stub wiring 33 is not removed, it will remain on the package substrate 20 and in the semiconductor device 10 (FIG. 1). The plating stub wiring 33 communicated with the signal wiring 32 functions as an antenna, and degrades signal transmission characteristics due to signal reflection and / or resonance. This is a factor that hinders further speeding up of the semiconductor device, such as limiting the signal frequency usable in the semiconductor device to less than the resonance frequency.

  The plating stub wiring 33 can be removed by etching after the plating process, for example. However, this requires a process of forming a resist pattern that covers portions other than the plating stub wiring, removing the plating stub wiring by etching, and then stripping the resist, resulting in an increase in manufacturing cost. Even when other methods are used to remove the plating stub wiring 33, an increase in manufacturing cost cannot be avoided.

  Therefore, there has been proposed an attempt to suppress the influence of the plating stub wiring on the signal transmission characteristics without requiring an additional process for removing the plating stub wiring. As an example, a technique is known in which the signal wiring is formed so as to pass through the vicinity of the outer peripheral portion of the package substrate and the length of the plating stub wiring is shortened. As another example, in a package substrate having a microstrip line configuration, a ground and power plane are not formed in a region outside the outermost peripheral via, and a parasitic capacitance between the plated stub wiring and the plane in the region is not formed. There is also known a technique for eliminating the above.

  In a package substrate having a stripline or microstripline configuration, a grid-like opening may be provided in the ground and power plane. The opening prevents the gas generated from the insulating layer components during the firing of the ceramic substrate and the resin curing of the organic substrate and prevents the gas from being trapped under the plane and causing the plane to swell and peel off. Is to do. In such a configuration where the plane has an opening, impedance mismatch occurs in the signal wiring portion facing the opening in the signal wiring layer adjacent to the plane layer. In order to suppress this impedance mismatch, a method has been proposed in which an opening is not provided in the plane region facing the signal wiring.

JP 2000-269379 A JP-A-6-204357 Japanese Patent Laid-Open No. 10-173087 JP 2003-224227 A JP 2003-17618 A

  However, the known technique for suppressing the influence of the plating stub wiring on the signal transmission characteristics without removing the plating stub wiring has the following problems. Forming the signal wiring so as to pass through the vicinity of the outer periphery of the package substrate increases the signal density and increases the wiring density, thereby losing the flexibility of the wiring layout and reducing the number of wirings and thus the number of terminals of the semiconductor device. This hinders the increase. In addition, the fact that the ground and power planes are not formed in the outer region of the outermost peripheral via has a problem that, for example, the longer plating stub wiring extending from the inner peripheral via, which is originally a problem, is less effective. There are limitations on the applicable signal wiring layout.

  Therefore, there is a demand for a technique that can be applied to a wide range of signal wiring layouts and that suppresses deterioration in signal transmission characteristics due to plating stub wiring.

  According to one aspect, a wiring board including a signal wiring layer and a ground or power plane facing the signal layer via an insulating layer is provided. The signal wiring layer includes a plurality of signal wirings and a plurality of plating stub wirings connected to the plurality of signal wirings. The ground or power plane has an opening facing the starting point of each plating stub wiring, which is a connection portion of each plating stub wiring with the signal wiring.

  According to another aspect, a semiconductor device having a semiconductor element having a plurality of electrode pads and a wiring board on which the semiconductor element is mounted is provided. This wiring board includes a signal wiring layer and a ground or power plane facing the signal wiring layer via an insulating layer. The signal wiring layer includes a plurality of signal wirings electrically connected to the plurality of electrode pads of the semiconductor element, and a plurality of plating stub wirings connected to the plurality of signal wirings. The ground or power plane has an opening at a position facing the starting point of each plated stub wiring.

  In the plating stub wiring connected to any signal wiring, the characteristic impedance at the starting point can be increased. High-frequency signals are less likely to flow into the plating stub wiring, and a reduction in signal transmission characteristics due to the plating stub wiring is suppressed.

It is sectional drawing which shows a typical BGA type semiconductor device. It is a top view which shows typical plating stub wiring and wiring for plating. It is a top view which shows the typical package substrate and the semiconductor element mounted in it. It is sectional drawing which shows the wiring board and semiconductor device which concern on one Embodiment. It is a top view which shows the wiring board which concerns on one Embodiment, and the semiconductor element mounted in it. It is a top view which expands and shows the area | region A of FIG. It is a top view which shows each conductive layer contained in the area | region A of FIG. It is a line model of a signal path. It is a figure which shows typically the TDR waveform of a signal path | route. It is a top view which shows the modification of plating stub wiring. It is a figure which shows the TDR waveform in the modification of a plane opening part, and this modification. It is a top view explaining the modification of conductive layer arrangement | positioning.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, various components are not necessarily drawn to the same scale. Throughout the drawings, the same or corresponding components are denoted by the same or similar reference numerals.

  A semiconductor device 100 according to an embodiment has a package structure in which a semiconductor element is mounted on a wiring board 120 according to an embodiment.

  First, the overall configuration of the semiconductor device 100 and the wiring substrate 120 included in the semiconductor device 100 will be described with reference to FIGS. 4 shows a schematic cross-sectional view of the semiconductor device 100 after completion (after molding), and FIG. 5 shows a top view of the semiconductor device 100 before molding. In FIG. 5, only a part of the wiring existing on the surface of the wiring board 120 is shown in order to avoid complexity.

  The semiconductor device 100 has a BGA package structure in the illustrated example. Specifically, the semiconductor device 100 includes a semiconductor element 111, a wiring board 120 also called a package board, a conductor 112 that electrically connects the semiconductor element 111 to the package board 120, a mold resin 113, and an external terminal 114. And have.

  In the illustrated example, the semiconductor element 111 has a plurality of electrode pads 111a arranged along the outer edge on the front surface, and is bonded to the package substrate 120 via the adhesive layer 115 on the back surface side. The electrode pad 111a of the semiconductor element is connected to the bonding pad 131 on the package substrate 120 by a conductor 112 that can be a metal wire such as an Au wire. In another example, the semiconductor device may have bumps arranged in an array on the surface, and may be flip-chip mounted on the package substrate. The semiconductor element mounting surface side of the package substrate 120 is covered with a mold resin 113 so as to seal the semiconductor element 111 and the metal wire 112.

  In the illustrated example, the package substrate 120 is a stacked substrate having first to fourth conductive layers 130, 140, 150, and 160 and first to third insulating layers 171 to 173 interposed therebetween. is there. The insulating layers 171 to 173 are not particularly limited, and may be, for example, a resin layer containing a glass epoxy resin or a phenol resin, or a ceramic layer.

  The first conductive layer 130 located on the surface (semiconductor element mounting surface) of the package substrate 120 constitutes a signal wiring layer and includes the bonding pad 131. The signal wiring layer 130 further includes a signal wiring 132 communicating with the pad 131 and a plating stub wiring 133 communicating with the signal wiring 132 and extending to the outer edge of the package substrate 120. The second conductive layer 140 adjacent to the first conductive layer 130 constitutes one plane layer of a ground (GND) having a solid pattern and a power source. Therefore, each signal line 132 and the second conductive layer 140 constitute a microstrip line. The third conductive layer 150 adjacent to the second conductive layer 140 also generally has a solid pattern and constitutes the other plane layer of the ground and the power supply. Hereinafter, the second conductive layer 140 will be described as a ground plane layer, and the third conductive layer 150 will be described as a power plane layer. The fourth conductive layer 160 located on the back surface of the package substrate 120 constitutes a ball pad layer and includes ball pads 161 arranged in an array. The ground plane layer 140 and the power plane layer 150 may include patterns other than the ground plane and the power plane, respectively, but are also simply referred to as a ground plane and a power plane below.

  Each signal wiring 132 and the corresponding ball pad 161 are electrically connected by a via 182 penetrating the package substrate 120 (in FIG. 4, each via 182 and the first to third conductive layers 130 and 140 and The connection relationship with 150 is not shown correctly). As will be described later with reference to FIG. 7, the signal wiring layer 130 has a bonding pad connected to the ground pad of the semiconductor element 111 and a ground wiring connected to the bonding pad, and the ground wiring is grounded via the via. Connected to the plane. Similarly, the signal wiring layer 130 has a bonding pad connected to the power supply pad of the semiconductor element 111 and a power supply wiring connected to the bonding pad, and the power supply wiring is connected to the power supply plane via the via. Each of the ground plane and the power plane is connected to a corresponding ball pad 161 via a via 182.

  A protruding external terminal 114, typically a solder ball, is mounted on each of the ball pads 161 arranged in an array. Therefore, each solder ball 114 becomes an external terminal of the signal, ground, or power supply of the semiconductor device 100 depending on whether the corresponding ball pad 161 is connected to the signal wiring 132, the ground plane 140, or the power supply plane 150. .

  With the above configuration, a signal, ground, and power supply path is completed between the electrode pad 111 a of the semiconductor element 111 and the external terminal 114 of the semiconductor device 100. The signal path includes a metal wire 112 (a bump in the case of flip chip connection), a signal wiring 132 of the first conductive layer, a through via 182, and a ball pad 161. However, this signal path has a branch path called a plating stub wiring 133 connected to the signal wiring 132 at the position of the through via 182.

  For the first to fourth conductive layers 130, 140, 150, and 160, Cu, which is a low-resistance metal, is typically used. In order to prevent surface oxidation and / or improve the connectivity with the Au wire 112, the Cu surfaces of the bonding pad 131 and the ball pad 161 are plated with, for example, Ni / Au plating. Also in the case of flip chip connection, Au or the like can be plated on the pad surface of the package substrate that receives the bumps of the semiconductor element.

  The plating stub wiring 133 electrically connects the individual signal wirings 132 and the bonding pads 131 and the ball pads 161 connected thereto, and makes it possible to perform electrolytic plating on all of them simultaneously. However, as described above, the plating stub wiring 133 forms a branch path of the signal path. One end of the branch path composed of the plated stub wiring 133 is connected to the signal path 132 to form a starting point, and the other end forms an open end at the outer edge of the package substrate 120. Therefore, the plating stub wiring 133 acts as an antenna, and affects the transmission characteristics of the signal flowing through the signal path due to total reflection of the signal at the open end and / or resonance in the branch path.

  In the present embodiment, the package substrate 120 further includes an opening 145 in the plane (here, a ground plane) 140 located under the signal wiring layer 130 so as to face the starting point of the plating stub wiring 133. Yes. In FIG. 5, the broken line surrounding the starting point portion of the plating stub wiring 133 indicates the opening 145 located under the signal wiring layer 130.

  Next, an example of a detailed configuration of the region including the opening 145 and the effect of the opening 145 will be described with reference to FIGS. FIG. 6 is an enlarged view of region A in FIG. 5, and FIG. 7 shows each conductive layer pattern included in region A. FIG. 8 shows a line model of one signal path, and FIG. 9 schematically shows a time domain reflectometry (TDR) waveform of the signal path.

  In this example, the signal wiring layer 130 that is the first conductive layer has bonding pads 131 arranged in a row in the vicinity of the region where the semiconductor element 111 is mounted. The ball pad layer 160 which is the fourth conductive layer has ball pads 161 arranged in four rows along the outer edge of the package substrate 120. The bonding pad 131 includes a signal pad 131s, a ground pad 132g, and a power pad 131v, and the ball pad 161 also includes a signal pad 161s, a ground pad 161g, and a power pad 161v.

  Each signal bonding pad 131s is connected to a corresponding signal via 182s by a signal wiring 132 in a signal wiring layer communicating with the signal bonding pad 131s, and the signal via 182s is connected to a corresponding signal ball pad 161s. In the signal wiring layer 130, the plating stub wiring 133 extends to the outer edge of the package substrate 120 starting from the position of each signal via 182 s. Each ground bonding pad 131g is connected to a first ground via 181g connected to the ground plane 140 by a ground wiring 138 communicating with the ground bonding pad 131g and shorter than the signal wiring 132. The ground plane 140 is connected to a plurality of ground ball pads 161g by a plurality of second ground vias 182g. Each power supply bonding pad 131v is connected to a first power supply via 181v connected to the power supply plane 150 by a power supply wiring 139 communicating with the power supply pad 131v and shorter than the signal wiring 132. The power plane 150 is connected to a plurality of power ball pads 161v by a plurality of second power vias 182v. The ground plane 140 and the power plane 150 have an insulator 185 on the side wall of the through hole filled with different types of vias 181 or 182 of the signal, ground and power, and are electrically insulated from these vias. .

The ground plane 140 has an opening 145 in a region facing the starting point of each plated stub wiring 133, that is, a region adjacent to each signal via 182 s on the outer edge side of the package substrate 120. The size of each opening 145 is determined within a range that does not affect the signal wiring 132 adjacent to the signal wiring 132 communicating with the plating stub wiring 133 immediately above the opening 145 and does not physically interfere with other vias 182. For example, it can be as large as 200 μm ² . Further, the shape and size of the opening 145 may be changed for each opening, and can be flexibly determined according to the layout of the signal wiring 132 and the plating stub wiring 133.

Each signal path 132 can be represented by a line model shown in FIG. The signal wiring 132 and the plating stub wiring 133 of the package substrate 120 and the wiring of a circuit board such as a motherboard on which the semiconductor device 100 is mounted form a distributed constant circuit, and a characteristic impedance Zo = (L / C) ^1/2 is important. Zo of the signal wiring 132 is usually matched to a specific impedance such as 50Ω. Although the wire 112 / bump portion and the via 182 / ball 114 portion connecting the semiconductor element 111 to the package substrate 120 have a short line length, it is difficult to match Zo, which may cause signal reflection. Although Zo matching design has been studied for a high-speed signal-compatible substrate, generally, the capacitance is increased in the via / ball portion, and the characteristic impedance is slightly reduced.

  When the signal wiring 132 and the plating stub wiring 133 have the same width and face the solid ground plane, the plating stub wiring 133 is also impedance-matched. In this case, Zo of the signal wiring 132 and the plating stub wiring 133 observed by the TDR method becomes flat as shown in FIG. In the actual TDR measurement, the via / ball side line, which is the original signal transmission path when viewed from the semiconductor element side, and the plated stub line are branched, and Zo is observed as a mixed value of both. However, FIG. 9 shows that there is no via / ball connection. Therefore, the signal transmitted to the branching portion with the plating stub wiring 133 via the signal wiring 132 easily flows to the plating stub wiring 133 side. Then, due to total reflection at the open end of the plating stub wiring 133, a signal component having a frequency corresponding to the length of the plating stub wiring 133 resonates.

  In contrast, when the ground plane 140 has the opening 145 facing the starting point portion of the plating stub wiring 133, C of the plating stub wiring 133 is reduced and L is increased at the portion. That is, as shown in FIG. 9B, Zo increases at the entrance of the plating stub wiring 133 and impedance mismatch occurs. Then, since the signal reflection at the portion increases, the electrical signal flowing into the plating stub wiring 133 decreases, and more electrical signals flow to the via / ball side that is more consistent. As a result, it is possible to suppress a decrease in transmission characteristics of the high frequency signal due to the plating stub wiring 133.

  In the present embodiment, an opening 145 is intentionally provided in the ground or power plane 140 in order to cause mismatch in characteristic impedance between the signal wiring 132 and the plating stub wiring 133 communicating therewith. However, the opening 145 can also have an effect of discharging gas generated from the components of the insulating layer and suppressing the expansion and / or peeling of the plane 140.

  Next, various modifications of the above-described embodiment will be described with reference to FIGS.

  First, referring to FIG. 10, a modified example of the plating stub wiring is shown.

  As shown in FIG. 10A, the plating stub wiring 133 of the signal wiring layer 130 is narrower and narrower than the other portions at the starting point facing the opening 145 provided in the adjacent ground or power plane 140. The portion 133a may be included. By reducing the wiring width of the portion, the inductance L at the entrance of the plating stub wiring 133 and thus the characteristic impedance Zo can be further increased.

  Further, as shown in FIG. 10B, the plating stub wiring 133 may form a so-called meander wiring 133b at the starting point portion facing the plane opening 145. The meander wiring is a zigzag wiring used in the equal delay wiring technology or the like. By forming the meander wiring 133b in the portion and increasing the wiring length, it is possible to further increase the inductance L and hence the characteristic impedance Zo at the entrance of the plating stub wiring 133 while suppressing an increase in the capacitance C.

Here, when performing the electroplating process, it is important not to have characteristic impedance Zo = (L / C) ^1/2 that is meaningful for a high-frequency signal, but to set the resistance R at DC to a certain predetermined value or less. It is. Although the modification shown in FIGS. 10A and 10B can increase the resistance R of the plating stub wiring 133, the Cu wiring originally has a low resistance. Can be suppressed. Therefore, these modified examples can further reduce the high-frequency signal branched to the plating stub wiring 133 side while ensuring the original function of the plating stub wiring 133, and can enhance the effect of improving the signal transmission characteristics. Alternatively, the opening 145 can be downsized while maintaining the effect of improving the signal transmission characteristics.

  Note that the modified examples shown in FIGS. 10A and 10B may be combined, and the plating stub wiring 133 may be formed thin and long at the starting point portion facing the plane opening 145.

  Next, referring to FIG. 11, a modified example of the plane opening 145 and its effect are shown. 11, (a) is a cross-sectional view corresponding to a part of FIG. 4, (b) is a top view corresponding to FIG. 6, and (c) shows a schematic TDR waveform similar to FIG.

  The ground or power plane 140 adjacent to the signal wiring layer 130 may have a plurality of openings 145 and 146 separated from each other so as to face at least one plating stub wiring 133. As described above, the opening 145 is disposed to face the starting point portion of the plating stub wiring 133, and the opening 146 is disposed on the outer edge side of the package substrate 120 from the opening 145. For example, as shown in FIG. 11B, it is assumed that ball pads 161 and through vias 182 associated therewith are arranged in four rows along the outer edge of the package substrate 120. Only one opening 145 is formed for a relatively short plated stub wiring starting from the outermost via, and the opening 145 is formed for a relatively long plated stub wiring starting from the inner peripheral via. In addition, one or more openings 146 may be formed.

  When only the opening 145 is formed at a position facing the starting point portion of the plated stub wiring 133, particularly in a relatively long plated stub wiring, resonance at a relatively low frequency according to the length affects the signal transmission characteristics. It can happen. However, by providing a plurality of openings 145 and 146 along one plating stub wiring 133, mismatching of characteristic impedance Zo occurs at each opening / non-opening change point, and the length of the plating stub wiring 133 is increased. Resonance at a frequency corresponding to the frequency can be eliminated. Even if resonance corresponding to the short transmission line length partitioned by the plurality of openings 145 and 146 occurs, the resonance frequency can be set sufficiently higher than the signal frequency. Therefore, even in a signal wiring having a relatively short wiring length accompanied by a relatively long plating stub wiring, the influence of resonance of the plating stub wiring 133 is suppressed, and a signal transmission in a higher frequency region is possible.

  For example, when the resonance frequency of the plating stub wiring 133 attached to the outermost ball pad 161 is sufficiently higher than the frequency of the signal handled by the pad 161, what is applied to some plating stub wirings 133? It is good also as a structure which does not provide an opening part. When the signal frequency of each signal wiring 132 is known in advance, the number of openings for the plating stub wiring 133 communicating therewith may be determined according to the signal frequency.

  Finally, referring to FIG. 12, a modification of the conductive layer arrangement of the package substrate 120 is shown in a plan view similar to FIG. The package substrate 120 shown in FIG. 4 may have 230, 240, 250, and 260 instead of the conductive layers 130, 140, 150, and 160, respectively. The signal wiring layer is formed as the second conductive layer 240, and is disposed between the ground as the first and third conductive layers and the plane layers 230 and 250 of the power source. That is, a stripline configuration is formed. Which of the first and third conductive layers 230 and 250 is the ground plane layer is not limited to this, but the following description will be made assuming that the first conductive layer 230 is the ground plane layer.

  The ground plane layer 230 formed on the semiconductor element mounting surface of the package substrate 120 includes a bonding pad 231 and a ground plane 235 arranged in a row in the vicinity of the region where the semiconductor element 111 is mounted. The bonding pad 231 includes a signal pad 231s, a ground pad 231g, and a power supply pad 231v.

  Each signal bonding pad 231 s is connected to the corresponding first signal via 281 s by the first signal wiring 232 in the ground plane layer 230 that communicates with the signal bonding pad 231 s, and the first signal via 281 s corresponds to the corresponding in the signal wiring layer 240. Connected to the second signal wiring 242. Each of the second signal wirings 242 is connected to the corresponding signal ball pad 261s in the ball pad layer that is the fourth conductive layer 260 through the corresponding second signal via 282s. In the signal wiring layer 240, the plating stub wiring 243 extends to the outer edge of the package substrate starting from the position of each of the second signal vias 282s. Each ground bonding pad 231g is connected to the ground plane 234 by a ground wiring 238 communicating therewith, and the ground plane 234 is connected to a plurality of ground ball pads 261g by a plurality of ground vias 282g. Each power supply bonding pad 231v is connected to a first power supply via 281v connected to the power supply plane 250 by a power supply wiring 239 communicating therewith. The power plane 250 is connected to a plurality of power ball pads 261v by a plurality of second power vias 282v. In this example, the first signal via 281s extends only between the first conductive layer 230 and the second conductive layer 240, and the first power supply via 281v includes the first to third conductive layers 230 and 240. And 250 only. The second signal via 282 s extends only between the second to fourth conductive layers 240, 250, and 260, and the second power supply via 282 v is between the third conductive layer 250 and the fourth conductive layer 260. Only extends to. The power plane 250 has an insulator 285 on the side wall of the through hole filled with the ground via 282g and the second signal via 282s, and is electrically insulated from these vias.

The ground plane 234 and the power supply plane 250 have openings 235 and 255 respectively in a region facing the starting point of each plated stub wiring 243, that is, a region adjacent to the second signal via 282s on the outer edge side of the package substrate. Have. The size of each of the openings 235 and 255 does not affect the signal wiring 242 adjacent to the signal wiring 242 communicating with the plating stub wiring 243 facing the opening 235 and 255 and does not physically interfere with other vias 282. For example, the size can be about 200 μm ² .

  Thus, by providing openings 235 and 255 opposite the starting point of the plating stub wiring 243 in both the ground plane 234 and the power supply plane 250 arranged with the signal wiring layer 240 interposed therebetween, FIG. A large impedance mismatch can be generated as compared with the above configuration. However, only one of the ground plane 234 and the power supply plane 250 may have an opening 235 or 255.

  Although the embodiment has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes can be made within the scope of the gist described in the claims. For example, the modifications described with reference to FIGS. 10-12 can be applied in appropriate combinations. Further, the wiring board may include a further conductive layer in addition to the signal wiring layer, the ground plane layer, the power supply plane layer, and the ball pad layer.

Regarding the above description, the following additional notes are disclosed.
(Appendix 1)
A signal wiring layer having a plurality of signal wirings and a plurality of plating stub wirings connected to the plurality of signal wirings;
A ground or power plane facing the signal wiring layer through an insulating layer,
The plane has an opening at a position facing a starting point portion connected to the signal wiring of each plating stub wiring,
A wiring board characterized by that.
(Appendix 2)
The wiring board according to appendix 1, wherein the plated stub wiring is narrower than other portions at a portion facing the opening of the plane.
(Appendix 3)
The wiring board according to appendix 1 or 2, wherein the plating stub wiring forms a meander wiring at a portion facing the opening of the plane.
(Appendix 4)
The wiring board according to any one of appendices 1 to 3, wherein the plane has a plurality of openings spaced from each other so as to face at least one of the plurality of plated stub wirings. .
(Appendix 5)
The plurality of plating stub wirings include at least a first plating stub wiring group and a second plating stub wiring in which the start point portion is located on the outer peripheral side of the wiring board as compared with the first plating stub wiring group. Including groups,
The at least one plating stub wiring includes the first plating stub wiring group;
The wiring board according to appendix 4, which is characterized in that.
(Appendix 6)
The plane is one of ground or power supply planes,
The wiring board further includes the other plane of the ground or the power supply that is opposed to the surface of the one plane opposite to the surface facing the signal wiring layer via a further insulating layer,
The other plane does not have an opening at a position facing the starting point portion of each plating stub wiring.
The wiring board according to any one of appendices 1 to 5, wherein:
(Appendix 7)
The plane is one of ground or power supply planes,
The wiring board further includes the other plane of the ground or the power source that is opposed to the surface opposite to the surface facing the one plane of the signal wiring layer via a further insulating layer,
Both the one plane and the other plane have an opening at a position facing the starting point portion of each plating stub wiring,
The wiring board according to any one of appendices 1 to 5, wherein:
(Appendix 8)
A semiconductor element having a plurality of electrode pads, and a wiring board on which the semiconductor element is mounted,
The wiring board is
A plurality of signal wirings electrically connected to the plurality of electrode pads of the semiconductor element, and a signal wiring layer having a plurality of plating stub wirings connected to the plurality of signal wirings;
A ground or power plane facing the signal wiring layer through an insulating layer, and the plane has an opening at a position facing a starting point portion connected to the signal wiring of each plating stub wiring. ,
A semiconductor device.
(Appendix 9)
A plurality of external terminals formed on a surface opposite to the semiconductor element mounting surface of the wiring board and electrically connected to the plurality of signal wirings via vias formed in the wiring board; Item 8. The semiconductor device according to appendix 8, wherein

DESCRIPTION OF SYMBOLS 100 Semiconductor device 111 Semiconductor element 111a Electrode pad 112 Metal wire 113 Mold resin 114 External terminal 115 Adhesive layer 120 Wiring board (package board)
130, 240 Signal wiring layer 131, 231 Bonding pad 132, 242 Signal wiring 133, 243 Plating stub wiring 133a Narrow portion 133b Meander wiring 140, 230 Ground plane layer 145, 146, 235, 255 Plane opening 150, 250 Power plane Layer 160, 260 Ball pad layer 161, 261 Ball pad 171, 172, 173 Insulating layer 181, 182, 281, 282 Via 185, 285 Insulator

Claims (6)

A signal wiring layer having a plurality of signal wirings and a plurality of plating stub wirings connected to the plurality of signal wirings;
A ground or power plane facing the signal wiring layer through an insulating layer,
The plane has an opening at a position facing a starting point portion connected to the signal wiring of each plating stub wiring,
A wiring board characterized by that.   The wiring board according to claim 1, wherein the plated stub wiring is narrower than other portions in a portion facing the opening of the plane.   The wiring board according to claim 1, wherein the plating stub wiring forms a meander wiring in a portion facing the opening of the plane.   4. The wiring according to claim 1, wherein the plane has a plurality of openings spaced from each other so as to face at least one of the plurality of plating stub wirings. 5. substrate. The plane is one of ground or power supply planes,
The wiring board further includes the other plane of the ground or the power source that is opposed to the surface opposite to the surface facing the one plane of the signal wiring layer via a further insulating layer,
Both the one plane and the other plane have an opening at a position facing the starting point portion of each plating stub wiring,
The wiring board according to any one of claims 1 to 4, wherein the wiring board is provided. A semiconductor element having a plurality of electrode pads, and a wiring board on which the semiconductor element is mounted,
The wiring board is
A plurality of signal wirings electrically connected to the plurality of electrode pads of the semiconductor element, and a signal wiring layer having a plurality of plating stub wirings connected to the plurality of signal wirings;
A ground or power plane facing the signal wiring layer through an insulating layer, and the plane has an opening at a position facing a starting point portion connected to the signal wiring of each plating stub wiring. ,
A semiconductor device.