JP2011180969A - Data processor - Google Patents

Abstract

Provided is a data processor capable of managing access to a shared resource and increasing the physical address space of the shared resource while minimizing required resources.
A data processor (1, 2, 3) includes a central processing unit (101) for executing a program and an internal module (105, 102) for outputting address information for accessing an address space of the central processing unit. The internal module has a first operation mode in which an identifier used for memory protection is not added to the address information, and a second operation mode in which the identifier is added to the address information.
[Selection] Figure 1

Description

  The present invention relates to a data processor, and more particularly to a technique effective when applied to a data processor having a function of outputting address information for accessing an address space of a central processing unit.

  In recent years, due to the high integration of semiconductor devices, a microprocessor system in which a plurality of microprocessors equipped with a single central processing unit is integrated.

  In the microprocessor system, resources such as a main storage device and an input / output device used by each central processing unit are commonly shared in the system mainly due to restrictions on the number of terminals with respect to the LSI area. Is. When resources are used by a plurality of central processing units in this way, for example, illegal access due to bugs in the control software occurs, and data is not processed correctly due to a collision of the memory unit of the main storage device that is a resource. Such a problem may occur. Therefore, when using resources, it is important to manage access to resources to avoid unauthorized access.

  When a program is operated on a microprocessor system equipped with a plurality of central processing units, an operating system corresponding to the program is required. There are roughly two types of operating system systems corresponding to a microprocessor system equipped with a plurality of central processing units.

  One is a symmetric multiprocessor system in which a single operating system manages all of a plurality of central processing units, a single main storage device, and input / output devices, and the other is a plurality of central processing units. This is an asymmetric multiprocessor system in which an operating system is installed in each processing device. In particular, in a microprocessor for an embedded device, an asymmetric multiprocessor system is often used. The reason for this is that software assets can be easily migrated, and a subsystem with different characteristics can be easily handled by an asymmetric multiprocessor in a recent embedded system. An example of a microprocessor system to which an asymmetric multiprocessor system is applied is an automotive microprocessor system. In the microprocessor system, an information system process for calculating a relatively large amount of data such as a car navigation system, and a control system that requires a more reliable process such as a brake control, although the data scale is small. By coordinating with processing, they coexist and fuse as one system. In recent years, the demand for such multiprocessors is rapidly expanding.

  For example, Patent Document 1 discloses a conventional method of shared resource management in an asymmetric multiprocessor system. In Patent Document 1, an operating system and a user program operating under the control of the operating system are handled as a virtual machine, and a virtual machine ID (VMID) for identifying the virtual machine is set. Then, the VMID is stored for each entry of the memory management unit (MMU) and the cache memory that are physically mounted, and the physical address management module (PAM) determines which protection domain they belong to. How to manage access to is shown.

  On the other hand, in recent application systems using a microprocessor system, larger-scale data such as a database used in a recognition system using moving image data or audio data has come to be handled. In addition, as memory devices have been miniaturized and memory technology has been improved, inexpensive memory devices have become widespread, and the main storage capacity installed in the system has been rapidly increasing. In particular, in the asymmetric multiprocessor described above, it is necessary to store all operating system and user program codes and data such as processing results in the main storage device which is a representative resource to be used. Therefore, a substantial increase in the required main storage capacity is required. This requires an increase in the physical address space that can be handled by the central processing unit in the microprocessor system. Therefore, in general, in order to increase the physical address space in which the main memory is arranged, a physical address bus having a wider address width is provided, and a cache tag array for storing an accompanying physical address and a page number stored in the MMU are provided. Solutions to increase the width are taken.

JP 2008-97173 A

  The above-described microprocessor system equipped with a plurality of central processing units capable of executing programs using shared resources under the management of different operating systems has the following problems.

  The first problem is an increase in hardware scale associated with shared resource management in a microprocessor system. For example, when shared resources are managed by the method of Patent Literature 1, VMID is used as described above to distinguish a plurality of operating systems. Then, it is necessary to provide a memory unit for storing VMID in an associative memory such as a cache memory. For example, if 200 protection domains exist on a microprocessor system, an 8-bit VMID is required. A memory unit for storing this 8-bit additional information is included in all entries in the associative memory of the microprocessor. Must have. In the case of a microprocessor system used for general purposes, the application system is different, so it is difficult to predetermine resources that the microprocessor hardware has in advance. Therefore, in a multiprocessor system used in an asymmetric configuration, the memory unit for storing the VMID in the associative memory of each microprocessor is inevitably designed with a large margin. For example, in a multiprocessor system equipped with two microprocessors, when there is a first processor that handles one protection domain and a second processor that handles 16 protection domains, the VMID is stored in the first processor. One bit is sufficient, but the second processor needs the 4-bit VMID. In the case of a multiprocessor system used in such an asymmetric configuration, an associative memory is designed so that each microprocessor can handle the maximum protection domain (4 bits), and as a result, an excessive specification is defined. Become. This is a problem for an embedded processor that places particular emphasis on low cost.

  The second problem is an increase in hardware scale accompanying an increase in the physical address space of the main storage device. As described above, if the physical address space of the main memory increases, it is necessary to increase the number of bits of the physical address stored in the associative memory such as the MMU and the cache in proportion thereto, and the hardware scale increases as a whole system. However, even in an asymmetric multiprocessor system that requires a large physical address space, the memory capacity required by each operating system and the application under its control is comparable. Are small and vary from operating system to operating system. For example, one operating system and a subsystem operating under its control may require as much as 4 gigabytes of memory space, while another subsystem may require only a small memory space. In such a case, the multiprocessor system as a whole requires a memory space exceeding 4 gigabytes, but the subsystem belonging to each protection domain often requires a memory space of 4 gigabytes or less. However, in a microprocessor system using a plurality of operating systems, as in the first problem, it is difficult to predetermine resources to be provided in the microprocessor hardware when the application system is different. It is designed to be large with a margin. For this reason, the microprocessor has an excessive specification that is not originally required, and can be a problem of cost, particularly in the field of the embedded processor, as in the first problem.

  An object of the present invention is to provide a data processor capable of managing access to a shared resource and increasing the physical address space of the shared resource while minimizing required resources.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in a data processor having a central processing unit that executes a program and an internal module that outputs address information for accessing an address space of the central processing unit, the internal module assigns an identifier used for memory protection to the address There is a first operation mode that is not added to the information, and a second operation mode that adds the identifier to the address information.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the data processor can cope with the increase in the physical address space of the shared resource and the access management to the shared resource while minimizing the required resource.

FIG. 1 is a block diagram of a data processor according to the first embodiment. FIG. 2 is an explanatory diagram of an operation mode of a program executed by the CPU 101. FIG. 3 is a detailed block diagram of the data processor according to the first embodiment. FIG. 4 is an example of the correspondence between the setting value of the DMCR 104 and the extended data. FIG. 5 is an example of a block diagram of the comparison unit 1025. FIG. 6 is an example of a correspondence relationship between the setting value of the DMCR 104 and the data stored in the expansion array 1022. FIG. 7 is a block diagram of a data processor according to the second embodiment. FIG. 8 is a setting example of DMID and address space related to the processor cores 20_A to 20_C. FIG. 9 is a detailed block diagram of the data processor 2 according to the second embodiment. FIG. 10 is an example of information supplemented by the bus interface 206. FIG. 11 is a block diagram of the data processor 3 according to the third embodiment. FIG. 12 is an example of the correspondence between the setting value of DMCR 304 and the extended data. FIG. 13 is an example of a block diagram of the comparison unit 3025. FIG. 14 is an example of a block diagram of the error correction logic unit 3027. FIG. 15 is an example of a block diagram of the extension data generation unit 3030.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (2 operation modes)
A data processor (1, 2) according to a representative embodiment of the present invention includes a central processing unit (101) that executes a program and an associative memory that holds a part of data in the address space of the central processing unit (102) and a first register (103) that holds an identifier used for memory protection. The associative memory includes a plurality of associative entries including a tag unit (1022, 1023) for storing tags and a data unit (1024) for storing data, and the central processing unit when accessing the central processing unit. A comparison unit (1025) for comparing the information supplied from the information and the indexed tag. The associative memory has a first operation mode in which the supplied information is address information, and a second operation mode in which the supplied information is address information and the identifier. According to this, the data processor can cope with memory protection using the identifier and expansion of the number of bits of the physical address stored in the associative memory.

[2] (Switching of expansion part)
The data processor according to item 1 further includes a second register (104) for holding information for determining the operation mode of the associative memory, and the tag unit includes an address unit (1023) for storing address information; And an extension (1022). The associative memory determines the operation mode based on a value of the second register, and the extension unit stores address information in the first operation mode, and the identifier in the second operation mode. Is stored. According to this, since the extension part is used, it becomes easy to cope with two operation modes.

[3] (Detailed operation in the first operation mode)
In the data processor according to item 1 or 2, in the first operation mode, the comparison unit is held in the address unit and the extension unit in the supplied address information and the associative entry corresponding to the address information. Compare the address information. As a result, if they match, the associative memory outputs the data of the data portion in the associative entry, and if they do not match, the supplied address information and the corresponding data are converted to the corresponding Store in associative entry.

[4] (Detailed operation in the second operation mode)
In the data processor according to any one of Items 1 to 3, in the second operation mode, the comparison unit is configured to provide the address information in the address section in the associative entry corresponding to the supplied address information and the address information. And the supplied identifier and the information held in the extension in the associative entry are compared. As a result, if both match, the associative memory outputs the data of the data part in the associative entry. If one or both do not match, the supplied address information and the corresponding data are output. Are stored in the corresponding associative entry.

[5] (Domain identifier)
In the data processor according to any one of Items 1 to 4, the identifier used for protecting the memory is a domain identifier for identifying upper software that manages execution of the program. According to this, it is possible to protect the memory for each upper software.

[6] (Multiple data processing units)
The data processor according to any one of Items 1 to 5, wherein the data processor includes a plurality of data processing units (20_A to 20_C) including the central processing unit, the associative memory, the first register, and the second register. The second register can be set for each data processing unit.

[7] (The number of bits in the address space is complemented)
The data processor according to Item 6 further includes buses (20, 21) commonly used by the data processing units, and the data processing unit is configured to respond to an access request from the central processing unit. Has an access control unit (206) that performs control for outputting the address information supplied by the first and third registers (107, 107A to 107C) in which information for complementing the address information is stored. The bus has a bus width equal to or larger than a bus width corresponding to a maximum address space among the plurality of data processing units. Further, when the access control unit determines that the address width based on the address information supplied by the central processing unit is smaller than the bus width when the central processing unit makes an access request, Based on the value of the register, new address information obtained by supplementing the address information with predetermined information is output to the bus. According to this, even if the number of bits in the address space of the data processing unit does not match the number of bits in the bus, the data processing unit can be applied.

[8] (Bit number complementation of identifier)
In the data processor according to item 7, the access control unit further performs control to output the value of the first register in response to an access request from the central processing unit.

  [9] In the data processor according to item 8, the third register further stores information for complementing the value of the first register, and the bus further includes the memory protection among a plurality of the data processing units. The bus width is equal to or larger than the bus width corresponding to the maximum amount of data used for the identifier. In addition, when the central processing unit makes an access request, the access control unit determines that the value of the first register is smaller than the bus width, based on the value of the third register, New information obtained by complementing predetermined information to the value of the first register is output to the bus. According to this, even when the number of bits of the identifier of the data processing unit does not match the number of bits of the bus, the data processing unit can be applied.

[10] (Specific method of complementation)
In the data processor according to any one of Items 7 to 9, the access control unit determines the number of bits to be complemented with reference to the value of the second register. According to this, since the operation mode of the data processing unit is known by referring to the value of the second register, it is easy to determine the number of bits to be complemented.

[11] (Two operation modes (ECC))
A data processor (1, 2, 3) according to another exemplary embodiment of the present invention includes a central processing unit (101) that executes a program and a part of data in the address space of the central processing unit. And an associative memory (302) for holding. The associative memory includes a plurality of associative entries including a tag unit (1022, 1023, 3022) for storing a tag and a data unit (1024) for storing data, and the central processing unit accesses the central processing unit. Comparing units (1025, 3025) for comparing information supplied from the processing device with the indexed tags. The associative memory has a first operation mode in which the supplied information is address information, and a second operation mode in which the supplied information is address information and information for error correction. According to this, the data processor can cope with soft error countermeasures and expansion of the number of bits of the physical address stored in the associative memory.

[12] (Switching of expansion part)
The data processor according to item 11 further includes a first register (103) that holds information for determining the operation mode of the associative memory, and the tag unit includes an address unit (1023) that stores address information. And expansion portions (1022, 3022). The associative memory determines the operation mode based on the value of the first register, and the extension unit stores address information in the first operation mode, and the error correction in the second operation mode. Information for storing is stored. According to this, since the extension unit is used, it becomes easy to cope with two operation modes.

[13] (Cache memory)
In the data processor according to any one of Items 2 to 12, the associative memory is a cache memory.

[14] (Address translation buffer)
In the data processor according to any one of Items 2 to 12, the associative memory is an address conversion buffer that stores an address conversion pair for converting a virtual address in a virtual address space of the central processing unit into a physical address.

[15] (Internal module)
The data processor (1, 2, 3) according to another exemplary embodiment of the present invention includes a central processing unit (101) that executes a program and the central processing based on data processing by the central processing unit. It has an internal module (105, 102, 302) that outputs address information for accessing the address space of the device, and a first register (103) that holds an identifier used for memory protection. The internal module has a first operation mode in which the identifier is not added to the address information, and a second operation mode in which the identifier is added to the address information. According to this, the data processor can cope with the memory protection against the access of the internal module and the expansion of the number of bits of the physical address.

[16] (Switching operation mode)
The data processor according to item 15, further includes a second register (104, 304) that holds information for determining the operation mode, and the internal module is configured to select the operation mode based on a value of the second register. To decide. The identifier used for memory protection is a domain identifier for identifying higher-order software that manages execution of the program. According to this, switching between the two operation modes is facilitated, and memory protection for each upper software is possible.

2. Details of Embodiments Embodiments will be further described in detail.

<< Embodiment 1 >>
FIG. 1 is an example of a data processor according to the first embodiment.

  A data processor 1 shown in FIG. 1 includes a processor core (PRO_CORE) 10 that performs data processing and a physical address management module (PAM) 30 that manages access to a main storage device (MEM) 40, and includes a bus 50. Commonly connected to The PAM 30 is connected to the main storage device 40 which is a shared resource such as the processor core 10. The bus 50 is also connected to an I / O circuit (not shown) and other peripheral circuits.

  The processor core 10 includes a central processing unit (hereinafter referred to as “CPU”) 101, a memory management unit (MMU) 105, a cache memory (CACHE) 102, a domain ID register (DMID) 103, and a domain control register (DMCR) 104. And a bus interface (BIF) 106. FIG. 1 shows only the components necessary for the description of the present embodiment.

  The CPU 101 fetches an instruction stored in the main storage device 40, decodes the fetched instruction, and performs data processing according to the decoded instruction. Access to the main storage device 40 by the CPU 101 is specified by a 32-bit logical address and an 8-bit protection domain ID (domain ID) described later. The logical address is converted into a physical address by the MMU 105, and access is executed by outputting the physical address and the domain ID on the bus 50 via the bus interface 106.

  The cache memory 102 is a physical cache, although not particularly limited. Details of the cache memory 102 will be described later.

  Although the details will be described later, the domain control register (DMCR) 104 stores a value for determining the type of information stored in the extended array 1022 of the cache memory 102.

  The domain ID register 103 stores a domain ID (DMID).

  The domain ID will be described in detail.

  The CPU 101 executes a plurality of programs. These programs have different accessible address ranges and operate in a plurality of operation modes.

  FIG. 2 is an explanatory diagram of an operation mode of a program executed by the CPU 101.

  As shown in FIG. 2, an operating system program that is higher-level software is represented in a privilege mode (PRIV mode), and a program for executing a user application is represented in a user mode (USER mode). The data processor 1 according to the present embodiment has an operation mode (hereinafter referred to as “XVS mode”) that manages and supervises a plurality of higher-level operating systems. The XVS mode is an operation mode with the highest authority, and executes domain management software (DMGR) that realizes interference prevention and communication between operating systems. In the XVS mode, the settings of the domain ID register 103, the domain control register 104, and the PAM 30 can be rewritten. On the other hand, in operation modes other than the XVS mode (privileged mode and user mode), rewriting of the above settings is prohibited by hardware such as a mode register, so that protection from software defects and malicious programs is ensured.

  The domain ID identifies higher-order software that manages execution of the program, and a number is assigned to each operating system. The domain ID is used to distinguish each operating system when a plurality of operating systems operate. The CPU 101 stores the domain ID of the operating system to be executed in the domain ID register in the XVS mode. In this embodiment, the domain ID is used for memory protection. For example, the PAM 30 manages access to the main storage device 40 by an application program operating under the management of the operating system.

  A specific method of access management of the main storage device 40 by the PAM 30 is as follows.

  The PAM 30 stores a plurality of data pairs of an address of the main storage device 40 and a protection domain ID (DMID) accessible to the address in an entry table. When the processor core 10 requests access to the main storage device 40, the PAM 30 receives the physical address (PADR) and the domain ID output to the bus 50, and the data of the entry table Access authority is confirmed by comparing with a pair. The entry table can be set in the XVS mode. For example, when the system is started, the domain management software is set prior to starting the operating system.

  FIG. 3 is a detailed block diagram of the data processor according to the first embodiment.

  The logical address space of the CPU 101 is not particularly limited, but is a space managed by a 32-bit address signal. The physical address space generated by the MMU 105 is a space managed by an address signal having a maximum of 40 bits and a minimum of 32 bits. As described above, for the sake of easy understanding, the MMU 105 uses a 32-bit logical address as a combination of the upper physical address (UPADR) [39:32] and the lower physical address (LPADR) [31: 0]. Converting to a 40-bit physical address, the 32-bit logical address is made equal to the 32-bit LPADR.

  As described above, the physical address space of the CPU 101 can further expand the address space of at least 32 bits by 8 bits, and DMID of a maximum of 8 bits can be used for protecting the memory of the main storage device 40 by the PAM 30. The cache memory 102 is considered to be able to perform associative storage consistent with memory protection using up to 8-bit address expansion and up to 8-bit DMID. The contents will be described in detail below.

  The cache memory 102 includes memory units 1022 to 1024 configured by SRAM, a comparison unit 1025 that compares a tag address to determine whether a cache hit or a cache miss, and selects data based on the determination result And a control logic unit 1021 that controls the memory units 1022 to 1024 and the comparison unit 1025.

  Although not particularly limited, the memory units 1022 to 1024 have a 4-way set associative configuration, and each set includes an expansion array 1022, a tag array 1023, and a data array 1024. Each array has a data line that can be indexed by an index address, and the corresponding data line of each array is collectively referred to as a cache line. The cache line is an extension data in the extension array 1022 and a tag in the tag array 1023. Information, data information for a plurality of access units in the data array 1024, and valid bits are held as cache entries.

  The extension data is, for example, extension address information of up to 8 bits or DMID of up to 8 bits, and logical addresses output by the CPU 101 when accessing the memory are illustrated as a tag address TAG, an index address INDEX, and an offset address OFST for convenience. . Here, it is understood that the 32-bit lower physical address (LPADR) is the same.

  When accessing the CPU 101, the memory units 1022 to 1024 give the cache line information designated by the index address INDEX to the comparison unit 1025, and the comparison unit 1025 receives the physical address information at that time, the DMCR 104, and the domain ID register. A cache hit or miss is discriminated by referring to the value 103. In the case of a cache hit in the read access of the CPU 101, the data in the data array 1024 of the cache line of the way related to the hit is selected by the selection unit 1029, and only the necessary data specified by the offset address OFST is returned to the CPU 101. It is. If there is a cache miss in the read access, the control logic unit 1021 starts a bus cycle using the access address at that time, reads the data related to the cache miss, returns it to the CPU 101, and based on the read data, etc. Create a cache entry. If it is a cache hit in a write access, the control logic unit 1021 writes the write data to the data array 1024 of the cache line of the way related to the hit. If there is a cache miss in the write access, the control logic unit 1021 starts a bus cycle using the access address at that time, reads the data related to the cache miss, generates a cache entry, and corresponds to the generated cache entry. Write data relating to a cache miss is stored in the data array 1024.

  Expansion data in the expansion array 1022 is determined by the setting of the DMCR 104.

  FIG. 4 is an example of the setting value of the DMCR 104 and the extension data.

  The setting of the DMCR 104 is determined from the number of protection domains required in the application system of the data processor 1 and the maximum main storage capacity value used in the protection domain. For example, if there are 10 types of operating systems and the maximum main storage capacity value required is 64 GB, 4 bits are required as a protection domain, and a 32-bit lower physical address is used as a physical address. 36 bits including the upper physical address of 4 bits are required. Therefore, the 8-bit storage capacity of the expansion array 1022 is divided into 4 bits, DMID is stored in one 4 bits, and higher physical address can be stored in the other 4 bits. In this case, as shown in FIG. 4, by setting the setting value of the DMCR 104 to “01”, the upper physical address [35:32] is stored in the extended array 1022 [7: 4], and the extended array 1022 DMID [3: 0] is stored in [3: 0]. On the other hand, if the physical address is not expanded and 8 bits are required as a protection domain, the DMCR value is set to “00” to store DMID [7: 0] in the expanded array 1022 [7: 0]. When the physical address is expanded by 8 bits, UPADR [39:32] is stored in the expanded array 1022 [7: 0] by setting the DMCR value to “10”. The correspondence between the setting value of the DMCR 104 and the extension data is not limited to the above example, and can be changed according to the use of the extension array 1022.

  Next, the operation of the cache memory 102 in read access will be described in detail.

  When the CPU 101 performs a read access, the memory units 1022 to 1024 provide the cache unit information specified by the index address INDEX to the comparison unit 1025 and the selection unit 1029. That is, the tag information for each way, the valid bit, and the extension data are provided to the comparison unit 1025, and the data information of each way is provided to the selection unit 1029. Further, the comparison unit 1025 inputs UPADR and LPADR. The operation of the comparison unit 1025 will be described in detail with reference to FIG.

  FIG. 5 is an example of a block diagram of the comparison unit 1025.

  The comparison unit 1025 includes an extended function selector 1027 and comparators 1030 and 1031.

  The extended function selector 1027 inputs the value of the DMCR 104, the value (DMID) of the domain ID register 103, and UPADR, and selects and outputs UPADR or DMID or both based on the value of the DMCR 104 To do. For example, in the case of FIG. 4, when the DMCR value is “00”, DMID [7: 0] is selected and output. When the DMCR value is “11”, the upper physical address [39:32] is selected and output. When the DMCR value is “01”, DMID [3: 0] and the upper physical address are selected. The address [35:32] is selected and output.

  The comparator 1031 compares the data selected by the extended function selector 1027 with the information in the extended array 1022 for each way, and if the comparison result is the same, the comparison result is the same. A comparison result mismatch is output for each way. For example, when the value of the DMCR 104 is “00”, since the extension data is DMID [7: 0], the comparator 1031 compares DMIDs. The comparator 1030 compares the tag information [31: 0] and LPADR [31: 0] for each way, and if the comparison result is coincident and the valid bit indicates valid, the comparison result coincides. Otherwise, a comparison result mismatch is output for each way. If there is a way in which both the comparator 1030 and the comparator 1031 match the comparison result, the comparison unit 1025 outputs a cache hit as a signal HIT for each way. On the other hand, if the comparison result does not match in any way, a cache miss is output by the signal HIT. The HIT signal is given to the control logic unit 1021 and the selection unit 1029.

  When the comparison unit 1025 makes a cache hit by the comparison, the selection unit 1029 selects and outputs data of one way hit among the four ways based on the signal HIT. On the other hand, when a cache miss occurs, the control logic unit 1021 starts a bus cycle using the physical address at that time, and gives a command to the bus interface 106 to read data related to the cache miss. The bus interface 106 instructs the PAM 30 to transfer data from the main storage device 40 by giving a DMID together with a physical address. At this time, the bus interface 106 refers to the value of the DMCR 104 and gives a physical address corresponding to the number of bits of the managed address space to the PAM 30. For example, in the case of FIG. 4, when the value of the DMCR 103 is “00”, LPADR [31: 0] is output because the managed address space is 32 bits. On the other hand, when the value of the DMCR 103 is “11”, the address space to be managed is 40 bits, so UPADR [39:32] and LPADR [31: 0] are output.

  Data obtained from the main storage device 40 in accordance with the instruction is given to the control logic unit 1021 via the bus interface 106. The control logic unit 1021 returns only the necessary data specified by the offset address OFST among the read data to the CPU 101 and generates a cache entry based on the read data. The cache entry generation method is described below.

  The control logic unit 1021 stores the read data in the data array 1024 corresponding to the indexed cache line. Further, the write control unit 1026 provided in the control logic unit 1021 stores the LPADR tag information of the access address in the tag array 1023 corresponding to the indexed cache line and enables the valid bit. Further, the write control unit 1026 stores the extension data in the extension array 1022 corresponding to the cache line based on the value of the DMCR 104.

  FIG. 6 shows an example of a correspondence relationship between the setting value of the DMCR 104 and the data stored in the expansion array 1022.

  For example, as shown in FIG. 6, when the value of the DMCR 104 is “00”, the write control unit 1026 stores DMID [7: 0] as the extension data in the extension array 1022, and the value of the DMCR 104 When “11” is “11”, UPADR [39:32] is stored as the extension data. Further, when the value of the DMCR is “01”, 8 bits including DMID [3: 0] and UPADR [35:32] are stored as the extension data.

  The tag information, the extension data, and the data information are stored in the memory units 1022 to 1024 corresponding to the cache lines indexed by the above method.

  Next, the operation of the cache memory 102 in write access will be described.

  When the CPU 101 performs a write access, the tag information and the valid bit for each way of the cache line specified by the index address INDEX are given to the comparison unit 1025 as in the case of the read access described above. Then, the comparator 1031 compares the data selected by the extended function selector 1027 with the extended data in the same manner as in read access, and the comparator 1030 compares the tag information with LPADR. Thus, a cache hit or miss is determined. If the result of the comparison is a cache hit, the control logic unit 1021 writes data to the data array indexed by the offset address OFST of the data array 1024 corresponding to the cache line of the way related to the hit. On the other hand, if it is a cache miss, the control logic unit 1021 activates a bus cycle using the access address at that time in the same manner as at the time of read access, reads the data related to the cache miss, and generates a cache entry. Then, write data relating to a cache miss is stored in the data array indexed by the offset address OFST of the data array 1024 relating to the entry.

  According to the data processor according to the first embodiment, the cache memory 102 includes the expansion array 1022 and the DMCR 104, so that the number of protection domains and the size of the physical address space can be increased stepwise according to the application system. It becomes possible to select. As a result, the size of the cache memory array that occupies a large area of the processor core 10 can be reduced as compared with the conventional method in which the 8-bit protection domain and the 8-bit upper physical address are separately stored.

<< Embodiment 2 >>
FIG. 7 is a block diagram of a data processor according to the second embodiment.

  The data processor 2 shown in FIG. 7 has a plurality of processor cores, and the processor cores 20_A to 20_C are commonly connected to the bus 51 and use the main storage device 41 via the physical address management module (PAM) 31. . The PAM 31 manages access to the main storage device 41 by the same method as the PAM 30. The processor cores 20_A to 20_C have the same function as the processor core 10 according to the first embodiment, and can set independent DMIDs and address spaces.

  FIG. 8 shows a setting example of DMID and address space related to the processor cores 20_A to 20_C.

  In FIG. 8, the processor core 20_A is set with one protection domain and a 40-bit (1 TB) physical address space. The processor core 20_B has a protection domain of 16 (4 bits) and a physical address space of 36 bits (64 GB), and the processor core 20_C has a protection domain of 256 (8 bits) and 32 bits (4 GB). ) Physical address space is set. At this time, the bus 51 includes a maximum address space of 40 bits and a maximum protection domain number of 8 bits (256) in the processor cores 20_A to 20_C, and the PAM 31 and the main storage device 41 can take. The space specified by the maximum physical address space of 40 bits can be handled by dividing it into 256 protection domains. When a plurality of processor cores having different protection domain numbers and physical address spaces set as described above perform bus access, the following problems occur.

  For example, when the cache memory 102_B related to the processor core 20_B set as shown in FIG. 8 gives a command for reading data related to a cache miss to the bus interface, the bus interface sends a protection domain to the PAM 31 along with a physical address. By giving (DMID), the transfer of data from the main storage device 41 is instructed. At this time, since the physical address space managed in the processor core 20_B is 36 bits and the protection domain is 4 bits, in order to perform bus access to an access target in which an 8-bit protection domain and a 40-bit address space are set. Has the problem of lack of information. Therefore, the processor cores 20_A to 20_C according to the second embodiment supplement the information in the number of address bits and the protection domain for bus access instead of the bus interface 106 of the processor core 10 according to the first embodiment. The bus interface 206 has a function, and further includes a complement register (EXTID) 107 in which information for the complement is stored.

  FIG. 9 shows a detailed block diagram of the data processor 2. Here, for ease of explanation, only the connection relationship between one of the processor cores 20_A to 20_C and the bus 51 is shown.

  In FIG. 9, the components other than the bus interface 206 and the EXTID 107 are the same as those of the processor core 10. The bus interface 206 inputs the upper physical address (UPADR), the lower physical address (LPADR), the values of the domain ID register 103 and the DMCR 104 and the value of the EXTID 107.

  In the EXTID 107, information on complementary bits corresponding to the value of the DMCR 104 is stored. Although not particularly limited, the storage capacity of 8 bits is provided in the same manner as the expansion array 1022 here. For example, in the case of FIG. 4 described above, when the value of the DMCR 104 is “00”, the physical address is 32 bits and the DMID is 8 bits. Therefore, the EXTID 107 stores 8 bits of complementary bits of the physical address. When the value of the DMCR 104 is “01”, since the physical address is 36 bits and the DMID is 4 bits, the EXTID 107 stores 4 complementary bits for each of the physical address and DMID. Further, when the value of the DMCR 104 is “10”, since the physical address is 40 bits and the DMID is 0 bits, the EXTID 107 stores DMID complementary bits for 8 bits.

  Specific processing contents related to bit complementation by the bus interface 206 are as follows.

  For example, when the cache memory 102 reads data related to a cache miss, when the bus interface 206 receives a command for reading data from the cache memory 102, the bus interface 206 refers to the value of the DMCR 104. Then, the bus interface 206 complements the input physical address and DMID information with the complementary bit based on the value of the DMCR 104, and provides the PAM 31 with new physical addresses PADR2 and DMID2, thereby providing the main memory. An instruction to transfer data from the device 41 is given.

  FIG. 10 shows an example of information supplemented by the bus interface 206.

  For example, when the DMCR value is “00”, the bus interface 206 uses the complementary bits [7: 0] stored in the EXTID 107 as the upper physical address (UPDR2), and the UPADR2 [7: 0] and LPADR. A new physical address PADR2 [39: 0] combined with [31: 0] is output. The bus interface 206 outputs the DMID [7: 0] as the DMID2 [7: 0]. When the DMCR value is “01”, the bus interface 206 uses the complementary bits [7: 4] stored in the EXTID 107 as the upper physical address (UPDR2), and the UPADR2 [7: 4] and LPADR [ 31: 0] and a physical address PADR2 [35: 0] are output. The bus interface 206 outputs DMID2 [7: 0], which is a combination of the complementary bits [3: 0] stored in the EXTID 107 and the DMID [7: 4]. At this time, only the value of DMID2 [7: 4] on the upper side of the DMID2 [7: 0] makes sense. When the DMCR value is “00”, the bus interface 206 outputs the complementary bits [7: 0] stored in the EXTID 107 as DMID2 [7: 0]. At this time, the value of the DMID2 [7: 0] does not make sense. The bus interface 206 outputs the UPADR [38:32] as UPADR2 [38:32].

  According to the second embodiment, even when the cache memory 102 is accessed by the bus, even if the number of bits such as the address output from the bus interface of the processor core is different from the number of bits such as the address to be accessed. Since bus access is possible, a plurality of processor cores to which the cache memory 102 is applied can be connected to a common bus.

  In the conventional data processor to which the configuration of the data processor according to the second embodiment is not applied, the maximum physical address space and the maximum number of protection domains are combined when the physical address space and the protection domain required by the plurality of processor cores are different. I had to use cache memory. However, according to the present embodiment, it is possible to cope with protection corresponding to various domains and expansion of the physical address space while keeping the area of the processor core small.

<< Embodiment 3 >>
FIG. 11 shows a data processor 3 according to the third embodiment.

  In the data processor 1 according to the first embodiment, the physical address and the protection domain (DMID) are stored in the extended array 1022 of the cache memory 102 so as to be switchable. The protection domain (DMID) and the error correction code (hereinafter referred to as “ECC (Error Checking and Correction) code”) are stored in a switchable manner. Here, the ECC is a function of detecting and correcting an error in order to avoid a soft error in which information of a storage element constituting a RAM (Random Access Memory) is reversed due to the influence of radiation or neutron radiation. In the following description, ECC using 4 redundant bits for 32-bit data will be described as an example.

  The data processor 3 according to the third embodiment includes a cache memory 302 and a domain control register (DMCR) 103 instead of the cache memory 102 and the DMCR 104 of the data processor 10 according to the first embodiment.

  The cache memory 302 further includes an error correction logic unit (ECR (Error Collector)) 3027 that detects and corrects data errors, and replaces the expansion array 1022, the control logic unit 1021, and the comparison unit 1025. And an expansion array 3022, a control logic unit 3021, and a comparison unit 3025. The other components are the same as those of the cache memory 102, and a detailed description thereof is omitted.

  The expansion array 3022 is not particularly limited, but here has a storage capacity of 8 bits. The extension data is, for example, a protection domain (DMID) having a maximum of 8 bits or an ECC code having a maximum of 4 bits, which is determined by a setting value of the DMCR 304.

  FIG. 12 shows an example of the correspondence between the setting value of the DMCR 304 and the extended data.

  In this case, the DMID [7: 0] is stored in the extended array 3022 [7: 0] by setting the value of the DMCR 304 to “0”. On the other hand, by setting the value of the DMCR 304 to “0”, DMID [3: 0] is stored in the extended array 3022 [3: 0] and the ECC code [ 3: 0] is stored, and the cache memory 302 is a cache memory corresponding to an ECC memory having a 4-bit protection domain (DMID) and a 4-bit redundant code.

  The comparison unit 3025 determines a cache hit or miss in the same way as the comparison unit 1025 when the CPU 101 performs a read access. At this time, the comparison unit 1025 compares the extension data EXT [7: 0] and DMID [7: 0]. The comparison is performed by comparing the DMID upper DMID [7: 4] and the extension data. Are divided into the comparison of the higher-order extension data EXT [7: 4] and the lower-order DMID [3: 0] of the DMID and the lower-order extension data EXT [3: 0] of the extension data.

  The comparison unit 3025 is supplied with the tag information TAG, the valid bit, and the extension data EXT for each way from the extension array 3022 and the tag array 1023 when the CPU 101 performs a read access. Further, the comparison unit 3025 inputs UPADR, LPADR, DMID, and DMCR 304 values.

  FIG. 13 is an example of a block diagram of the comparison unit 3025.

  The comparison unit 3025 includes comparators 3031 to 3033 and a logic unit 3034.

  The comparator 3031 compares the LPADR and the tag information TAG for each way, and outputs a comparison result coincidence if the comparison results match, and a comparison result disagreement for each way otherwise. The comparator 3032 compares the lower-order DMID [3: 0] and the lower-order extended data EXT [3: 0] for each way, and if the comparison results match, the comparison result matches. Otherwise, a comparison result mismatch is output for each way. Further, the comparator 3033 compares the higher-order DMID [7: 4] and the higher-order extended data EXT [7: 4] for each way, and if the comparison results match, the comparison result matches. Otherwise, a comparison result mismatch is output for each way.

  The logic unit 3034 receives the comparison results of the comparators 3031 to 3033 and outputs a cache hit / cache miss as a signal HIT for each way. At this time, the logic unit 3034 receives the value of the DMCR 304 and determines whether the comparison result of the comparator 3033 is valid or invalid according to the value of the DMCR 304. That is, in the case of FIG. 12, when the value of the DMCR 304 is “0”, the upper side extension data EXT [7: 4] and the lower side extension data EXT [3: 0] are both DMIDs. The comparison result of the unit 3033 is validated, and a cache hit / miss is determined based on the comparison results of all the comparators 3031 to 3033. On the other hand, when the value of the DMCR 304 is “1”, the upper side extension data EXT [7: 4] is an ECC code, and the lower side extension data EXT [3: 0] is a DMID. That is, since the comparison unit 3033 compares the ECC code and the DMID, the logic unit 3034 invalidates the comparison result, and the cache hit / miss is performed based on the comparison result of the comparator 3031 and the comparator 3032. Judging. In order to determine validity / invalidity of the comparison result of the comparison unit 3033, for example, as shown in FIG. 13, the logical sum of the comparison result of the comparison unit 3033 and the value of the DMCR 304 may be taken for each way.

  The error correction logic unit (ECR) 3027 detects and corrects an error in the data DATA provided from the data array 1024 when the CPU 101 performs a read access. Further, the ECR 3027 selects and outputs either error-corrected data or the data DATA based on the value of the DMCR 304.

  FIG. 14 shows an example of a block diagram of the ECR 3027.

  The ECR 3027 receives the extension data EXT and data DATA for each way as cache line information specified by the index address INDEX from the extension array 3022 and the data array 1024 when the CPU 101 performs read access. Of the received extension data, the higher-order extension data EXT [7: 4] and data DATA are input to the ECC decoding units (ECDECEC) 3028_0 to 3028_3 for each way. The ECC decoding units 3028_0 to 3028_3 perform error correction on the data DATA using the higher-order extension data EXT [7: 4] as necessary, and provide the error-corrected data to the selection circuits 3029_0 to 3029_3. The selection circuits 3029_0 to 3029_3 receive the value of the DMCR 304, and select and output either the error-corrected data or the data DATA based on the value. For example, in the case of FIG. 12, when the value of the DMCR 304 is “0”, the ECC function is invalidated and the data DATA0 to 3 are supplied to the selection unit 1029 as they are. On the other hand, when the value of the DMCR 104 is “1”, the ECC function is enabled, and output data from the ECC decoding units 3028_0 to 3028_3 is selected and supplied to the selection unit 1029.

  The control logic unit 3021 has a write control unit 3026, and the write control unit 3026 has an extended data generation unit (EXTGEN) 3030 in addition to the functions of the write control unit 1026.

  The EXTGEN 3030 stores the extension data in the extension array 3022 when generating a cache entry related to a cache miss and when generating a cache entry at the time of write access. At this time, the EXTGEN 3030 also generates the ECC code.

  FIG. 15 is an example of a block diagram of the extension data generation unit (EXTGEN) 3030. Here, only a circuit block that realizes a function of generating higher-order extension data [7: 4] among the extension data [7: 0] is illustrated.

  For example, when data related to a cache miss is read to generate a cache entry, the data WDATA read from the main storage device 40 is input to an ECC code generation unit (ECCGEN) 3035. The ECCGEN 3035 generates an ECC code of the data WDATA and supplies it to the selection circuit 3036. The selection circuit 3036 selects either the DMID or the generated ECC code based on the value of the DMCR 304 and supplies it to the extended array 3022. For example, in the case of FIG. 12, when the value of the DMCR 304 is “0”, the ECC function is invalidated, and DMID [7: 4] is given to the expansion array 3022 as upper side expansion data [7: 4]. On the other hand, when the value of the DMCR 304 is “1”, the ECC function is validated, and the generated ECC code is given to the extension array 3022 as the upper side extension data EXT [7: 4]. In the case of FIG. 12, the lower side extension data EXT [3: 0] has a value of DMID [3: 0] regardless of the value of DMID.

  According to the data processor 3 according to the third embodiment, the cache memory 302 can select means for improving the reliability of the cache memory in accordance with the application system. That is, it is possible to select whether the use of the extended array of the cache memory 302 is used for improving soft error resistance or for assigning a large number of protection domains from the viewpoint of software.

  In the third embodiment, the ECC using 4 redundant bits for 32 bits of data has been described as an example of the soft error correction method. However, the present invention is not limited to this, and only error detection is performed using 1 redundant bit. It is also possible to apply to a parity system that performs the above.

  In the third embodiment, the case where error correction is performed on the read contents of the data array 1024 is shown as an example. However, the present invention is not limited to this, and it is also possible to perform error correction on the tag information of the tag array 1023. In this case, for example, a circuit for error correction may be disposed between the tag array 1023 and the comparison unit 3025.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the data processors of the first to third embodiments, the access to the main storage devices 40 and 41 has been described as an example. However, the present invention is not limited to this, and the buses 50 and 21 include the main storage devices 40 and 41. It is possible to arrange shared resources such as peripheral devices and input / output devices other than the above, and the access management to these resources is performed by the main storage devices 40 and 41 by the PAMs 30 and 31 installed for each resource. Can be managed and protected in the same way.

  In the data processors according to the first to third embodiments, the DMID and the upper physical address, and the DMID and the ECC code can be switched as the extension data. However, the present invention is not limited thereto, and the three data Can be switched. For example, the data stored in the extended array in the second embodiment may be a protection domain and an ECC code, and these may be switched, or the data stored in the extended array in the third embodiment may be changed to an upper physical address. And ECC codes, which can be switched.

  Further, in the data processors of the first to third embodiments, the case where the expansion array is applied to the cache memory has been shown. Is possible. For example, as one example, the present invention can be applied to a TLB (Translation Look-aside Buffer) which is a typical configuration example of a memory management unit (MMU). In a data processor that supports virtual memory, the MMU generally has a virtual address to physical address translation function, and the TLB is a part of an address translation table that constitutes a virtual memory subsystem of an operating system. It is stored in a high-speed associative memory, and a physical address is searched using a virtual address as a search key. In a data processor having a domain protection function capable of executing a plurality of operating systems, it is determined to which protection domain a virtual address-to-physical address translation pair held in the TLB belongs, and unauthorized memory access Must be shut off. Therefore, like the cache memory described above, it is necessary to add a protection domain (DMID) to the TLB and store it. Therefore, by providing the DMCR in the data processor and the expansion array in the TLB, the memory protection function by the protection domain, the expansion of the virtual address space corresponding to the cache tag, and the error of the RAM constituting the TLB It is possible to easily switch between the correction function and the same effect as described above.

  As another example, the expansion array or the like can be applied to a data processor including a DMAC (Direct Memory Access Controller) that performs data transfer instead of the CPU. For example, a register that sets transfer conditions when the CPU requests transfer to the DMAC has the same function as the expansion array. As a result, the DMAC can easily switch the memory protection function by the protection domain, the expansion of the address space, and the like, and has the same effect as described above.

1-3 Data processor 10, 20_A-20_C Processor core 30, 31 Physical address management module 40, 41 Main storage device 50, 51 Bus 101 CPU
102, 302 Cache memory 103 Domain ID register 104, 304 Domain control register 105 MMU
106, 206 Bus interface 107, 107A to 107C Complement register 1021, 3021 Control logic unit 1022, 3022 Expansion array 1023 Tag array 1024 Data array 1025, 3025 Comparison unit 1026, 3026 Write control unit 1027 Extended function selector 1030, 1031 Comparator 3027 Error Correction logic unit 3028_0 to 3028_3 ECC decoding unit 3029_0 to 3029_3 selection circuit 3030 extended data generation unit 3031 to 3033 comparator 3034 logic unit 3035 ECC code generation unit 3036 selection circuit

Claims (16)

A central processing unit for executing the program;
An associative memory for holding a part of data on the address space of the central processing unit;
A data processor having a first register for holding an identifier used for memory protection,
The associative memory is indexed with a plurality of associative entries including a tag unit for storing a tag and a data unit for storing data, and information supplied from the central processing unit when accessed by the central processing unit. A comparison unit for comparing the tag with
The content addressable memory has a first operation mode in which the supplied information is address information and a second operation mode in which the supplied information is address information and the identifier. A second register holding information for determining the operation mode of the associative memory;
The tag part has an address part for storing address information and an extension part,
The associative memory determines the operation mode based on a value of the second register;
The data processor according to claim 1, wherein the extension unit stores address information in the first operation mode, and stores the identifier in the second operation mode.   In the first operation mode, the comparison unit compares the supplied address information with the address information held in the address unit and the extension unit in the associative entry corresponding to the address information, and matches. In the case, the associative memory outputs the data of the data part in the associative entry, and if not, stores the supplied address information and the corresponding data in the corresponding associative entry. The data processor according to claim 2.   In the second operation mode, the comparison unit compares the supplied address information with information held in the address unit in the associative entry corresponding to the address information, and the supplied identifier And the information held in the extension part in the associative entry are compared, and if both match, the associative memory outputs data of the data part in the associative entry, and one or both do not match The data processor according to claim 2, wherein the supplied address information and data corresponding thereto are stored in the corresponding associative entry.   The data processor according to claim 2, wherein the identifier used for memory protection is a domain identifier for identifying higher-order software that manages execution of the program. A plurality of data processing units each including the central processing unit, the associative memory, the first register, and the second register;
The data processor according to claim 2, wherein the second register can be set for each data processing unit. A bus commonly used by each of the data processing units;
The data processing unit stores an access control unit that performs control for outputting address information supplied by the central processing unit in response to an access request from the central processing unit, and information for complementing the address information. And a third register
The bus has a bus width equal to or larger than a bus width corresponding to a maximum address space among the plurality of data processing units,
When the central processing unit makes an access request, the access control unit determines that the address width based on the address information supplied by the central processing unit is smaller than the bus width. 7. The data processor according to claim 6, wherein new address information obtained by complementing predetermined information to the address information is output to the bus based on the value.   The data processor according to claim 7, wherein the access control unit further performs control to output a value of the first register in response to an access request of the central processing unit. The third register further stores information for complementing the value of the first register,
The bus further has a bus width equal to or greater than a bus width corresponding to a maximum data amount of an identifier used for memory protection among the plurality of data processing units,
When the central processing unit makes an access request, the access control unit determines that the value of the first register is smaller than the bus width, based on the value of the third register. 9. The data processor according to claim 8, wherein new information obtained by complementing predetermined information to a value of one register is output to the bus.   The data processor according to claim 7 or 9, wherein the access control unit determines the number of bits to be complemented with reference to a value of the second register. A central processing unit for executing the program;
An associative memory for holding a part of the data on the address space of the central processing unit,
The associative memory is indexed with a plurality of associative entries including a tag unit for storing a tag and a data unit for storing data, and information supplied from the central processing unit when accessed by the central processing unit. A comparison unit for comparing the tag with
The associative memory has a first operation mode in which the supplied information is address information, and a second operation mode in which the supplied information is address information and error correction information. Processor. A first register holding information for determining the operation mode of the associative memory;
The tag part has an address part for storing address information and an extension part,
The associative memory determines the operation mode based on a value of the first register;
The data processor according to claim 11, wherein the extension unit stores address information in the first operation mode and stores information for error correction in the second operation mode.   The data processor according to claim 2 or 12, wherein the associative memory is a cache memory.   13. The data processor according to claim 2, wherein the associative memory is an address translation buffer that stores an address translation pair for translating a virtual address in a virtual address space of the central processing unit into a physical address. A central processing unit for executing the program;
An internal module that outputs address information for accessing the address space of the central processing unit based on data processing by the central processing unit;
A data processor having a first register for holding an identifier used for memory protection,
The internal module has a first operation mode in which the identifier is not added to the address information, and a second operation mode in which the identifier is added to the address information. A second register holding information for determining the operation mode;
The internal module determines the operation mode based on a value of the second register;
16. The data processor according to claim 15, wherein the identifier used for memory protection is a domain identifier for identifying higher-order software that manages execution of the program.

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