JP2011176009A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for suppressing a leakage current, even when a negative voltage is applied to a gate pad formed on a semi-insulating substrate and a positive voltage is applied to a back electrode formed on the backside of the semi-insulating substrate. <P>SOLUTION: A plurality of gate electrodes 15 formed in parallel on the surface of the semi-insulating substrate 11 with the back electrode 10 formed thereon are connected to gate electrode connections 21, and also the gate electrode connections 21 are divided into a plurality of parts concerning a semiconductor device. The semiconductor device includes: n-type resistance layers 22 formed on the surface of the semi-insulating substrate 11 between the gate electrode connections 21; p-type impurity layers 23 for covering the circumferences of the n-type resistance layers 22; and n-type impurity layers 24 which cover the circumferences of the p-type impurity layers 23 and are formed at a desired concentration. The gate pad 29 is formed to connect the gate electrode connections 21 to extraction electrodes 25 on the n-type resistance layers 22 adjacent to the gate electrode connections 21. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a plurality of transistors are formed in parallel on a substrate.

  A conventional semiconductor device having excellent high-frequency characteristics and capable of high gain includes a plurality of field effect transistors (hereinafter referred to as FETs) on a semi-insulating compound semiconductor substrate (hereinafter referred to as a semi-insulating substrate) such as GaAs. Are provided in parallel. In this semiconductor device, each electrode (drain electrode, source electrode, gate electrode) constituting each FET is connected to each electrode connection portion (drain electrode connection portion, source electrode connection portion, gate electrode connection portion). . An insulating film is formed on the semi-insulating substrate on which the FET is formed so that each electrode connection portion is exposed, and an electrode pad (drain) is formed on each exposed electrode connection portion. Pad, source pad, and gate pad). Further, on the back surface of the semi-insulating substrate, a back electrode that penetrates the semi-insulating substrate and is electrically connected to the source pad is provided.

  When a high-frequency signal is input to such a semiconductor device, a loop oscillation occurs in the device, causing a problem that a signal having a frequency other than a desired frequency is amplified. Here, the loop oscillation is a phenomenon in which a standing wave having a frequency corresponding to the length of this path is generated in an electrically closed path in the apparatus.

  Therefore, conventionally, the gate electrode connection portion is divided into a plurality of parts, and a relatively high-concentration n-type resistance layer, for example, is formed in a strip shape at a position between these gate electrode connection portions on the surface of the semi-insulating substrate The gate pad is formed so that the gate electrode connecting portion and the ohmic electrode formed on the surface of the resistance layer are connected. (See Patent Documents 1 and 2).

  In the above-described configuration, by dividing the gate electrode connection portion into a plurality of parts, the length of the electrically closed path in the device is shortened, so that the generation of standing waves is suppressed and loop oscillation is suppressed. .

  Further, in the above structure, even when a potential difference is generated between the gate pads, the resistance layer absorbs unnecessary power based on the potential difference, so that the potential difference between the gate pads can be reduced. As a result, each FET can be operated uniformly.

JP-A-4-45547 JP 2001-274415 A

  In the semiconductor device described above, when a negative potential is applied to the gate pad and the back electrode is 0 V, there is a problem in that a leakage current is generated between the gate electrode connection portion and the back electrode via the resistance layer. is there. As a result, the performance of the semiconductor device deteriorates.

  On the other hand, in the semiconductor device described above, it is necessary to efficiently radiate the heat generated in the FET to the outside. In order to realize this, it is generally known that the semi-insulating substrate should be thin. It has been. However, if the semi-insulating substrate is made thin in order to obtain a high-efficiency heat dissipation effect, the amount of leakage current described above increases, which also deteriorates the performance of the semiconductor device.

  Therefore, according to the present invention, a negative voltage is applied to the gate electrode pad electrically connected to the resistance layer, and the occurrence of leakage current can be suppressed even when the back electrode is 0V. It is to provide a semiconductor device.

  A semiconductor device according to the present invention includes a plurality of drain electrodes and a plurality of source electrodes alternately formed on a semi-insulating substrate, and a plurality of gate electrodes formed between the drain electrodes and the source electrodes, respectively. A plurality of gate electrode connecting portions connected to these gate electrodes, a plurality of lead electrodes formed between these gate electrode connecting portions, and a drain pad electrically connected to the plurality of drain electrodes, An insulating film formed on the semi-insulating substrate so that a source pad electrically connected to the plurality of source electrodes, the plurality of gate electrode connection portions, and the plurality of lead electrodes are exposed; A plurality of gate pads respectively formed so as to contact the gate electrode connecting portion and the lead electrode adjacent to the electrode connecting portion; The first conductive type resistance layer formed on the semi-insulating substrate so as to be in contact with the plurality of lead electrodes formed between the electrode connection portions, and the periphery including the lower surface of the resistance layer so as to cover the periphery The first conductivity type first impurity layer formed on the semi-insulating substrate so as to cover the first impurity layer of the second conductivity type formed on the semi-insulating substrate and the periphery including the lower surface of the first impurity layer. 2 impurity layers and a back electrode formed on the back surface of the semi-insulating substrate and electrically connected to the source pad. Impurities in the first impurity layer and the second impurity layer The concentration is such that when a negative voltage is applied to the gate pad and the back electrode is 0 V, a voltage is applied between these impurity layers, and the resistance layer and the first impurity layer The concentration at which a potential barrier is formed between It is an feature.

  According to the semiconductor device of the present invention, the impurity layer having a desired impurity concentration is formed around the resistance layer between the gate electrode connection portions divided into a plurality of parts. Thereby, a negative voltage is applied to the electrode pad on the gate electrode connecting portion, and a potential barrier is formed in the resistance layer and the impurity layer even when the back electrode is 0V. Therefore, even when a negative voltage is applied to the gate electrode pad and the back electrode is 0 V, the leakage current generated based on this potential difference can be suppressed.

It is a top view which shows the semiconductor device which concerns on embodiment of this invention. It is sectional drawing shown along the dashed-dotted line AA 'of FIG. It is a top view which expands and shows a part of FIG. FIG. 2 shows a relationship between a cross section taken along one-dot chain line BB ′ in FIG. 2 and a potential formed by this cross section, and FIG. 2A is a cross sectional view showing a part of the cross section in a band shape. b) is a diagram showing the potential. FIG. 2 shows a relationship between a cross section taken along one-dot chain line BB ′ in FIG. 2 and a potential formed by this cross section, and FIG. 2A is a cross sectional view showing a part of the cross section in a band shape. b) is a diagram showing the potential.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a top view showing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, in the semiconductor device of this embodiment, a plurality of field effect transistors 12 (hereinafter referred to as FETs 12), for example, are arranged in parallel on the surface of a semi-insulating substrate 11 as a plurality of transistors. Has been. Further, a Ti layer, for example, is formed on the back surface of the semi-insulating substrate 11, and an Au layer, for example, is formed on the back surface of the semi-insulating substrate 11 via the Ti layer. A back electrode 10 (not shown in FIG. 1) is formed by the Ti layer and the Au layer. The semi-insulating substrate 11 is a compound semiconductor substrate formed of a material having excellent high frequency characteristics such as a GaAs substrate.

  Each FET 12 includes a drain electrode 13, a source electrode 14, and a gate electrode 15 that are parallel to each other, and a gate electrode 15 is formed between the drain electrode 13 and the source electrode 14. Each of these electrodes 13, 14, 15 is formed so as to cross over the element region 16 formed in a strip shape on the semi-insulating substrate 11. The element region 16 is a region appropriately formed so that, for example, the FET 12 performs a desired operation.

  Here, for example, attention is focused on the FET 12 shown in FIG. At this time, the FET 12 and the left FET 12 adjacent thereto are formed so as to share the source electrode 14 with each other. Further, the FET 12 shown in FIG. 1 and the right-side FET 12 adjacent thereto are formed so as to share the drain electrode 13. Thus, the plurality of FETs 12 are arranged so as to share the source electrode 14 or the drain electrode 13 with adjacent FETs. The drain electrode 13 and the source electrode 14 are made of, for example, ohmic metal in which AuGe and Pt are stacked in this order. The gate electrode 15 is made of, for example, a Schottky metal in which Al and Ti are stacked in this order. The gate electrode 15 may be a Schottky metal in which Ti, Al, and Ti are stacked in this order. Thus, when the uppermost layer is a Ti layer, for example, when an insulating film (not shown) is formed on the gate electrode 15, the adhesion between the gate electrode 15 and the insulating film (not shown) is improved. Can be made.

  The plurality of drain electrodes 13 described above are connected to a drain electrode connection portion 17 formed on the semi-insulating substrate 11. Similarly, the plurality of source electrodes 14 are connected to a source electrode connection portion 18 formed on the semi-insulating substrate 11. The plurality of gate electrodes 15 are connected to a gate bus line 19 formed on the semi-insulating substrate 11. The gate bus line 19 is connected to the gate electrode connection portion 21 through a plurality of lead lines 20. Thus, the plurality of gate electrodes 15 are electrically connected to the gate electrode connection portion 21. The drain electrode connecting portion 17 is integrally formed of the same material as the plurality of drain electrodes 13. Similarly, the source electrode connection portion 18 is integrally formed of the same material as the plurality of source electrodes 14. Further, the gate electrode connection portion 21, the gate bus line 19, and the plurality of lead lines 20 are integrally formed of the same material as the plurality of gate electrodes 15.

  The drain electrode connection portion 17, the source electrode connection portion 18, the gate bus line 19, the plurality of lead lines 20, and the gate electrode connection portion 21 are each formed outside the element region 16 on the semi-insulating substrate 11. Among these, the drain electrode connection portion 17 is formed along the longitudinal direction of the element region 16. Further, the source electrode connecting portion 18 is formed along the longitudinal direction of the element region 16 at a position facing the drain electrode connecting portion 17 with the element region 16 therebetween. Furthermore, the gate bus line 19 is formed along the longitudinal direction of the element region 16 at a position between the source electrode connection 18 and the element region 16, and the gate electrode connection 21 is connected to the source electrode connection 18. Is formed along the longitudinal direction of the element region 16 at a position facing the gate bus line 19 with a gap therebetween. The plurality of lead lines 20 are formed between the gate bus line 19 and the gate electrode connection portion 21 in a direction perpendicular to the longitudinal direction thereof. And the gate electrode connection portion 21 are electrically connected.

  The plurality of source electrodes 14 are formed so as to be electrically insulated from each other at positions intersecting the gate bus lines 19. Similarly, the source electrode connection portion 18 is formed so as to be electrically insulated from each other at a position intersecting with the plurality of lead lines 20. Specifically, for example, the plurality of source electrodes 14 are formed in an air bridge shape on the gate bus line 19. Alternatively, it is formed on the gate bus line 19 via an insulator. The same applies to the source electrode connecting portion 18.

  Here, the gate bus line 19 and the gate electrode connection portion 21 are divided into a plurality of parts. The number of divisions of the gate electrode connection portion 21 is appropriately determined according to the carrier frequency of the high frequency signal input to the device. Although FIG. 1 shows an example in which the gate bus line 19 and the gate electrode connection portion 21 are divided into two parts, actually, for example, in a device in which about 100 to 200 FETs 12 are formed in total. When a 10 GHz RF signal is input, the gate bus line 19 and the gate electrode connection portion 21 are divided into, for example, several to several tens.

  Below, the divided | segmented part of the gate electrode connection part 21 is demonstrated with reference to FIG. 2 is a cross-sectional view taken along one-dot chain line AA ′ in FIG. As shown in FIG. 2, a strip-shaped resistance layer 22 is formed on the surface of the semi-insulating substrate 11 between the gate electrode connection portions 21 divided into a plurality of portions. The resistance layer 22 is, for example, a relatively high concentration n-type impurity layer. Further, the p-type impurity layer 23 is formed on the semi-insulating substrate 11 so as to cover the side surface and the lower surface of the resistance layer 22 and to be partially exposed from the semi-insulating substrate 11. Further, the n-type impurity layer 23 is formed on the semi-insulating substrate 11 so as to cover the side surface and the lower surface of the p-type impurity layer 23 and to be partially exposed from the semi-insulating substrate 11.

  FIG. 3 is an enlarged top view showing a part of FIG. 1 in order to explain the p-type impurity layer 23 and the n-type impurity layer 24 in more detail. As shown in FIG. 3, the p-type impurity layer 23 is formed so as to cover the periphery of the resistance layer 22, and the n-type impurity layer 24 is formed so as to cover the periphery of the p-type impurity layer 23.

  The resistance layer 22, the p-type impurity layer 23, and the n-type impurity layer 24 are formed, for example, in the order of the n-type impurity layer 24, the p-type impurity layer 23, and the resistance layer 22. However, this order is not necessarily required. The impurity concentration of the formed n-type impurity layer 24 and p-type impurity layer 23 is such that when a negative voltage is applied to a gate pad 29 described later and the back electrode 10 is 0 V, a voltage is applied between them, In addition, the concentration is determined so that a potential barrier is formed between the resistance layer 22 and the p-type impurity layer 23.

On the resistance layer 22 formed as described above, an extraction electrode 25 made of an ohmic metal having ohmic properties with respect to the resistance layer 22 is formed as shown in FIG. Further, on the semi-insulating substrate 11 on which the plurality of FETs 12, the electrode connection parts 17, 18, 21 and the extraction electrode 25 shown in FIG. The lead electrode 25 is exposed on the surface, and a protective film 26 having an opening is formed in a region where a source pad 28 described later is formed. The protective film 26 is made of, for example, silicon nitride (SiN) or silicon oxide (SiO ₂ ), and has a thickness of about 200 nm, for example. Electrode pads are respectively formed in the opening portions of the protective film 26. That is, a drain pad 27 is formed on the drain electrode connection portion 17, and a plurality of source pads 28 are formed so as to be in contact with the source electrode connection portion 18. The plurality of source pads 28 are integrally formed simultaneously with the source electrode connecting portion 18.

  The above-described source pad 28 is electrically connected to the back electrode 10 through a through hole (not shown) penetrating the semi-insulating substrate 11.

  As shown in FIG. 2, the gate pad 29 is extended from the gate electrode connection portion 21 to a position including the extraction electrode 25 adjacent to the connection portion 21. Accordingly, each gate electrode connection portion 21 divided into a plurality of portions and the extraction electrode 25 adjacent to the connection portion 21 are electrically connected by each gate pad 29. Further, each of the divided gate electrode connection portions 21 is electrically connected via each gate pad 29, the extraction electrode 25, and the resistance layer 22.

  In addition, about the manufacturing method of the above-mentioned semiconductor device, each structure should just be formed by the method generally known, and the manufacturing method of each structure, the order of manufacture, etc. are not limited.

  Here, when no voltage is applied to the gate pad 29, the potential formed by the layers 22, 23, and 24 is formed as shown in FIG. FIG. 4 shows the relationship between the cross section taken along the alternate long and short dash line BB ′ of FIG. 2 and the potential formed by this cross section. FIG. 4A is a cross-sectional view showing a part of the cross section in a band shape, and FIG. 4B is a view showing potential. In FIG. 5B, the solid line with the shallow potential indicates the conduction band, the solid line with the deep potential indicates the valence band, and the dotted line indicates the Fermi level.

  As shown in FIG. 4B, the potential formed by the resistance layer 22 and the n-type impurity layer 24 is substantially equal, but the potential formed by the p-type impurity layer 23 is the resistance layer 22 and the n-type impurity layer. 24 is formed shallower than the potential formed by. The potential formed by the semi-insulating substrate 11 is formed between the n-type impurity layer 24 and the p-type impurity layer 23 so as to have a gradient that becomes shallower toward the back electrode 10 side.

  Next, when a negative voltage is applied to the gate pad 29 and the back electrode 10 is at 0 V, the potential formed by the layers 22, 23, and 24 is formed as shown in FIG. FIG. 5A is the same cross-sectional view as FIG. 4A, and FIG. 5B is a diagram showing the potential. In FIG. 4B, the solid line with the shallow potential indicates the conduction band, the solid line with the deep potential indicates the valence band, and the dotted line indicates the Fermi level, as in FIG. 4B.

  As shown in FIG. 5B, when a negative voltage V is applied to the gate pad 29, a voltage is applied between the n-type impurity layer 24 and the p-type impurity layer 23, and a relatively n-type impurity layer is applied. A potential that deepens the potential of 24 is formed. At this time, a potential barrier 41 is formed between the resistance layer 22 and the p-type impurity layer 23.

  As described above, in the semiconductor device of the present embodiment, the p-type impurity layer 23 is formed at a desired concentration around the resistance layer 22, and the n-type impurity at the desired concentration around the p-type impurity layer 23. Layer 24 is formed. As a result, a negative voltage is applied to the gate pad 29, and the potential barrier 41 is formed between the resistance layer 22 and the p-type impurity layer 23 even when the back electrode 10 is 0V. Therefore, even when a negative voltage is applied to the gate pad 29 and the back electrode 10 is 0 V, a leak current flows between the gate electrode connection portion 21 and the back electrode 10 via the resistance layer 22. This can be suppressed.

  In addition, since the potential barrier 41 is formed as described above, it is possible to suppress a leakage current from flowing, and thus the semi-insulating substrate 11 can be thinned. As a result, the heat generated in the plurality of FETs 12 can be efficiently radiated, and the heat dissipation of the device can be improved.

  Further, for example, even if the back electrode 10 is formed on the side surface of the semi-insulating substrate 11 against the circumstances for manufacturing, the gate electrode 21 and the back surface formed on the side surface of the semi-insulating substrate 11 are used. Generation of a leakage current between the electrode 10 and the electrode 10 can be suppressed.

  The semiconductor device according to the embodiment of the present invention has been described above. However, the semiconductor device according to the embodiment of the present invention is not limited to the above-described embodiment.

  For example, the resistance layer 22, the p-type impurity layer 23, and the n-type impurity layer 24 may have opposite conductivity types. In this case, the lead electrode 25 made of ohmic metal needs to be applied with a metal that is ohmic to the p-type resistance layer 22.

  Further, the present invention can also be applied to a semiconductor device formed in the same manner as the drain pad 25 or the gate pad 27 so that the source pad 28 is in contact with the source electrode connection portion 18.

DESCRIPTION OF SYMBOLS 10 ... Back electrode 11 ... Semi-insulating substrate 12 ... Field effect transistor 13 ... Drain electrode 14 ... Source electrode 15 ... Gate electrode 16 ... Element region 17 ... Drain Electrode connection 18 ... Source electrode connection 19 ... Gate bus line 20 ... Lead line 21 ... Gate electrode connection 22 ... Resistance layer 23 ... p-type impurity layer 24 ... n-type impurity layer 25 ... extraction electrode 26 ... protective film 27 ... drain pad 28 ... source pad 29 ... gate pad

Claims (2)

A plurality of drain electrodes and a plurality of source electrodes alternately formed on the semi-insulating substrate;
A plurality of gate electrodes respectively formed between the drain electrode and the source electrode;
A plurality of gate electrode connections connected to these gate electrodes;
A plurality of extraction electrodes formed between the gate electrode connection portions;
The drain pad electrically connected to the plurality of drain electrodes, the source pad electrically connected to the plurality of source electrodes, the plurality of gate electrode connection portions, and the plurality of lead electrodes are exposed. A protective film formed on the semi-insulating substrate;
A plurality of gate pads respectively formed to contact the gate electrode connecting portion and the lead electrode adjacent to the electrode connecting portion;
A resistance layer of a first conductivity type formed on the semi-insulating substrate so as to be in contact with the plurality of lead electrodes formed between the gate electrode connection portions;
A first impurity layer of a second conductivity type formed on the semi-insulating substrate so as to cover the periphery including the lower surface of the resistance layer;
A first conductivity type second impurity layer formed on the semi-insulating substrate so as to cover the periphery including the lower surface of the first impurity layer;
A back electrode formed on the back surface of the semi-insulating substrate and electrically connected to the source pad;
Comprising
The impurity concentration of the first impurity layer and the second impurity layer is such that when a negative voltage is applied to the gate pad and the back electrode is 0 V, the voltage between these impurity layers is The semiconductor device has a concentration at which a potential barrier is formed between the resistance layer and the first impurity layer.   2. The semiconductor device according to claim 1, wherein the conductivity type of the resistance layer and the second impurity layer is n-type, and the conductivity type of the first impurity layer is p-type.

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