JP2011170758A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor that can perform high speed calculation, even when executable instructions are increased. <P>SOLUTION: The processor 1 includes an instruction decoder CTRL which classifies the executable instructions into four instruction types of M type instruction, R type instruction, J type instruction, and B type instruction based on the content of processing to be performed according to the instructions. The processor 1 further includes pipeline registers 11-14 provided in association with the instruction types. The instruction decoder CTRL decodes the instruction type of an instruction to be executed based on an identification code included in the instruction. In addition, the instruction decoder CTRL stores data stored in a general-purpose register block REG and a parameter in the instruction into corresponding pipeline registers based on the instruction type of the instruction. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a processor that realizes high-speed computation by pipeline processing.

  In recent years, programmable logic controllers (PLCs), which have high demands for speeding up, can be speeded up by combining a general-purpose microprocessor that performs communication processing and peripheral processing with a dedicated processor that processes instructions such as bit operation processing instructions. Is realized.

This type of processor achieves high speed by executing each instruction such as a basic instruction mainly for bit operation processing and an application instruction that handles data composed of a plurality of bits (for example, , See Patent Document 1). In the PLC described in Patent Document 1, a five-stage pipeline structure is configured by dedicated hardware (processor), and the following processing is performed in each execution stage of pipeline processing.
First stage: Instruction fetch processing for fetching the next instruction to be executed from the instruction memory.
Second stage: instruction decode processing and register fetch processing for fetching a value from a general-purpose register.
Third stage: Any of arithmetic logic operation processing, data address calculation processing, and branch destination calculation processing.
Fourth stage: access processing to the data memory.
Fifth stage: Bit operation processing, general-purpose register write processing, or branch processing.

Japanese Patent No. 3000857

  By the way, the instruction processing time in the processor as described above is determined by the processing time of the execution stage having the longest processing time among the execution stages of the pipeline processing. In order to achieve high speed, it is necessary to set the processing time in each execution stage to be within the time of one clock of the pipeline processing and equal in processing time in each execution stage.

  However, in the above-described conventional processor, pipeline execution is performed using common hardware regardless of the processing contents for each instruction, so that various processing is performed so that processing is not performed by hardware that does not require processing during instruction decoding processing. Control is performed. For this reason, when the number of instructions that can be executed by the processor is increased, the time required for the instruction decoding process becomes longer, and the processing time in the second stage may not be within the time of one clock of the pipeline processing. As a result, for example, as shown in FIG. 3B, the pipeline processing in the subsequent stage is stopped (NOP in the drawing) until the instruction decoding processing (ID in the drawing) is completed in the second stage, and the processing speed is increased. There was a problem of lowering.

  The present invention has been made in view of the above reasons, and an object of the present invention is to provide a processor capable of high-speed computation even when the number of executable instructions is increased.

  In order to achieve the above object, according to the first aspect of the present invention, as hardware constituting each execution stage of the instruction pipeline processing, an instruction memory for storing an instruction to be executed, an instruction to be executed next from the instruction memory, A program counter for storing an address; an instruction register for storing the instruction read from the instruction memory by instruction fetch processing; and an instruction for reading from a general-purpose register based on the instruction stored in the instruction register Decoder, general-purpose register block composed of a plurality of general-purpose registers, a data memory and a memory access interface for controlling access to the data memory, an arithmetic logic unit for performing arithmetic logic operation processing, and a bit operation for performing bit operation processing Multiple pipelines connecting the unit and each execution stage Each instruction type classified based on processing content, and a plurality of instruction type-specific execution stages configured by combining the hardware, and the instruction decoder based on the instruction type It is characterized by branching to the execution stage.

  According to a second invention, in the first invention, the instruction code has an identification code corresponding to the instruction type, and the instruction decoder determines the instruction type based on the identification code. .

  According to the present invention, it is possible to provide a processor capable of high-speed processing even when the number of instructions that can be processed is increased by shortening the time required for instruction decoding.

It is a schematic block diagram which shows the hardware structure of the processor concerning embodiment of this invention. It is the schematic which shows an example of the instruction set and instruction structure of the processor. (A) shows a pipeline structure in the processor, and (b) is a schematic diagram showing a pipeline structure in a conventional processor.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. The processor 1 according to the present embodiment is a processor that achieves high speed by configuring a PLC together with a general-purpose microprocessor that performs communication processing and peripheral processing, and executing various instructions in a pipeline.

  Each instruction processed by the processor 1 is classified into a plurality of instruction types based on the contents of processing performed according to the instruction and resources such as memory accessed at the time of processing. In the present embodiment, the instruction decoder CTRL of the processor 1 to be described later is classified into four instruction types, an M type instruction, an R type instruction, a J type instruction, and a B type instruction.

  As shown in FIG. 2, the structure of each instruction includes an identification code field, an op code field following the identification code, and a parameter field following the op code field. The value has been determined. The op code is set to a value that does not overlap if the same instruction type is not used, and the instruction can be uniquely derived from both the identification code and the op code.

  Here, the M type instruction is an instruction mainly including access to a value stored in the data memory 3 (see FIG. 1), and 00 is set as the identification code in binary. The parameter field of the M type instruction includes a src1 field, a dst1 field, and an offset field. Specifically, an effective address is obtained from the value of the register specified in the src1 field and the value of the offset field, and the value stored in the data memory 3 is read out to the general-purpose register specified in the dst1 field. Command (LOAD command).

  The R type instruction is an instruction that mainly performs an operation between general-purpose registers or an operation between a value of a general-purpose register and a constant, and the identification code is set to 01 in binary. The parameter field of the R type instruction includes a src1 field, a src2 field, a dst1 field, and a function field. Specifically, an instruction that performs the process of writing the sum of the general register value specified in the src1 field and the general register value specified in the src2 field to the general register specified in the dst1 field (ADD instruction) Etc. The function field is used, for example, for designating detailed specifications of the calculation method.

  The J-type instruction is an instruction that mainly compares values and constants of general-purpose registers and performs branch processing according to the comparison result, and the identification code is set to 10 in binary. The parameter field of the J type instruction is composed of a src1 field, a src2 field, and an offset field. Specifically, the value of the general-purpose register specified in the src1 field is compared with the value of the general-purpose register specified in the src2 field. If they are equal, the value of the offset field is added to the program counter PC to branch. An instruction to perform processing (BE instruction).

  The B type instruction is an instruction mainly for performing bit operation, the identification code is set to 11 in binary, and its parameter field is configured by a Bit Processing Instruction field. Specifically, an instruction (SET instruction) for performing processing such as setting a specific bit to 1 is used.

  In conventional processors, instructions such as ANDI that perform operations between values stored in general-purpose registers and existing values are classified separately from instructions such as AND that perform operations between registers. In the present embodiment, the hardware that performs processing for any instruction can be shared, so both are classified into R type instructions, and each instruction is classified into four instruction types.

  In this way, the processor 1 can classify each instruction to be processed into four instruction types and determine which instruction type the instruction is based on the identification code included in the instruction. Table 1 shows specific examples of instructions included in each instruction type.

  Next, an outline of pipeline processing in the processor 1 will be described with reference to FIG. The processor 1 executes pipelined instruction execution stages composed of first and second stages in which common processing is performed regardless of the instruction type, and third to fifth stages having different processing contents for each instruction type. is doing.

  In the first stage, an instruction fetch process (IF in FIG. 3A) for fetching an instruction to be executed from the instruction memory 2 is performed according to the value of the program counter PC. In the second stage, the instruction type is determined from the instruction, branching to the third stage according to the instruction type is performed, and a necessary value is extracted from the general-purpose register block REG and output to the corresponding pipeline register ( ID in FIG. 3A is performed.

  In the third stage, when the instruction to be executed is an M-type instruction, processing for calculating an address for accessing the data memory 3 from the contents of a pipeline register 11 described later (M_EX in FIG. 3A) is performed. . In the case of an R-type instruction, processing (R_EX in FIG. 3A) is performed based on the contents of a pipeline register 12 described later to perform an arithmetic logic operation on the corresponding register value and existing value. In the case of a J-type instruction, a process of comparing and determining the corresponding register and the existing value (J_EX in FIG. 3A) is performed based on the contents of a pipeline register 13 described later. In the B type instruction, processing (B_MA in FIG. 3A) for reading out data to be calculated from the data memory 3 is performed based on the contents of a pipeline register 14 to be described later.

  In the fourth stage, when the instruction to be executed is an M-type instruction, the process of reading the data to be calculated from the data memory 3 based on the address calculated in the third stage (M_MA in FIG. 3A) Done. In the case of an R type instruction, processing (R_WB in FIG. 3A) for storing the operation result in the third stage in the general-purpose register block REG is performed. In the case of a J-type instruction, a process (J_WB in FIG. 3A) for outputting the address (branch address) of the instruction to be processed next to the instruction memory 2 is performed based on the comparison result in the third stage. Is called. In the case of the B type instruction, a process of performing bit operation on the data read in the third stage and writing it into the general-purpose register block (B_WB in FIG. 3A) is performed.

  In the fifth stage, when the instruction to be executed is an M-type instruction, the data read in the fourth stage is calculated and written into the general-purpose register block (M_WB in FIG. 3A). In the case of an R type instruction, a J type instruction, and a B type instruction, the process is completed in the fourth stage, and therefore the process is not performed (NOP in FIG. 3A).

  Next, the hardware configuration of the processor 1 will be described with reference to FIG.

  The processor 1 receives a signal from the instruction memory 2 for storing the instruction to be executed and the program counter control circuit PC-CAL, and calculates the address of the instruction memory 2 in which the instruction to be executed next is stored. With. The processor 1 also includes pipeline registers ID / M_EX, ID / R_EX, ID / J_EX, ID / B_MA, M_EX / M_MA, R_EX / R_WB, J_EX / J_WB, M_MA / between pipeline execution stages. R_WB, B_MA / B_WB (11 to 19 in FIG. 1).

  Pipeline registers 11, 15, and 16 are used when processing M-type instructions, respectively, between the second stage and the third stage, between the third stage and the fourth stage, and between the fourth stage and the fifth stage. It is an intervening pipeline register. Pipeline registers 12 and 17 are pipeline registers that are used when processing R-type instructions, and are interposed between the second stage and the third stage and between the third stage and the fourth stage, respectively. Pipeline registers 13 and 18 are used when processing J-type instructions, and are pipeline registers that intervene between the second stage and the third stage and between the third stage and the fourth stage, respectively. The pipeline registers 14 and 19 are pipeline registers that are used when processing B-type instructions, and are interposed between the second stage and the third stage and between the third stage and the fourth stage, respectively.

  The processor 1 includes an instruction register IR in which an instruction fetched from the instruction memory 2 is stored. The instruction register IR is a pipeline register IF / ID interposed between the first stage and the second stage in pipeline processing. Is also used. The processor 1 fetches the next instruction to be executed from the instruction memory 2 based on either the address calculated by the program counter PC or the branch address output to the instruction memory 2 by the above-described J_WB processing. Store in register IR. These processes correspond to the first stage of pipeline processing.

  The processor 1 also includes a general-purpose register block REG composed of a plurality of general-purpose registers, and an instruction decoder CTRL that determines an instruction type based on an instruction identification code stored in the instruction register IR. The instruction decoder CTRL accesses the general-purpose register block REG according to the determined instruction type, and stores the values read from the general-purpose register block REG and instruction parameter values in the pipeline registers 11 to 14 corresponding to the instruction type. To do. These processes correspond to the second stage of pipeline processing.

  The processor 1 also includes an arithmetic logic unit (hereinafter referred to as an arithmetic unit) ALU, an address calculation register M_EX in which control signals indicating data to be operated and a calculation method are stored, and arithmetic and logic operation registers R_EX and J_EX. Is provided. The arithmetic unit ALU calculates an address for accessing the data memory 3 based on the contents of the address calculation register M_EX, and stores it in the memory access register M_MA included in the processor 1. The arithmetic unit ALU performs an operation based on the contents of the arithmetic logic operation register R_EX or J_EX and outputs the result to the write-back register R_WB or J_WB. These processes correspond to the third stage in the case of an M type instruction, an R type instruction, and a J type instruction in pipeline processing. Note that the address calculation register M_EX, arithmetic and logic operation registers R_EX and J_EX, the memory access register M_MA, and the write-back registers R_WB and J_WB also share the pipeline registers 11, 12, 13, 15, 17, and 18, respectively. .

  The processor 1 includes a data memory 3, a memory access interface 4 that controls access to the data memory 3, and a memory access register B_MA that is also used as the pipeline register 14. The memory access interface 4 reads data from the data memory 3 based on the contents of the memory access registers M_MA and B_MA, and stores them in the pipeline registers 16 and 19. These processes correspond to the fourth stage in the case of the M type instruction in the pipeline process and the third stage in the case of the B type instruction. Note that the write-back register M_WB and the write-back register B_WB are also used as the pipeline register 16.

  The processor 1 also includes a bit operation unit BPU that performs bit operations, and a bit accumulator BITACC that performs invalidation control of application instructions that follow in accordance with the output of the bit operation unit BPU. The bit operation unit BPU performs a bit operation based on the contents of the write back register B_WB, and writes the operation result to the general-purpose register block REG. This process corresponds to the fourth stage in the case of a B type instruction in pipeline processing.

  The processor 1 writes to the general-purpose register block REG based on the contents stored in the write-back registers M_WB and R_WB, and also uses the branch address of the instruction memory 2 based on the contents stored in the write-back register J_WB. Rewrite. This processing corresponds to the fifth stage in the case of the M type instruction in the pipeline processing and the fourth stage in the case of the R type instruction and the J type instruction.

  Each pipeline register IF / ID, 11 to 19 and the program counter PC can be configured by, for example, a rising trigger type D flip-flop.

  As described above, the instruction decoder CTRL can branch the process based on the value set in the instruction identification code field. This identification code does not increase even when the number of instructions that can be processed by the processor 1 increases, and the instruction decoder CTRL can operate at almost the same processing speed as when the number of instructions that can be processed is small. As a result, it is possible to reduce the processing time of the second stage, which mainly includes instruction decoding processing by the instruction decoder CTRL, from being longer than the time for one clock of pipeline processing.

  Note that the hardware structure, instruction set, instruction structure, and identification code are not limited to the configurations described in the present embodiment.

DESCRIPTION OF SYMBOLS 1 Processor 2 Instruction memory 3 Data memory 4 Memory access interface 11 ... 19 Pipeline register
PC program counter
PC-CAL Program counter control circuit
IR instruction register
CTRL instruction decoder
REG General-purpose register block
ALU arithmetic logic unit
BPU bit arithmetic unit
BITACC bit accumulator

Claims (2)

As hardware constituting each execution stage of instruction pipeline processing,
An instruction memory for storing instructions to be executed;
A program counter for storing an address of an instruction to be executed next from the instruction memory;
An instruction register for storing the instruction read from the instruction memory by an instruction fetch process;
An instruction decoder for reading from a general-purpose register based on an instruction stored in the instruction register;
A general purpose register block consisting of multiple general purpose registers;
A data memory and a memory access interface for controlling access to the data memory;
An arithmetic logic unit that performs arithmetic logic processing;
A bit operation unit for performing bit operation processing;
A plurality of pipeline registers that connect each execution stage,
For each instruction type classified based on the processing content, it has a plurality of instruction type execution stages configured by combining the hardware,
The processor, wherein the instruction decoder performs a branch to the execution stage based on the instruction type. The instruction code has an identification code corresponding to the instruction type,
The processor according to claim 1, wherein the instruction decoder determines an instruction type based on the identification code.

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