JP2011159192A - Semiconductor integrated circuit device and program debugging method - Google Patents

Abstract

An object of the present invention is to facilitate program debugging or reduce the cost of program debugging.
A plurality of CPU blocks (CPUBK [0], CPUBK [1],..., CPUBK [n−1], CPUBK [n]) 500a having the same configuration are provided, and a CPUBK is set by a mode setting register (MREG) 210. [0], CPUBK [n−1] are operated in the program execution mode, and CPUBK [1], CPUBK [n] are operated in the debug execution mode. The debug information from CPUBK [0] and CPUBK [n-1] is output via the debug information storage device access controller (DIMAC) 220, and collected via the DIMAC of CPUBK [1] and CPUBK [n]. Is done. The DIMACs of CPUBK [1] and CPUBK [n] have a communication path associated with ring connection, and can transmit / receive debug information and the like to each other.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit device including a microprocessor and a debugging device for supporting program development, and relates to a technique effective for realizing a debugging function and mounting method using the same.

  Support for program development by a debugging device is indispensable for developing applications that become larger and more complex year by year. Currently, a debugging circuit for acquiring debugging information at the time of program execution is incorporated in a CPU (Central Processing Unit), and the information is sent to an external PC (Personal) through an output terminal provided at the edge of the chip. Computer) etc. and analyzing the behavior of the program on an external PC. At this time, the data inside the chip is usually output from the chip edge to the outside of the chip via the pin terminals. However, due to restrictions on the number of pin terminals that can be installed on the chip edge, the chip terminal part has a data output band There is a problem that the output bandwidth is insufficient due to a bottleneck, and therefore all of the debug information acquired from the CPU cannot be extracted to the outside, and only a part of the information can be extracted to the outside. With the progress of multi-core / many-core processors, and the fact that a large number of CPU cores are mounted on a single CPU, the problem of insufficient output bandwidth is becoming increasingly serious. In this regard, Non-Patent Document 1 describes a technique for outputting data inside a chip from the top surface of the chip to the outside of the chip using a wireless interconnect technology. In this technology, the use of the upper surface portion of the chip avoids the conventional bottleneck and succeeds in securing a data output band wider than the conventional one.

"An Attachable Wireless Chip-Access Interface for Arbitrary Data Rate Using Pulse-Based Inductive-Coupling through LSI Package", Hiroki Ishikuro, Toshihiro Sugahaara and Tadahiro Kuroda, IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2007 2 Moon

  The content described in Non-Patent Document 1 of the background art is an approach for expanding the external output band. However, in the current situation where the number of CPUs mounted in one microprocessor is increasing year by year, the speed of increasing the number of CPUs exceeds the speed of expanding the external output band. It is difficult to solve the problem by itself.

  In general, in debugging of a multi-core / many-core processor, it is extremely difficult to output a large amount of debug information obtained from a large number of CPUs in real time to the outside of the chip without omission. Even if it can be output, it is very difficult for the user to find out information necessary for true bug analysis or performance tuning from a large amount of debug information.

  In a multi-CPU, one processing process is generally distributed and executed by a plurality of CPUs, but this also makes debugging difficult. Since one processing process is executed separately by multiple CPUs, it is not possible to know the whole picture of how a certain process was executed with only debug information obtained from one CPU, and only a fragment. . In order to know the whole picture, it is necessary to obtain debug information from a plurality of CPUs and collect the debug information distributed to the plurality of CPUs for each process, which is difficult with the current technology.

  In addition, the explosive increase in the number of CPUs mounted in one microprocessor increases the hardware mounting cost of the debug module. In order to collect a large amount of debug information output from a large number of CPUs in real time and output them to the outside of the chip, it is necessary to route a huge amount of wiring, which alone requires a great amount of hardware cost and mounting cost. .

  The present invention has been made in view of the above, and one of its purposes is to provide a semiconductor integrated circuit device capable of facilitating program debugging or reducing the cost of program debugging. is there. Specifically, for example, it is to provide a technique for extracting and outputting only truly necessary debug information having high importance from a large amount of debug information. Furthermore, it is to provide means for realizing the above technique by adding a small amount of hardware to an existing circuit without adding a large amount of expensive dedicated hardware logic. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The semiconductor integrated circuit device according to the present embodiment includes a plurality of CPUs, and has a configuration in which two modes of “program execution mode” and “debug execution mode” can be defined for each CPU. Here, the “program execution mode” is a mode operating as a normal CPU, and the “debug execution mode” is a mode operating as a debug execution CPU. Each CPU is provided with a mode setting register for setting which one of these two operation modes to operate. As a result, the same CPU can be switched and used as both a program execution CPU and a debug execution CPU simply by switching the setting of the mode setting register.

  Further, two input paths and two output paths for inputting / outputting debug information are added to each CPU. One set of debug information input / output paths added to each two is used for inputting / outputting debug information between the program execution CPU and the debug execution CPU for debugging the processor. . The other set is used to input / output debug information between the debug execution CPUs when operating as a debug execution CPU.

  That is, each CPU (1) input path for receiving information from the program execution CPU during the debug execution mode operation, and (2) information from other debug execution CPUs during the debug execution mode operation. An input path for receiving, (3) an output path for transmitting information to the debug execution CPU during the program execution mode operation, and (4) information to a debug execution CPU other than itself during the debug execution mode operation. The output path for transmitting the data is provided. During the debug execution mode operation, the input paths (1) and (2) and the output path (4) are used, and the output path (3) is not used. Conversely, during the program execution mode operation, only the output path (3) is used, and the input paths (1) and (2) and the output path (4) are not used. By providing these input / output paths, a certain CPU can transmit / receive necessary debug information (or performance tuning information) through a dedicated path during both the program execution CPU operation and the debug execution CPU operation. It becomes possible.

  At the time of debug execution, for example, half of all the CPUs are operated in the program execution mode and the other half are operated in the debug execution mode. A pair of debug execution CPUs are defined for all the program execution CPUs, and the output path (3) of the program execution CPU and the input path (1) of the debug execution CPU are connected. In addition, each debug execution CPU is sequentially connected between adjacent debug execution CPUs, and is connected in a large ring shape as a whole. The output path (4) of each debug execution CPU is connected to the input path (2) of the adjacent debug execution CPU. By connecting the program execution CPU and the debug execution CPU in such a form, debug information can be transmitted from all the program execution CPUs to all the debug execution CPUs with a small additional hardware cost. It becomes possible.

  Furthermore, this large ring-shaped data transmission / reception path is connected to an external output terminal at least at one place. By connecting the debug execution CPU and the external output terminal in such a form, all the debug execution CPUs can be connected to the outside of the chip via the connection portion with the external output terminal at a slight additional hardware cost. Debug execution results (or performance tuning information) can be output.

  When executing debugging, three information transmission / reception modes are defined: (a) information collection mode, (b) information transfer mode, and (c) information output mode. In the information collection mode (a), from the program execution CPU to the debug execution CPU using the connection path from the output path (3) of the program execution CPU to the input path (1) of the debug execution CPU described above. Debug information is sent. In this mode, debug information can be collected from the program execution CPU to the debug execution CPU. In the information transfer mode (b), from the debug execution CPU to the debug execution CPU, the connection path from the output path (4) of the debug execution CPU to the input path (2) of the debug execution CPU described above is used. Debug information is sent. In the information output mode of (c), the connection is in the same form as in (b), but the transferred debug information is not finally written to another CPU for debug execution, but from the external output terminal. Output to the outside.

  Since all the debug execution CPUs are connected in a large ring as described above, the debug information collected in the information collection mode (a) can be transferred to any arbitrary debug execution CPU. It is. Since the CPU for debug execution itself is a normal general-purpose CPU as its name suggests, it is possible to utilize high data processing capability for debugging.

  Furthermore, the semiconductor integrated circuit device according to the present embodiment can be combined with a so-called three-dimensional mounting technique to constitute a very powerful debugging device. Specifically, a plurality of chips composed of a plurality of CPUs and additional circuits for constructing the various paths (1) to (4) described above for each CPU are stacked in a three-dimensional manner. Connect via vias or wireless interconnect technology. Then, the CPU of one of the adjacent chips is operated in the program execution mode, and the CPU of the other chip is operated in the debug execution mode. Thereby, a three-dimensional chip having a high-performance debugging function can be easily configured.

  Further, by using the same chip composed of a plurality of CPUs and the above-described additional circuit for two different uses for program execution and debug execution, it is possible to reduce chip manufacturing costs. . That is, conventionally, it has been necessary to produce a high-performance debug circuit in order to realize a high-performance debug function. However, the use of this embodiment makes it unnecessary to create a high-performance debug circuit. Furthermore, in the past, in order to realize a high-performance debugging function, it was necessary to incorporate a high-performance debugging dedicated circuit into the chip, which was a heavy burden in terms of chip area. If used, such a circuit is not required in the chip. Further, by connecting in three dimensions, for example, products that are actually provided to customers do not require a debugging function, so a product having only one chip layer is shipped, and only two chips are provided for developers who need the debugging function. It is possible to respond such as shipping products for developers with multiple debugging functions. Furthermore, in the 3D packaging technology, if wireless interconnect technology is used instead of through via technology, all chips are shipped with only one layer and operated in the program execution mode, and only when the debugging function is required. By stacking one chip and connecting with wireless interconnect technology, and operating the stacked chip in debug execution mode, a high-performance debugging function can be realized by a very simple means only when necessary. It becomes possible.

  Of the inventions disclosed in the present application, the effects obtained by the representative embodiments will be briefly described. This makes it possible to facilitate program debugging or reduce the cost of program debugging.

1 is a block diagram showing an example of the overall configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a block diagram which shows the characteristic component in the CPU block shown in FIG. It is a block diagram which shows the other characteristic component in the CPU block shown in FIG. (A)-(d) is explanatory drawing which showed four types of operation modes with which the CPU block shown in FIG. 1 is provided. FIG. 2 is an explanatory diagram showing a connection example between a CPU block set in a program execution mode and a CPU block set in a debug execution mode in the semiconductor integrated circuit device of FIG. 1. FIG. 2 is an explanatory diagram showing an example of connection between CPU blocks set in a debug execution mode in the semiconductor integrated circuit device of FIG. FIG. 2 is an explanatory diagram illustrating a specific usage example of the semiconductor integrated circuit device of FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. In the semiconductor integrated circuit device by Embodiment 2 of this invention, it is a block diagram which shows the structural example of each CPU block contained in it. In the semiconductor integrated circuit device by Embodiment 2 of this invention, it is a block diagram which shows the example of the whole structure. (A) is the schematic which shows an example of the mounting form in the semiconductor integrated circuit device of FIG. 13, (b) is a circuit diagram which shows the structural example of the input-output connector in (a). 14 is an explanatory diagram showing a connection example between a CPU block set in a program execution mode and a CPU block set in a debug execution mode in the semiconductor integrated circuit device of FIG. FIG. 14 is an explanatory diagram showing an example of connection between CPU blocks set in a debug execution mode in the semiconductor integrated circuit device of FIG. 13;

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of the overall configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. The semiconductor integrated circuit device of FIG. 1 includes a plurality of CPU blocks (CPUBK) 500a. As an example, FIG. 1 shows four CPU blocks CPUBK [0], CPUBK [1],. ], CPUBK [n] (n = 3, 5,...) Are shown. Each CPU block (CPUBK) 500a includes a central processing unit (CPU) 100 and an additional circuit (AM) 200 for constructing a debugging device. The central processing unit (CPU) 100 includes a control register (CREG) 110, a debug information generation device (DIG) 120, and a debug information storage device (DIM) 130 in order to realize a debug function.

  The control register (CREG) 110 has a function of setting what kind of trace information is to be acquired from the central processing unit (CPU) 100 being executed according to the value written in the register. The debug information generation device (DIG) 120 has a function of taking out debug information from the central processing unit (CPU) 100 in operation according to the setting of the control register (CREG) 110. The debug information storage device (DIM) 130 has a storage holding function for temporarily storing the debug information extracted by the debug information generation device (DIG) 120 inside the central processing unit (CPU) 100.

  The additional circuit (AM) 200 includes a mode setting register (MREG) 210, a debug information storage device access controller (DIMAC) 220, a debug information input path 1 (DI1) 230, a debug information output path 1 (DO1) 240, and a debug information input. A path 2 (DI2) 250 and a debug information output path 2 (DO2) 260 are included. The mode setting register (MREG) 210 has a function of setting which of the two modes of “program execution mode” and “debug execution mode” to the central processing unit (CPU) 100 to operate. When the program execution mode is selected, the central processing unit (CPU) 100 executes an arithmetic processing operation in accordance with a given program in the same manner as when the mode setting register (MREG) 210 is not provided. When the debug execution mode is selected, the central processing unit (CPU) 100 executes a debug execution program instead of a normal program. The debug information storage device access controller (DIMAC) 220 includes a debug information storage device (DIM) 130, a debug information input path 1 (DI1) 230, a debug information output path 1 (DO1) 240, and a debug information input path 2 (DI2). 250 and a debug information output path 2 (DO2) 260 each having a function of controlling input / output of debug information.

  The debug information input path 1 (DI1) 230 is used to transfer the debug information of the central processing unit (CPU) 100 operating in the program execution mode to another central processing unit (CPU) 100 operating in the debug execution mode. Function as an input path. The debug information output path (DO1) 240 is used for transferring debug information of the central processing unit (CPU) 100 operating in the program execution mode to another central processing unit (CPU) 100 operating in the debug execution mode. It functions as an output path. The debug information input path 2 (DI2) 250 transfers debug information of the central processing unit (CPU) 100 that operates in the debug execution mode to another central processing unit (CPU) 100 that also operates in the debug execution mode. It has a function as an input path. The debug information output path 2 (DO2) 260 transfers debug information of the central processing unit (CPU) 100 that operates in the debug execution mode to another central processing unit (CPU) 100 that also operates in the debug execution mode. It has a function as an output path when

  In the example of the semiconductor integrated circuit device of FIG. 1, even-numbered CPU blocks (CPUBK [0],..., CPUBK [n−1]) 500a are set in the program execution mode (PMOD), CPU block (CPUBK [1],..., CPUBK [n]) 500a is set to the debug execution mode (DMOD). The debug information output path 1 (DO1) 240 in the even-numbered CPUBK [0] is connected to the debug information input path 1 (DI1) 230 in the odd-numbered CPUBK [1]. Debug information output path 1 (DO1) 240 at n−1] is connected to debug information input path 1 (DI1) 230 at CPUBK [n].

  In the odd-numbered CPU block (CPUBK [1],..., CPUBK [n]) 500a set in the debug execution mode, adjacent CPU blocks (CPUBK [m], CPUBK [m + 2]) (m is an odd number) Thus, the debug information output path 2 (DO2) 260 of the CPUBK [m] is sequentially connected to the debug information input path 2 (DI2) 250 of the CPUBK [m + 2]. The debug information output path 2 (DO2) 260 of the CPU block (CPUBK [n]) is connected to the debug information input path 2 (DI2) 250 of the CPU block (CPUBK [1]), so that the debug execution mode is set. Each CPU block set to 1 is connected in a ring shape as a whole. An external output terminal (EOT) 400 is provided at an arbitrary position in the ring. The external output terminal (EOT) 400 has a function for finally outputting debug information of the central processing unit (CPU) 100 operating in the debug execution mode to the outside of the chip through the debug information output path 2 (DO2) 260. Have.

  2 and 3 show characteristic components in the CPU block (CPUBK) 500a shown in FIG. A CPU block 500 a shown in FIG. 2 includes a mode setting register (MREG) 210 in the additional circuit (AM) 200. By setting this MREG, it is possible to arbitrarily select whether the central processing unit (CPU) 100 in the CPU block is operated in the program execution mode or the debug execution mode. That is, the same central processing unit (CPU) 100 can be used not only for program execution but also for debug execution, and debugging can be executed without providing a dedicated dedicated debug execution circuit or the like. As a result, the hardware cost can be reduced. In addition, since a high-performance CPU that is also used for program execution is used for debug execution, it is possible to improve debug processing capability.

  The CPU block 500a shown in FIG. 3 includes a debug information storage device access controller (DIMAC) 220 in addition to the mode setting register (MREG) 210 in the additional circuit (AM) 200. The debug information storage device access controller (DIMAC) 220 has the following four paths in addition to having an access path with the debug information storage device (DIM) 130. First, by having debug information input path 1 (DI1) 230, it receives debug information from another CPU block operating in the program execution mode, and receives the debug information from the central processing unit (CPU) of its own CPU block. ) 100 can be used for analysis and the like. On the other hand, by having the debug information output path 1 (DO1) 240, it is possible to request other CPU blocks that operate in the debug execution mode to analyze the debug information accompanying the execution of the program. Further, by having the debug information input path 2 (DI2) 250 and the debug information output path 2 (DO2) 260, data can be exchanged between CPU blocks operating in the debug execution mode. That is, for example, it is possible to share and analyze debug information of other CPU blocks operating in the debug execution mode, or to request sharing.

  4A to 4D are explanatory views showing four types of operation modes provided in the CPU block (CPUBK) 500a shown in FIG. FIG. 4A shows the operation content of the CPU block 500a set to the program execution mode (PMOD). Here, the debug information generation device (DIG) 120 in the central processing unit (CPU) 100 acquires debug information having contents corresponding to the control register (CREG) 110 and stores it in the debug information storage device (DIM) 130. To do. The debug information storage device access controller (DIMAC) 220 outputs the debug information stored in the debug information storage device (DIM) 130 via the debug information output path 1 (DO1) 240.

  FIG. 4B shows a case where the debug information output through the debug information output path 1 (DO1) 240 as set in the debug execution mode (DMOD) and described in FIG. 4A is collected. The operation contents of the CPU block 500a are shown. Here, the debug information storage device access controller (DIMAC) 220 collects debug information from the CPU block for executing other programs via the debug information input path 1 (DI1) 230, and collects the debug information from the debug information storage device (DI1) 230 DIM) 130. The central processing unit (CPU) 100 performs predetermined analysis or the like on the debug information stored in the debug information storage device (DIM) 130.

  FIG. 4C shows the operation contents of the CPU block 500a when data is transferred between CPU blocks set to the debug execution mode (DMOD) and set to another debug execution mode (DMOD). Has been. Here, the debug information storage device access controller (DIMAC) 220 receives debug information, analysis results, and the like output from other CPU blocks for debug execution via the debug information input path 2 (DI2) 250, Is stored in the debug information storage device (DIM) 130. As a result, the central processing unit (CPU) 100 can analyze, for example, debug information from another CPU block for debug execution. The debug information storage device access controller (DIMAC) 220 receives the debug information or analysis result stored in the debug information storage device (DIM) 130 and sends it to the debug information output path 2 (DO2) 260. To another CPU block for debug execution. As a result, the central processing unit (CPU) 100 can request, for example, analysis of debug information from another CPU block for debug execution.

  In FIG. 4 (d), the debug execution mode (DMOD) is set, and after the analysis and the like described in FIG. 4 (c) is finished, it is output via the external output terminal (EOT) 400. The operation contents of the CPU block 500a at that time are shown. Here, the debug information storage device access controller (DIMAC) 220 receives the analysis result and the like stored in the debug information storage device (DIM) 130, and outputs it to the outside via the debug information output path 2 (DO2) 260. Output toward the terminal (EOT) 400. Similarly, the debug information storage device access controller (DIMAC) 220 receives an analysis result obtained by another CPU block for debug execution via the debug information input path 2 (DI2) 250, and receives it. Output to the external output terminal (EOT) 400 via the debug information output path 2 (DO2) 260.

  FIG. 5 is an explanatory diagram showing a connection example between the CPU block set in the program execution mode and the CPU block set in the debug execution mode in the semiconductor integrated circuit device of FIG. As shown in FIG. 5, the debug information output path 1 (DO1) 240 of the CPU block (CPUBK [n-1]) 500a set to the program execution mode (PMOD) is set to the debug execution mode (DMOD). Connected to the debug information input path 1 (DI1) 230 of the CPU block (CPUBK [n]) 500a. In this way, debugging can be performed by connecting CPUBK [n] to CPUBK [n−1] in a one-to-one manner and performing debugging.

  FIG. 6 is an explanatory diagram showing a connection example between CPU blocks set in the debug execution mode in the semiconductor integrated circuit device of FIG. As shown in FIG. 6, the debug execution CPU block (CPUBK [1],..., CPUBK [n]) includes a debug information input path 2 (DI2) 250 and a debug information output path 2 (DO2) 260. Are connected to each other, and can be output to an external output terminal (EOT) 400 from a part of the ring. By connecting to the external output terminal (EOT) 400 through the ring connection in this manner, for example, the analysis result in each CPU block can be output to the external output terminal without providing the external output terminal in each CPU block. Is possible. Also, the ring connection makes it possible, for example, to distribute analysis results in a certain CPU block to a plurality of CPU blocks, or to integrate analysis results in a plurality of CPU blocks into one CPU block. Performance debugging can be realized. Furthermore, when ring connection is used, wiring can be simplified compared to the case where such information exchange is performed by bus connection, and a reduction in bandwidth associated with bus arbitration can be suppressed.

  Next, a specific use example of the semiconductor integrated circuit device of FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 7, a control register (CPUBK [0], CPUBK [n-1]) 500a set in a program execution mode via a mode setting register (MREG) 210 is controlled by a control register ( CREG) 110 is used to specify debug information to be acquired. Then, in each of the CPUBK [0] and CPUBK [n−1], the designated debug information is stored in the debug information storage device (DIM) 130 by the debug information generation device (DIG) 120, and the debug information storage device access controller. (DIMAC) 220 outputs the stored debug information to debug information output path 1 (DO1) 240.

  On the other hand, the CPU block (CPUBK [1]) 500a set to the debug execution mode via the mode setting register (MREG) 210 receives the debug information output from the CPUBK [0] as the debug information storage device access controller (DIMAC). ) 220 debug information input path 1 (DI1) 230. Similarly, the CPU block (CPUBK [n]) 500a set to the debug execution mode also collects debug information output from the CPUBK [n−1].

  Here, for example, CPUBK [0] executes program processing of a part of work A and a part of work B, and CPUBK [n−1] It is assumed that some program processing has been executed. In this case, as shown in FIG. 8, the central processing unit (CPU) 100 of the CPUBK [1] sends debug information related to a part of the work B to the debug information storage device access controller (DIMAC) 220, for example, as debug information. Obtained from the storage device (DIM) 130. In addition, the central processing unit (CPU) 100 of the CPUBK [n] sends, for example, debug information related to another part of the work A to the debug information storage device access controller (DIMAC) 220, the debug information storage device (DIM) 130. To get from.

  Subsequently, as shown in FIG. 9, the central processing unit (CPU) 100 of the CPUBK [1] uses a debug information storage device access controller (DIMAC) 220 to ring-connect debug information related to a part of the work B. To CPUBK [n]. Similarly, the central processing unit (CPU) 100 of the CPUBK [n] uses the debug information storage device access controller (DIMAC) 220 to send debug information about another part of the work A to the CPUBK [1 via the ring connection. ]. Next, the debug information storage device access controller (DIMAC) 220 of the CPUBK [1] stores the debug information related to the other part of the work A transferred via the ring connection in the debug information storage device (DIM) 130. . Similarly, the debug information storage device access controller (DIMAC) 220 of CPUBK [n] stores the debug information related to a part of the work B transferred via the ring connection in the debug information storage device (DIM) 130. Then, the central processing unit (CPU) 100 of the CPUBK [1] performs analysis or the like on the debug information regarding part of the work A and the other part, and the central processing unit (CPU) of the CPUBK [n]. 100 performs an analysis or the like on the debug information regarding a part of the work B and the other part described above.

  When the analysis result or the like is obtained, as shown in FIG. 10, the central processing unit (CPU) 100 of CPUBK [1] sends the analysis result or the like regarding the work A to the debug information storage device access controller (DIMAC) 220. It is acquired from the debug information storage device (DIM) 130. Further, the central processing unit (CPU) 100 of the CPUBK [n] causes the debug information storage device access controller (DIMAC) 220 to obtain the analysis result and the like regarding the work B from the debug information storage device (DIM) 130. Then, as shown in FIG. 11, the central processing unit (CPU) 100 of the CPUBK [1] uses the debug information storage device access controller (DIMAC) 220 to send the analysis result and the like regarding the work A to the outside via the ring connection. Output to an output terminal (EOT) 400. Similarly, the central processing unit (CPU) 100 of the CPUBK [n] uses the debug information storage device access controller (DIMAC) 220 to send the analysis result and the like regarding the work B to the external output terminal (EOT) 400 via the ring connection. Output to.

  Thereby, even when one processing process is distributed and executed on a plurality of CPUs, debugging thereof can be easily realized. In addition, here, the case where the analysis on the work A and the work B is performed and the respective analysis results are all output is taken as an example, but of course, the analysis is performed only on the work A according to the importance, It is also possible to output the analysis result and the like.

  As described above, by using the semiconductor integrated circuit device according to the first embodiment, typically, it is possible to facilitate program debugging or reduce the cost of program debugging. That is, with the addition of a very small amount of hardware, a single CPU can be operated as both a normal arithmetic processor and a debug execution processor. Similarly, with the addition of very little hardware, (1) a large amount of debugging information / performance tuning information output from multiple CPUs is collected, and (2) such information is debugged as needed. (3) It is possible to extract and output only highly important information from the huge amount of debugging information / performance tuning information collected, or to process and output the information. It is possible to realize a semiconductor integrated circuit device having much stronger debugging capability / performance tuning capability than the conventional method. Furthermore, although the above effects can be realized, the hardware cost and the implementation cost necessary to realize these can be greatly reduced as compared with the conventional method.

(Embodiment 2)
FIG. 12 is a block diagram showing a configuration example of each CPU block included in the semiconductor integrated circuit device according to the second embodiment of the present invention. The CPU block 500b shown in FIG. 12 differs from the CPU block 500a shown in FIG. 3 in the configuration in the additional circuit (AM) 200. Since other configurations are the same as those in FIG. 3, detailed description thereof is omitted.

  An additional circuit (AM) 200 shown in FIG. 12 includes a mode setting register (MREG) 210, a debug information storage device access controller (DIMAC) 220, a debug information input path 1 (DI1) 230, and a debug information output path 1 (DO1) 240. , Debug information input path 2 (DI2) 250, debug information output path 2 (DO2) 260, and input / output interface (IOIF) 300. The mode setting register (MREG) 210 has a function of setting which of the two modes of “program execution mode” and “debug execution mode” to the central processing unit (CPU) 100 to operate. When the program execution mode is selected, the central processing unit (CPU) 100 executes an arithmetic processing operation in accordance with a given program in the same manner as when the mode setting register (MREG) 210 is not provided. When the debug execution mode is selected, the central processing unit (CPU) 100 executes a debug execution program instead of a normal program.

  The debug information storage device access controller (DIMAC) 220 includes a debug information storage device (DIM) 130, a debug information input path 1 (DI1) 230, a debug information output path 1 (DO1) 240, and a debug information input path 2 (DI2). 250 and a debug information output path 2 (DO2) 260 each having a function of controlling input / output of debug information. The debug information input path 1 (DI1) 230 is used to transfer the debug information of the central processing unit (CPU) 100 operating in the program execution mode to another central processing unit (CPU) 100 operating in the debug execution mode. Function as an input path. The debug information output path 1 (DO1) 240 is used to transfer debug information of the central processing unit (CPU) 100 operating in the program execution mode to another central processing unit (CPU) 100 operating in the debug execution mode. Function as an output path. The debug information input path 2 (DI2) 250 transfers debug information of the central processing unit (CPU) 100 that operates in the debug execution mode to another central processing unit (CPU) 100 that also operates in the debug execution mode. It has a function as an input path. The debug information output path 2 (DO2) 260 transfers debug information of the central processing unit (CPU) 100 that operates in the debug execution mode to another central processing unit (CPU) 100 that also operates in the debug execution mode. It has a function as an output path when

  The input / output interface (IOIF) 300 includes an input / output selector (IOSEL) 310 and an input / output connector (IOC) 320. The input / output selector (IOSEL) 310 has a function of selecting either the debug information input path 1 (DI1) 230 or the debug information output path 1 (DO1) 240 and connecting it to the input / output connector (IOC) 320. The input / output connector (IOC) 320 is connected to the debug information input path 1 (DI1) 230 or the debug information output path 1 (DO1) 240 selected by the input / output selector (IOSEL) 310 to another central processing unit (CPU) 100. Input / output connector (IOC).

  FIG. 13 is a block diagram showing an example of the overall configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 13 has substantially the same configuration as the semiconductor integrated circuit device shown in FIG. 1, but the CPU block (CPUBK) 500a in FIG. 1 is replaced with the CPU block (CPUBK) 500b in FIG. With the replacement, the wiring between the CPU blocks is slightly different. That is, in FIG. 13, the input / output connector (IOC) 320 of the CPU block (CPUBK [0]) 500b set to the program execution mode (PMOD) is set to the CPU block (DMOD) set to the debug execution mode (DMOD). CPUBK [1]) is electrically coupled to an input / output connector (IOC) 320 of 500b. Similarly, the input / output connector (IOC) 320 of the CPU block (CPUBK [n−1]) 500b (n = 3, 5,...) Set in the program execution mode (PMOD) is in the debug execution mode (DMOD). ) Is electrically coupled to the input / output connector (IOC) 320 of the CPU block (CPUBK [n]) 500b set to (). The ring connection between the CPU blocks (CPUBK [1],..., CPUBK [n]) for debug execution is the same as the configuration example of FIG.

  14A is a schematic diagram showing an example of a mounting form in the semiconductor integrated circuit device of FIG. 13, and FIG. 14B is a configuration example of the input / output connector (IOC) 320 in FIG. 14A. FIG. The semiconductor integrated circuit device shown in FIG. 14A has a configuration in which, for example, two semiconductor chips (CP1, CP2) 600 are three-dimensionally stacked and mounted. A CPU block (CPUBK [0],..., CPUBK [n−1]) 500b for program execution shown in FIG. 13 is formed in CP1, and a CPU block for debug execution shown in FIG. (CPUBK [1],..., CPUBK [n]) 500b is formed.

  The above-described input / output connector (IOC) 320 in CPUBK [0],..., CPUBK [n−1] and input / output connector (IOC) 320 in CPUBK [1],. As shown in FIG. 14B, it is constructed by wireless interconnect technology or through via technology. That is, as shown in FIG. 14B, for example, when an input / output connector (IOCa1) is provided on the semiconductor chip CP1 and an input / output connector (IOCa2) is provided on the semiconductor chip CP2, electromagnetic induction coupling is performed between IOCa1 and IOCa2. Wireless communication using (M) can be performed. For example, when an input / output connector (IOCb1) is provided on the semiconductor chip CP1 and an input / output connector (IOCb2) is provided on the semiconductor chip CP2, wireless communication using electrostatic induction coupling (C) is performed between the IOCb1 and the IOCb2. Yes. Further, for example, when an input / output connector (IOCc1) is provided on the semiconductor chip CP1 and an input / output connector (IOCc2) is provided on the semiconductor chip CP2, wired communication can be performed between the IOCc1 and the IOCc2 via a through via (VIA).

  FIG. 15 is an explanatory diagram showing a connection example between the CPU block set in the program execution mode and the CPU block set in the debug execution mode in the semiconductor integrated circuit device of FIG. As shown in FIG. 15, in the CPU block (CPUBK [n−1]) 500 b set in the program execution mode (PMOD), the debug information output path 1 (DO1) 240 passes through the input / output selector (IOSEL) 310. To the input / output connector (IOC) 320. On the other hand, in the CPU block (CPUBK [n]) 500b set to the debug execution mode (DMOD), the debug information input path 1 (DI1) 230 is connected to the input / output connector (IOC) via the input / output selector (IOSEL) 310. 320 is connected. By electrically coupling the two input / output connectors (IOC) 320, the debug information output path 1 (DO1) 240 of the CPUBK [n-1] becomes the debug information input path 1 (DI1) of the CPUBK [n]. 230.

  Thus, by using the input / output connector (IOC) 320 that is also used for connection to the debug information input path 1 (DI1) 230 and the debug information output path 1 (DO1) 240, the CPU block for program execution and the debug execution It is possible to simplify the communication path with the CPU block. During the debugging period, output is always performed from the input / output connector (IOC) 320 of the CPU block for program execution, and input is always performed from the input / output connector (IOC) 320 of the CPU block for debug execution. Since output switching does not occur in particular, the use of such an input / output connector (IOC) 320 does not cause a reduction in communication efficiency.

  FIG. 16 is an explanatory diagram showing a connection example between CPU blocks set in the debug execution mode in the semiconductor integrated circuit device of FIG. As shown in FIG. 16, the debug execution CPU block (CPUBK [1],..., CPUBK [n]) includes a debug information input path 2 (DI2) 250 and a debug information output path 2 (DO2) 260. Are connected to each other, and can be output to an external output terminal (EOT) 400 from a part of the ring. As a result, the same effect as in FIG.

  As described above, by using the semiconductor integrated circuit device of the second embodiment, as in the case of the first embodiment, typically, it is possible to facilitate program debugging or reduce the cost of program debugging. It becomes possible. Further, these effects can be further improved as compared with the case of the first embodiment. That is, as shown in FIG. 14, two semiconductor chips CP1 and CP2 having the same configuration are manufactured, and for example, a semiconductor integrated circuit device in which they are connected by through vias (VIA) as a device for program development. Make it. Then, debugging of program development using CP1 using CP2 as a debug module is performed, and finally, one semiconductor chip (CP1 or CP2) not stacked with the developed program is provided to the market. When such a method is used, it is not necessary to newly develop a debug module for each product as in the prior art, and it is not necessary to incorporate the debug module into CP1 itself as in the prior art. Therefore, it is possible to further facilitate program debugging or to reduce the cost of program debugging, and to reduce the cost of the semiconductor chip itself.

  Further, instead of manufacturing the semiconductor integrated circuit device for debugging having the above-described through via (VIA), the semiconductor chips CP1 and CP2 having the wireless interconnect technology as shown in FIG. 14B are manufactured. Then, CP2 is superimposed on CP1, and in this state, program development using CP1 is debugged using CP2 as a debug module. If such a method is used, in addition to the effect of the above-described through via (VIA), it is possible to execute debugging without physically connecting CP1 and CP2, so only when necessary It is possible to realize high-performance debugging with simple means.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

100 Central processing unit (CPU)
110 Control register (CREG)
120 Debug information generator (DIG)
130 Debug information storage (DIM)
200 Additional circuit (AM)
210 Mode setting register (MREG)
220 Debug information storage device access controller (DIMAC)
230 Debug information input path 1 (DI1)
240 Debug information output path 1 (DO1)
250 Debug information input path 2 (DI2)
260 Debug information output path 2 (DO2)
300 Input / output interface (IOIF)
310 Input / output selector (IOSEL)
320 Input / output connector (IOC)
400 External output terminal (EOT)
500 CPU blocks (CPUBK)
600 Semiconductor chip (CP)

Claims (16)

A first central processing circuit including a first memory for storing processing data;
A first mode register for setting whether to operate the first central processing circuit in a program execution mode or a debug execution mode;
A first input function having a first input node and a first output node, and writing data input to the first input node to the first memory; and data read from the first memory to the first output node A first controller including a first output function for outputting;
A second central processing circuit including a second memory for storing processing data;
A second mode register for setting whether to operate the second central processing circuit in the program execution mode or the debug execution mode;
A second input function having a second input node and a second output node, and writing data input to the second input node to the second memory; and data read from the second memory to the second output node A second controller including a second output function for outputting;
A first communication path;
The first central processing circuit operates in the program execution mode according to the setting of the first mode register,
The first controller transmits the data in the first memory to the first communication path using the first output function when the first central processing circuit operates in the program execution mode.
The second central processing circuit operates in the debug execution mode according to the setting of the second mode register,
When the second central processing circuit operates in the debug execution mode, the second controller uses the second input function to transmit the first memory transmitted via the first communication path. A semiconductor integrated circuit device, wherein data is transmitted to the second memory. 2. The semiconductor integrated circuit device according to claim 1, further comprising:
A third central processing circuit including a third memory for storing processing data;
A third mode register for setting whether to operate the third central processing circuit in the program execution mode or the debug execution mode;
A third input node having a third input node and a third output node; a third input function for writing data input to the third input node to the third memory; and data read from the third memory to the third output node A third controller including a third output function for outputting;
A fourth central processing circuit including a fourth memory for storing processing data;
A fourth mode register for setting whether to operate the fourth central processing circuit in the program execution mode or the debug execution mode;
A fourth input function having a fourth input node and a fourth output node and writing data input to the fourth input node to the fourth memory; and data read from the fourth memory to the fourth output node A fourth controller including a fourth output function for outputting;
A second communication path,
The third central processing circuit operates in the program execution mode according to the setting of the third mode register,
When the third central processing circuit operates in the program execution mode, the third controller transmits the data in the third memory to the second communication path using the third output function,
The fourth central processing circuit operates in the debug execution mode according to the setting of the fourth mode register,
When the fourth central processing circuit operates in the debug execution mode, the fourth controller uses the fourth input function to transmit the third memory transmitted through the second communication path. Transmitting data to the fourth memory;
The second controller further includes:
A fifth input node and a fifth output node;
A fifth input function for writing data input to the fifth input node to the second memory when the second central processing circuit operates in the debug execution mode;
A fifth output function for outputting data read from the second memory to the fifth output node when the second central processing circuit operates in the debug execution mode;
The fourth controller further includes:
A sixth input node and a sixth output node;
A sixth input function for writing data input to the sixth input node to the fourth memory when the fourth central processing circuit operates in the debug execution mode;
A sixth output function for outputting data read from the fourth memory to the sixth output node when the fourth central processing circuit operates in the debug execution mode;
The fifth input node has a third communication path with the sixth output node;
The semiconductor integrated circuit device, wherein the sixth input node has a fourth communication path between the sixth input node and the fifth output node. The semiconductor integrated circuit device according to claim 2.
The semiconductor integrated circuit device is further set in the debug execution mode so as to correspond one-to-one with the N (N is an integer) central processing circuits set in the program execution mode. A semiconductor integrated circuit device having N central processing circuits. The semiconductor integrated circuit device according to claim 2.
The semiconductor integrated circuit device, wherein the third communication path and the fourth communication path are constructed in one ring wiring path. 5. The semiconductor integrated circuit device according to claim 4, further comprising:
A semiconductor integrated circuit device having an external output terminal connected to a part of the ring wiring path. The semiconductor integrated circuit device according to claim 2.
The first and third central processing circuits, the first and third mode registers, and the first and third controllers are formed in a first semiconductor chip,
The second and fourth central processing circuits, the second and fourth mode registers, and the second and fourth controllers are formed in a second semiconductor chip,
The semiconductor integrated circuit device, wherein the first semiconductor chip and the second semiconductor chip are three-dimensionally stacked and mounted. A first semiconductor chip and a second semiconductor chip which are three-dimensionally stacked and mounted;
A first communication path and a second communication path serving as a communication path between the first semiconductor chip and the second semiconductor chip;
The first semiconductor chip is
A first central processing circuit including a first memory for storing processing data;
A first mode register for setting whether to operate the first central processing circuit in a program execution mode or a debug execution mode;
A first input function having a first input node and a first output node, and writing data input to the first input node to the first memory; and data read from the first memory to the first output node A first controller including a first output function for outputting;
A third central processing circuit including a third memory for storing processing data;
A third mode register for setting whether to operate the third central processing circuit in the program execution mode or the debug execution mode;
A third input node having a third input node and a third output node; a third input function for writing data input to the third input node to the third memory; and data read from the third memory to the third output node A third controller including a third output function for outputting,
The second semiconductor chip is
A second central processing circuit including a second memory for storing processing data;
A second mode register for setting whether to operate the second central processing circuit in the program execution mode or the debug execution mode;
A second input function having a second input node and a second output node, and writing data input to the second input node to the second memory; and data read from the second memory to the second output node A second controller including a second output function for outputting;
A fourth central processing circuit including a fourth memory for storing processing data;
A fourth mode register for setting whether to operate the fourth central processing circuit in the program execution mode or the debug execution mode;
A fourth input function having a fourth input node and a fourth output node and writing data input to the fourth input node to the fourth memory; and data read from the fourth memory to the fourth output node A fourth controller including a fourth output function for outputting,
The first and third central processing circuits operate in the program execution mode according to the settings of the first and third mode registers,
The second and fourth central processing circuits operate in the debug execution mode according to the settings of the second and fourth mode registers,
The first controller transmits the data of the first memory to the first communication path using the first output function,
The second controller transmits the data of the first memory transmitted through the first communication path to the second memory using the second input function,
The third controller transmits the data of the third memory to the second communication path using the third output function,
The semiconductor integrated circuit device, wherein the fourth controller uses the fourth input function to transmit the data in the third memory transmitted through the second communication path to the fourth memory. The semiconductor integrated circuit device according to claim 7,
The second controller further includes:
A fifth input node and a fifth output node;
A fifth input function for writing data input to the fifth input node into the second memory;
A fifth output function for outputting data read from the second memory to the fifth output node;
The fourth controller further includes:
A sixth input node and a sixth output node;
A sixth input function for writing data input to the sixth input node into the fourth memory;
A sixth output function for outputting data read from the fourth memory to the sixth output node;
The fifth input node has a third communication path with the sixth output node;
The semiconductor integrated circuit device, wherein the sixth input node has a fourth communication path between the sixth input node and the fifth output node. The semiconductor integrated circuit device according to claim 8.
The semiconductor integrated circuit device, wherein the third communication path and the fourth communication path are constructed in one ring wiring path formed on the second semiconductor chip. The semiconductor integrated circuit device according to claim 9.
The semiconductor integrated circuit device, wherein the second semiconductor chip further has an external output terminal connected to a part of the ring wiring path. The semiconductor integrated circuit device according to claim 7,
The semiconductor integrated circuit device, wherein the first and second communication paths are constructed by through vias. The semiconductor integrated circuit device according to claim 7,
The semiconductor integrated circuit device, wherein the first and second communication paths are constructed by wireless communication. A method for debugging a program distributed and implemented in a first processor block and a second processor block using a third processor block and a fourth processor block,
Each of the first to fourth processor blocks includes a register for setting a program execution mode or a debug execution mode, a central processing circuit, a memory for storing processing data of the central processing circuit, and a first processing block. A controller having an input function and a first output function;
The first output function becomes effective when the program execution mode is set, and transmits data on the memory to the first output node;
The first input function is enabled when the debug execution mode is set, and transmits data of the first input node to the memory.
The first output node of the first processor block has a first communication path with the first input node of the third processor block;
The first output node of the second processor block has a second communication path with the first input node of the fourth processor block;
The third processor block is configured such that the registers of the first and second processor blocks are set to the program execution mode, and the registers of the third and fourth processor blocks are set to the debug execution mode. Collects debug information associated with program execution of the first processor block using the first output function of the first processor block and the first input function of the third processor block, and the fourth processor block Debugging a program, wherein debug information associated with program execution of the second processor block is collected using the first output function of the second processor block and the first input function of the fourth processor block Method. A program debugging method according to claim 13, comprising:
The controller included in the first to fourth processor blocks further includes a second input function and a second output function,
The second input function is enabled when the debug execution mode is set, and transmits data of a second input node to the memory.
The second output function becomes effective when the debug execution mode is set, and transmits data on the memory to a second output node.
The second output node of the third processor block has a third communication path with the second input node of the fourth processor block;
The second output node of the fourth processor block has a fourth communication path with the second input node of the third processor block;
A part or all of the debug information collected from the first processor block by the third processor block using the second output function of the third processor block and the second input function of the fourth processor block. A program debugging method comprising transferring the program to the fourth processor block. A program debugging method according to claim 13, comprising:
The first and second processor blocks are formed in a first semiconductor chip,
The third and fourth processor blocks are formed in a second semiconductor chip;
A program debugging method, wherein the first and second communication paths are constructed by three-dimensionally stacking and mounting the first semiconductor chip and the second semiconductor chip. The program debugging method according to claim 15, comprising:
The method for debugging a program, wherein the first and second communication paths are constructed by wireless communication.

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