JP2011155248A - Solid-state imaging device, method of manufacturing the same, and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a solid-state imaging device that suppresses deterioration in pixel characteristics due to a crystal defect caused in a silicon layer; a method of manufacturing the same; and a camera. <P>SOLUTION: The solid-state imaging device includes: a photodiode sectioned by pixels of a light-receiving surface, formed by integrating a plurality of pixels, of a semiconductor substrate; and a signal read portion for reading signal charges generated and stored in the photodiode or a voltage corresponding to the signal charges. The photodiode includes: a first semiconductor layer 13 of a first conductivity type, formed on the semiconductor substrate 10; a second semiconductor layer 24a of the first conductivity type, formed on the first semiconductor layer while projecting from the semiconductor substrate to be in a shape that decreases in area of a section on a plane parallel with a surface of the semiconductor substrate as it goes away from the semiconductor substrate; and a third semiconductor layer 25 of a second conductivity type, formed on a surface of the second semiconductor layer, wherein the first and second semiconductor layers are formed apart from a transfer gate electrode 22a of the signal read portion. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and a camera, and more particularly to a solid-state imaging device in which pixels having photodiodes on a light receiving surface are arranged in a matrix, a manufacturing method thereof, and a camera including the solid-state imaging device.

  For example, in a solid-state imaging device such as a CMOS image sensor or a CCD element, a light signal is incident on a photodiode (photoelectric conversion unit) formed on the surface of a semiconductor substrate, and a video signal is obtained by signal charges generated by the photodiode. It has become.

  In the CMOS image sensor, for example, a photodiode is provided for each pixel arranged in a two-dimensional matrix on the light receiving surface. A signal charge generated and accumulated in each photodiode during light reception is transferred to a floating diffusion by driving a CMOS circuit, and the signal charge is converted into a signal voltage and read.

  In the CCD element, for example, a photodiode is provided for each pixel arranged in a two-dimensional matrix on the light receiving surface as in the CMOS sensor. A signal charge generated and accumulated in each photodiode during light reception is transferred and read through a CCD vertical transfer path and a horizontal transfer path.

  In the solid-state imaging device such as the above-described CMOS sensor, for example, the above-described photodiode is formed on the surface of a semiconductor substrate for each pixel.

Patent Document 1 discloses a configuration in which a silicon layer having a lens shape is selectively epitaxially grown on a photodiode in a CCD element.
Usually, the light condensing property is reduced with the miniaturization of the photodiode. However, the configuration of Patent Document 1 aims to prevent the light condensing property from being deteriorated.
As shown in Patent Document 1, a silicon layer is grown on the photodiode up to the top of the light shielding film by selective epitaxial growth.
The surface of the silicon layer is round like a lens, and this lens-shaped silicon layer acts as a lens and can improve the light collecting property.

The case where the above-described epitaxially grown silicon layer is applied to a CMOS image sensor will be described below.
As can be seen from FIG. 2 of Patent Document 2, the silicon layer formed by epitaxial growth is grown to the upper part of the light shielding film.

When this is applied to a CMOS image sensor, a silicon layer formed by epitaxial growth is formed on the photodiode region and the floating diffusion region.
Here, the epitaxial silicon layer is formed up to the vicinity of the upper end of the transfer gate electrode in contact with the sidewall insulating film formed on the side wall of the transfer gate electrode.

In such a configuration, since the silicon layer formed by epitaxial growth is in contact with the sidewall insulating film, crystal defects are generated in the silicon layer.
A crystal defect in the silicon layer on the photodiode region becomes a dark current generation region, which causes a problem that pixel characteristics deteriorate.

JP 2008-147409 A

  When a silicon layer formed by epitaxial growth is applied to a CMOS image sensor, there arises a problem that a crystal defect occurs in the silicon layer and pixel characteristics deteriorate.

  In the solid-state imaging device according to the present invention, the first conductive type first semiconductor layer formed on the semiconductor substrate in the photodiode region divided for each pixel on the light receiving surface formed by integrating a plurality of pixels of the semiconductor substrate. And a first conductive layer formed on the first semiconductor layer so as to be convex with respect to the semiconductor substrate, and having a shape in which a cross-sectional area in a plane parallel to the surface of the semiconductor substrate decreases from the semiconductor substrate. Formed on the semiconductor substrate in a region adjacent to the photodiode, and a photodiode having a second semiconductor layer of a type and a third semiconductor layer of a second conductivity type formed on a surface of the second semiconductor layer. A transfer gate electrode, and a floating diffusion formed in the semiconductor substrate on the opposite side of the transfer gate electrode from the photodiode, A signal reading unit that reads a signal charge generated and accumulated in the photodiode or a voltage corresponding to the signal charge, and the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode Has been.

The solid-state imaging device according to the present invention includes a photodiode in a photodiode region divided for each pixel on a light receiving surface in which a plurality of pixels of a semiconductor substrate are integrated, and signal charges or signals generated and accumulated in the photodiode. A signal reading unit that reads a voltage corresponding to the electric charge is provided.
The photodiode is a first semiconductor layer of a first conductivity type formed on a semiconductor substrate, a convex shape with respect to the semiconductor substrate on the first semiconductor layer, and a cross section in a plane parallel to the surface of the semiconductor substrate. The first conductive type second semiconductor layer has a shape that decreases as the area of the second semiconductor layer becomes farther from the semiconductor substrate, and the second conductive type third semiconductor layer formed on the surface of the second semiconductor layer.
The signal reading unit includes a transfer gate electrode formed on a semiconductor substrate in a region adjacent to the photodiode, and a floating diffusion formed in the semiconductor substrate on the side opposite to the photodiode of the transfer gate electrode.
Here, the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode.

Preferably, the second semiconductor layer which is a light absorption layer is formed of a material having a band gap smaller than that of silicon. For example, Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se ₂ , Cu (In, Ga) (Se, S) ₂ , or CuInS. _{2 is} formed. These materials have a larger light absorption coefficient than silicon, particularly in the red wavelength region.

  According to the method for manufacturing a solid-state imaging device of the present invention, a first semiconductor layer of a first conductivity type is formed on the semiconductor substrate in a photodiode region divided for each of the pixels on a light receiving surface in which a plurality of pixels of the semiconductor substrate are integrated. Forming a floating diffusion in the semiconductor substrate spaced from the photodiode, forming a transfer gate electrode on the semiconductor substrate in a region between the photodiode and the floating diffusion, and The first conductivity type first electrode having a shape convex on the first semiconductor layer with respect to the semiconductor substrate and having a cross-sectional area in a plane parallel to the surface of the semiconductor substrate that decreases as the distance from the semiconductor substrate increases. A step of forming two semiconductor layers, and a step of forming a third semiconductor layer of the second conductivity type on the surface of the second semiconductor layer. And forming the first semiconductor layer, forming the second semiconductor layer, and forming the third semiconductor layer, forming the photodiode, forming the transfer gate electrode, and floating Forming a signal reading unit that reads a signal charge generated and accumulated in the photodiode or a voltage corresponding to the signal charge in the step of forming a diffusion, and forming the second semiconductor layer and the third semiconductor layer; In the forming step, the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode.

Preferably, the second semiconductor layer which is a light absorption layer is formed from a material having a band gap smaller than that of silicon. For example, Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se ₂ , Cu (In, Ga) (Se, S) ₂ , or CuInS. _{2 is} formed. These materials have a larger light absorption coefficient than silicon, particularly in the red wavelength region.

In the manufacturing method of the solid-state imaging device of the present invention, the first conductive type first semiconductor layer is formed on the semiconductor substrate in the photodiode region divided for each pixel of the light receiving surface in which a plurality of pixels of the semiconductor substrate are integrated. Form.
In addition, a floating diffusion is formed in a semiconductor substrate separated from the photodiode.
Next, a transfer gate electrode is formed on the semiconductor substrate in a region between the photodiode and the floating diffusion.
Next, a second semiconductor of the first conductivity type having a shape that is convex with respect to the semiconductor substrate on the first semiconductor layer, and that the cross-sectional area in a plane parallel to the surface of the semiconductor substrate decreases as the distance from the semiconductor substrate increases. Forming a layer, and forming a third semiconductor layer of the second conductivity type on the surface of the second semiconductor layer.
A photodiode is formed by the step of forming the first semiconductor layer, the step of forming the second semiconductor layer, and the step of forming the third semiconductor layer, and the step of forming the transfer gate electrode and the step of forming the floating diffusion A signal reading unit that reads a signal charge generated or accumulated in the diode or a voltage corresponding to the signal charge is formed.
Here, in the step of forming the second semiconductor layer and the step of forming the third semiconductor layer, the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode.

  The camera according to the present invention includes a solid-state imaging device in which a plurality of pixels are integrated on a light-receiving surface, an optical system that guides incident light to an imaging unit of the solid-state imaging device, and signal processing that processes an output signal of the solid-state imaging device The solid-state imaging device includes a first conductivity type formed on the semiconductor substrate in a photodiode region divided for each pixel of the light receiving surface formed by integrating a plurality of pixels of the semiconductor substrate. A first semiconductor layer and a shape formed on the first semiconductor layer so as to be convex with respect to the semiconductor substrate, and having a cross-sectional area in a plane parallel to the surface of the semiconductor substrate that decreases as the distance from the semiconductor substrate increases. A photodiode having a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type formed on a surface of the second semiconductor layer; and a region adjacent to the photodiode. A transfer gate electrode formed on a semiconductor substrate, and a floating diffusion formed in the semiconductor substrate on the opposite side of the transfer gate electrode from the photodiode, and a signal generated and stored in the photodiode A signal reading unit that reads a charge or a voltage corresponding to the signal charge, and the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode.

  The camera according to the present invention includes a solid-state imaging device in which a plurality of pixels are integrated on a light receiving surface, an optical system that guides incident light to an imaging unit of the solid-state imaging device, and signal processing that processes an output signal of the solid-state imaging device. The solid-state imaging device is a solid-state imaging device having the above structure.

  In the solid-state imaging device of the present invention, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode, and deterioration of pixel characteristics due to crystal defects occurring in the semiconductor layer can be avoided.

  According to the method for manufacturing a solid-state imaging device of the present invention, the semiconductor layer formed by epitaxial growth that constitutes the photodiode is formed apart from the transfer gate electrode, so that deterioration of pixel characteristics due to crystal defects occurring in the semiconductor layer can be avoided.

  In the camera of the present invention, in the solid-state imaging device constituting the camera, the semiconductor layer formed by epitaxial growth that constitutes the photodiode is formed away from the transfer gate electrode, and the pixel characteristics are deteriorated due to the occurrence of crystal defects in the semiconductor layer. Can be avoided.

FIG. 1 is a plan view of the solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is an enlarged schematic cross-sectional view of the main part of the solid-state imaging device according to the first embodiment of the present invention. FIG. 4A and FIG. 4B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIGS. 6A and 6B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 8A and FIG. 8B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 9A and FIG. 9B are cross-sectional views illustrating manufacturing steps of the method of manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 10 is an enlarged schematic cross-sectional view of a main part of the solid-state imaging device according to the first modification of the present invention. FIG. 11A and FIG. 11B are cross-sectional views showing the manufacturing process of the manufacturing method of the solid-state imaging device according to the first modification of the present invention. FIG. 12 is a cross-sectional view of a solid-state imaging device according to the second embodiment of the present invention. FIG. 13A and FIG. 13B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. FIG. 14A and FIG. 14B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. FIG. 15 is a cross-sectional view of a solid-state imaging device according to the third embodiment of the present invention. FIG. 16 is a plan view of a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 17 is a cross-sectional view of a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 18A and FIG. 18B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 19A and FIG. 19B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the fourth embodiment of the present invention. 20 (a) and 20 (b) are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 21 is a cross-sectional view of a solid-state imaging device according to the fifth embodiment of the present invention. FIG. 22A and FIG. 22B are cross-sectional views showing the manufacturing process of the manufacturing method of the solid-state imaging device according to the fifth embodiment of the present invention. FIG. 23A and FIG. 23B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the fifth embodiment of the present invention. FIG. 24 is a cross-sectional view of a solid-state imaging device according to the sixth embodiment of the present invention. FIG. 25A to FIG. 25C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the sixth embodiment of the present invention. FIG. 26A and FIG. 26B are cross-sectional views illustrating manufacturing steps of the method of manufacturing the solid-state imaging device according to the sixth embodiment of the present invention. FIG. 27A to FIG. 27D are schematic views according to a second modification of the present invention. FIG. 28 is a schematic cross-sectional view of a solid-state imaging device according to the seventh embodiment of the present invention. FIG. 29 is a schematic configuration diagram of a camera according to the eighth embodiment of the present invention.

  Embodiments of a solid-state imaging device, a manufacturing method thereof, and a camera including the solid-state imaging device according to the present invention will be described below with reference to the drawings.

The description will be given in the following order.
1. First Embodiment (Basic Configuration Solid-State Imaging Device and Manufacturing Method Thereof)
2. First Modification (Solid-state imaging device having a curved epitaxial semiconductor layer and manufacturing method)
3. Second Embodiment (Solid-state imaging device having a p-type semiconductor layer formed by in-situ B-doped epitaxial growth and manufacturing method thereof)
4). Third Embodiment (Solid-state imaging device having a layer of material having a smaller band gap than silicon formed by epitaxial growth and its manufacturing method)
5. Fourth Embodiment (Solid-state imaging device having a layer made of a material having a band gap smaller than that of silicon in a recess formed in a photodiode region of a long wavelength pixel (red pixel) and a manufacturing method thereof)
6). Fifth Embodiment (Solid-state imaging device having a layer made of a material having a smaller band gap than silicon in a recess formed in a photodiode region and a source / drain region of a PMOS, and a manufacturing method thereof)
7). Sixth Embodiment (Solid-state imaging device using Ge substrate and manufacturing method thereof)
8). Second Modification (Solid-state imaging device having a Si—Ge layer whose composition changes continuously)
9. Seventh Embodiment (Solid-state imaging device having an optical waveguide)
10. Eighth Embodiment (Camera provided with a solid-state imaging device)

<First Embodiment>
[Configuration of solid-state imaging device]
FIG. 1 is a plan view of a region corresponding to four pixels on the light receiving surface of the solid-state imaging device according to the present embodiment.
For example, photodiodes (PD1, PD2, PD3, PD4) are formed in the photodiode region divided for each pixel on the light receiving surface where a plurality of pixels of the semiconductor substrate are integrated.
Transfer gate electrodes (TG1, TG2, TG3, TG4) are formed on the semiconductor substrate in a region adjacent to the photodiode.
A floating diffusion FD is formed in the semiconductor substrate on the opposite side of the transfer gate electrode (TG1, TG2, TG3, TG4) from the photodiode (PD1, PD2, PD3, PD4).
The floating diffusion FD includes, for example, a first floating diffusion FD1 and a second floating diffusion FD2 that are divided into regions and have different impurity concentrations.
A signal reading unit that reads a signal charge generated or accumulated in the photodiode (PD1, PD2, PD3, PD4) or a voltage corresponding to the signal charge from the transfer gate electrode (TG1, TG2, TG3, TG4) and the floating diffusion FD. Composed.

FIG. 2 is a schematic cross-sectional view of a CMOS image sensor, which is a solid-state imaging device according to this embodiment, in which a plurality of pixels are integrated.
In the drawing, a logic region A _LG constituting a peripheral circuit of the pixel region is shown. The pixel region indicates a photodiode region A _PD , a transfer gate electrode region A _TG and a floating diffusion region A _FD .
Further, a cross-sectional view taken along a line AB in FIG. 2 corresponds to a cross section taken along a line AB in FIG.
A cross-sectional view taken along the line _CD corresponding to the logic region A _LG in FIG. 2 corresponds to a region not shown in FIG.

For example, the n-type first semiconductor layer 13 formed on the semiconductor substrate is formed in the photodiode region _{APD divided} for each pixel on the light receiving surface where a plurality of pixels of the semiconductor substrate 10 made of silicon are integrated. Yes.
Photodiode region _{A PD} is, for example STI is divided like (shallow trench isolation) type element isolation insulating film or ^{p +} -type semiconductor layer 15.
An n-type second semiconductor layer 24 a having a convex shape with respect to the semiconductor substrate 10 is formed on the n-type first semiconductor layer 13. The second semiconductor layer 24a is made of, for example, silicon. A p-type third semiconductor layer 25 is formed on the surface of the n-type second semiconductor layer 24a.
The n-type first semiconductor layer 13, the n-type second semiconductor layer 24a, and the p-type third semiconductor layer 25 constitute a photodiode having a HAD (hole accumulated diode) structure.

The layout of the n-type second semiconductor layer 24a in the cross section a in FIG. 2 and the layout of the n-type second semiconductor layer 24a in the cross section of b are indicated by a one-dot chain line a and two-dot chain line b in FIG. Has been.
As described above, the n-type second semiconductor layer 24 a has a shape in which the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 decreases as the distance from the semiconductor substrate 10 increases.

Further, for example, the transfer gate electrode 22a is formed on the semiconductor substrate 10 in the transfer gate electrode region _ATG, which is a region adjacent to the photodiode, via the gate insulating film 21a.
In addition, sidewall insulating films made of the first sidewall insulating film 30a and the second sidewall insulating film 31a are formed on both sides of the transfer gate electrode 22a.

Further, the photodiode of the transfer gate electrode 22a in the semiconductor substrate 10 in the floating diffusion region A _FD on the opposite side, the floating diffusion 14 is formed an n-type semiconductor layer.

An n-type fourth semiconductor layer 24 b having a convex shape with respect to the semiconductor substrate 10 is formed on the floating diffusion 14. The fourth semiconductor layer 24b is made of, for example, silicon.
Similar to the n-type second semiconductor layer 24 a, the n-type fourth semiconductor layer 24 b has a shape that becomes smaller as the cross-sectional area in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10.

  The transfer gate electrode 22a and the floating diffusion 14 constitute a signal reading unit that reads a signal charge generated and stored in the photodiode or a voltage corresponding to the signal charge.

In the present embodiment, the n-type second semiconductor layer 24a and the p-type third semiconductor layer 25 are formed apart from the transfer gate electrode 22a and the sidewall insulating films (30a, 31a) formed on the side walls thereof. Has been.
This is a layer in which, for example, the n-type second semiconductor layer 24a is formed by facet epitaxial growth, and the shape of the cross section in a plane parallel to the surface of the semiconductor substrate 10 decreases as the distance from the semiconductor substrate 10 decreases. It is by having.

  In the solid-state imaging device of the present embodiment, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode and the sidewall insulating film formed on the sidewall thereof, and crystal defects are generated in the semiconductor layer. It is possible to avoid deterioration of pixel characteristics due to.

Further, the n-type fourth semiconductor layer 24b is formed apart from the transfer gate electrode 22a and the sidewall insulating films (30a, 31a) formed on the side walls thereof.
This is, for example, a layer in which the n-type fourth semiconductor layer 24b is formed by facet epitaxial growth, and has a shape that decreases as the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10. It is by having.

In the prior art, the silicon layer formed by epitaxial growth on the floating diffusion region is configured to be close to the transfer gate electrode through the sidewall insulating film.
Therefore, the parasitic capacitance between the silicon layer and the transfer gate electrode is increased, which causes a problem that the photoelectric conversion efficiency is lowered.

  In the present embodiment, the semiconductor layer formed by epitaxial growth constituting the floating diffusion is formed apart from the transfer gate electrode and the sidewall insulating film formed on the side wall thereof. A decrease in photoelectric conversion efficiency caused by an increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode can be suppressed.

In the photodiode region A _PD , transfer gate electrode region A _TG and floating diffusion region A _FD , a first interlayer insulating film 34 made of, for example, silicon oxide is formed on the entire surface. A second interlayer insulating film 35 made of silicon nitride and a third interlayer insulating film 36 made of silicon oxide are formed thereon.
A contact reaching the transfer gate electrode 22a through the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 is opened, the plug 28a is buried, and an upper layer wiring 29a is formed on the upper layer. Is formed.

Similarly, a contact that reaches the n-type fourth semiconductor layer 24b through the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 is opened, and the plug 28b is embedded, An upper layer wiring 29b is formed in the upper layer.
As described above, the light receiving surface including the pixel region is formed.

On the other hand, a logic region A _LG is formed in a region different from the light receiving surface of the semiconductor substrate 10.
In the logic region _ALG , for example, a channel formation region is formed in the p-type region of the semiconductor substrate 10 separated by the STI type element isolation insulating film 12, and a gate electrode 22b is formed in the upper layer via the gate insulating film 21b. Has been.
A sidewall insulating film made up of the first sidewall insulating film 30b and the second sidewall insulating film 31b is formed on both sides thereof.
An n-type extension region 16 is formed in the semiconductor substrate 10 below the sidewall insulating film, and an n-type source / drain region 17 is formed in the semiconductor substrate 10 on the side thereof.

An n-type fifth semiconductor layer 24 c having a convex shape with respect to the semiconductor substrate 10 is formed on the n-type source / drain region 17. The fifth semiconductor layer 24c is made of, for example, silicon.
Similar to the n-type second semiconductor layer 24 a, the n-type fifth semiconductor layer 24 c has a shape in which the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 decreases as the distance from the semiconductor substrate 10 increases.

A refractory metal silicide layer 26 is formed on the upper surface of the n-type fifth semiconductor layer 24c.
Similarly, a refractory metal silicide layer 27 is formed on the upper surface of the gate electrode 22b.

A third interlayer insulating film 36 made of, for example, silicon oxide is formed on the entire surface of the logic region _ALG .
A contact reaching the refractory metal silicide layer 26 passing through the third interlayer insulating film 36 and connected to the n-type fifth semiconductor layer 24c is opened, the plug 28c is buried, and an upper layer wiring 29c is formed thereon. Has been.
A contact reaching the refractory metal silicide layer 27 passing through the third interlayer insulating film 36 and connected to the gate electrode 22b is opened, a plug 28d is buried, and an upper layer wiring 29d is formed in the upper layer.
As described above, MOS transistors are configured, and a logic region that forms a peripheral circuit including these is formed.
In the above description, the NMOS transistor has been described. However, the present invention is not limited to this, and the present invention can be applied to a PMOS transistor.

As shown in FIG. 2, the source / drain region of the MOS transistor formed in the logic region _ALG reaches a certain depth at the end, but is formed from a relatively shallow diffusion layer in most of the central region. Has been.
This is because the shape of the n-type fifth semiconductor layer 24c is transferred to the profile of the source / drain region by ion implantation through the n-type fifth semiconductor layer 24c as will be described later.
Having the source / drain of the above structure is effective in suppressing the short channel effect accompanying the miniaturization of the MOS transistor.

FIG. 3 is an enlarged schematic cross-sectional view of a main part of the solid-state imaging device according to the present embodiment.
The n-type second semiconductor layer 24a has a convex shape having a shape in which the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes smaller from the semiconductor substrate 10 as described above. It has the effect | action of the lens which condenses.
The surface of the n-type second semiconductor layer 24 a and the p-type third semiconductor layer 25 on the n-type second semiconductor layer 24 a has a shape having an oblique facet surface with respect to the surface of the semiconductor substrate 10. For this purpose, the light L is optically refracted in the traveling direction of the refracted light Lr from the traveling direction Lt of the original light. That is, it has a function of refracting toward the photodiode region.
As described above, the light condensing property can be improved.

In addition, the distance d between the n-type second semiconductor layer 24a and the p-type third semiconductor layer 25 and the sidewall insulating films (30a, 31a) can be secured.
Thereby, crystal defects generated in the n-type second semiconductor layer 24a and the p-type third semiconductor layer 25 can be reduced, and deterioration of pixel characteristics can be avoided.
In addition, the structure of the floating diffusion 14 has the same structure, and a reduction in photoelectric conversion efficiency caused by an increase in parasitic capacitance between the n-type fourth semiconductor layer 24b and the transfer gate electrode can be suppressed.

[Method for Manufacturing Solid-State Imaging Device]
Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS.
First, as shown in FIG. 4A, a trench is formed in a semiconductor substrate 10 with a predetermined depth using a hard mask, and silicon oxide is buried, so that an STI-type element isolation insulating film 11 and logic in the pixel region are formed. An STI type element isolation insulating film 12 in the region is formed.
The STI type element isolation insulating film 11 in the pixel region has a thickness of, for example, about 20 to 50 nm. The STI type element isolation insulating film 12 in the logic region has a thickness of about 100 to 200 nm.
Next, for example, silicon oxide is deposited on the entire surface by a CVD (Chemical Vapor Deposition) method to form the screen insulating film 20.

Next, as shown in FIG. 4B, a resist film opening a predetermined region is patterned and n-type impurities or p-type impurities are ion-implanted. Thereby, the n-type first semiconductor layer 13 is formed in the photodiode region _APD . Further, the floating diffusion 14 which is an n-type semiconductor layer is formed in the floating diffusion region A _FD . Further, the p ⁺ type semiconductor layer 15 and other p type well and n type well are formed.
Also, in the logic region A _LG , impurities are ion-implanted into the channel formation region or the like as necessary.
For example, the n-type first semiconductor layer 13 implants P with an energy of 500 to 800 keV and a dose of 1.0 × 10 ¹² (/ cm ² ).
For example, in a p-type well, B is implanted at an energy of 230 keV with a dose of 2.0 × 10 ¹³ (/ cm ² ).
For example, in an n-type well, P is implanted at a dose of 3.0 × 10 ¹³ (/ cm ² ) with an energy of 500 keV.
For example, in the channel formation region of the NMOS transistor, B is implanted at a dose of 1.0 × 10 ¹³ (/ cm ² ) with an energy of 20 keV.
For example, in the channel formation region of the PMOS transistor, P is implanted with energy of 50 keV and a dose of 6.0 × 10 ¹² (/ cm ² ).

Next, as shown in FIG. 5A, the screen insulating film 20 is removed. Next, silicon oxide to be a gate insulating film is formed with a thickness of 2 nm by, for example, a thermal oxidation method, polysilicon to be a gate electrode is formed by a CVD method, silicon nitride is formed thereon, and a transfer gate electrode Process to the pattern. As described above, the gate insulating film 21a, the transfer gate electrode 22a, and the silicon nitride film 23a are formed in the transfer gate electrode region _ATG . A silicon oxide film (not shown) having a thickness of about 2 nm is appropriately formed on the side wall surface of the transfer gate electrode 22a.
Similarly, in the logic region _ALG , a gate insulating film 21b, a gate electrode 22b, and a silicon nitride film 23b that form a transistor are formed. A silicon oxide film (not shown) having a thickness of about 2 nm is appropriately formed on the side wall surface of the gate electrode 22b.

Next, as shown in FIG. 5B, in the logic region _LG , p-type impurities are ion-implanted using the gate electrode 22b as a mask to form the extension region 16.
For example, As is implanted at an energy of 1.5 keV with a dose of 6.0 × 10 ¹⁴ (/ cm ² ).
Further, an impurity region called Halo is formed by ion implantation in an oblique direction as necessary.
For example, BF ₂ is implanted at an energy of 40 keV at a dose of 2.0 × 10 ¹⁵ (/ cm ² ), or As is implanted at an energy of 50 keV at a dose of 2.0 × 10 ¹³ (/ cm ² ). inject.

Next, as shown in FIG. 6A, a silicon oxide film is formed at 10 nm on the entire surface by, eg, CVD, a silicon nitride film is formed at 20 nm, a silicon oxide film is formed at 35 nm, and etch back is performed on the entire surface. To do. Thus, the first sidewall insulating film 30a, the second sidewall insulating film 31a, and the third sidewall insulating film 32a are formed on both sides of the transfer gate electrode 22a.
In the above, similarly, the first sidewall insulating film 30b, the second sidewall insulating film 31b, and the third sidewall insulating film 32b are formed on both sides of the gate electrode 22b in the logic region _LG .
The first insulating film 30c, the second insulating film 31c, and the third insulating film 32c are left on the p ⁺ type semiconductor layer 15.
When forming the sidewall insulating film, it is necessary to reduce damage to the photodiode. For example, the outer silicon oxide film and the silicon nitride film are removed by dry etching, and the inner silicon oxide film is wet etched. The method of removing by can be considered.
Further, the p ⁺ type semiconductor layer 15 is subjected to resist patterning so that the material of the sidewall insulating film remains. This is because epitaxial growth is not performed in the region of the p ⁺ type semiconductor layer 15 in the subsequent epitaxial growth step.

  Next, as shown in FIG. 6B, DHF treatment is performed to remove the natural oxide film on the surface of the silicon semiconductor substrate 10. At this time, the third sidewall insulating films (32a, 32b) and the third insulating film 32c are also removed at the same time.

Next, as shown in FIG. 7A, immediately after the DHF cleaning, silicon is selectively epitaxially grown so as to have a facet surface. Thereby, the second semiconductor layer 24a is formed in the photodiode region _APD . Further, to form a fourth semiconductor layer 24b in the floating diffusion region _{A FD.} Further, to form a fifth semiconductor layer 24c on the region to be a source drain region of the logic region A _LG.
The epitaxial growth described above can change the angle of the facet plane depending on conditions, and can form a plurality of plane orientations.
For example, the growth temperature is 750 ° C., the pressure is 10 Torr, the gas is SiH ₂ Cl ₂ (100 sccm) and HCL (25 sccm), and the boron concentration is 140 sccm using B ₂ H ₆ .

Next, as shown in FIG. 7B, a resist film opening a predetermined region is patterned and n-type impurities or p-type impurities are ion-implanted. As a result, the source / drain region 17 is formed in the logic region _ALG .
The shape of the fifth semiconductor layer 24c is transferred to the profile in the source / drain region 17, and reaches a certain depth at the end portion, but has a relatively shallow profile in most of the central region.
Also, n-type impurities are appropriately ion-implanted into the second semiconductor layer 24a, the fourth semiconductor layer 24b, and the like by epitaxial growth.
For example, in the source / drain region of the NMOS transistor, P is implanted at a dose of 4.0 × 10 ¹⁵ (/ cm ² ) with an energy of 20 keV. In the source / drain region of the PMOS transistor, B is implanted with energy of 4 keV at a dose of 4.0 × 10 ¹⁵ (/ cm ² ).
For example, As is implanted into the second semiconductor layer 24a and the like at a dose of 1.0 × 10 ^{12 to} 2.0 × 10 ¹² (/ cm ² ) with energy of 100 to 300 keV.

Next, as shown in FIG. 8A, the silicon nitride film 23a and the silicon nitride film 23b are removed.
Next, as shown in FIG. 8B, a resist film 33 that opens the photodiode region _APD is patterned, p-type impurities are ion-implanted, and p-type impurities are implanted into the surface layer portion of the second semiconductor layer 24a. A third semiconductor layer 25 is formed.
For example, B is implanted at a dose of 1.0 × 10 ¹³ (/ cm ² ) with an energy of 3 keV.
Next, a spike annealing process for activating impurity ions is performed. For example, the temperature is set to 1000 to 1070 ° C. by RTA (Rapid Thermal Annealing) processing.

  Next, as shown in FIG. 9A, silicon oxide is deposited on the entire surface by, eg, CVD to form a first interlayer insulating film 34, and then silicon nitride is deposited to form a second interlayer insulating film 35. Form.

Next, as shown in FIG. 9B, for example, a resist film that opens the logic region A _LG is patterned, and a dry etching process and a wet etching process are performed to form the first interlayer insulating film 34 in the logic region A _LG and The second interlayer insulating film 35 is removed.
It is preferable that part of the upper silicon nitride and the lower silicon oxide is removed by dry etching, and the remaining silicon oxide is removed by wet etching.
Using this method, it is possible to suppress the damage to the silicon in the logic area A _LG by dry etching.
However, even if wet etching is not used, a fatal problem does not occur.

Then, after the opening of the logic area A _LG, and Co and Ni were deposited to a thickness of 2~8nm by sputtering, by performing the silicidation process, a refractory metal silicide layer self-aligned manner Form. A so-called salicide layer is formed. Here, the refractory metal silicide layer 26 is formed on the upper surface of the n-type fifth semiconductor layer 24c, and the refractory metal silicide layer 27 is formed on the upper surface of the gate electrode 22b. Unreacted refractory metal is removed.

Next, a third interlayer insulating film 36 is formed by depositing a silicon oxide film with a film thickness of 500 to 700 nm on the entire surface by, eg, CVD, and planarized by CMP (Chemical Mechanical Polishing).
After the above, for example, a contact reaching the transfer gate electrode 22a and the like through the third interlayer insulating film 36 is opened, and a barrier metal film (not shown) made of Ti (30 nm) / TiN (10 nm) is formed. Plugs (28a, 28b, 28c) made of W or the like are formed.
Connected to the plugs (28a, 28b, 28c), upper layer wirings (29a, 29b, 29c) are formed.
As described above, the solid-state imaging device having the configuration shown in FIG. 2 can be manufactured.

  After the above, wirings, waveguides, on-chip lenses, color filters, and the like are formed as necessary by a commonly used method.

  In the manufacturing method of the solid-state imaging device according to the present embodiment, the semiconductor layer formed by epitaxial growth that constitutes the photodiode is formed apart from the transfer gate electrode and the sidewall insulating film. Deterioration can be avoided.

  In addition, since the semiconductor layer formed by epitaxial growth constituting the floating diffusion is formed apart from the transfer gate electrode and the sidewall insulating film, the photoelectric conversion efficiency is lowered due to the increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode. Can be suppressed.

<First Modification>
[Configuration of Solid-State Imaging Device Having Curved Shape Epitaxial Semiconductor Layer]
FIG. 10 is an enlarged schematic cross-sectional view of a main part of the solid-state imaging device according to this modification.
Compared to FIG. 3, the corners of the second semiconductor layer 24a formed by epitaxial growth are removed to form a curved surface, which is closer to the lens shape.
A third semiconductor layer 25 is formed on the curved second semiconductor layer 24a.

[Method for Manufacturing Solid-State Imaging Device]
FIGS. 11A and 11B are schematic cross-sectional views showing the manufacturing steps of the manufacturing method of this modification.
The process up to the step shown in FIG. 7B is performed as described above, and the surface is oxidized as shown in FIG. Thereby, the silicon oxide film 24d is formed thick near the corner of the second semiconductor layer 24a. For this reason, the surface of the second semiconductor layer 24a has a curved shape.
Next, as shown in FIG. 11B, the silicon oxide film 24d is removed by performing DHF treatment or the like.
After the above, it can carry out similarly to the above-mentioned 1st Embodiment.

Second Embodiment
[Configuration of solid-state imaging device having p-type semiconductor layer by in-situ B-doped epitaxial growth]
FIG. 12 is a cross-sectional view of a solid-state imaging device according to the second embodiment of the present invention.
The p-type third semiconductor layer 25a is a layer formed by in-situ B-doped epitaxial growth.
In the pixel region, a first interlayer insulating film 37 of silicon oxide, a second interlayer insulating film 38 of silicon nitride, a third interlayer insulating film 39 of silicon nitride, and a fourth interlayer insulating film 40 of silicon oxide are formed. .
Except for the above, the configuration is substantially the same as that of the solid-state imaging device of the first embodiment.

  In the solid-state imaging device of the present embodiment, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode and the sidewall insulating film formed on the sidewall thereof, and crystal defects are generated in the semiconductor layer. It is possible to avoid deterioration of pixel characteristics due to.

  In particular, the p-type third semiconductor layer 25a formed by in-situ B-doped epitaxial growth has much smaller impurity diffusion than the p-type semiconductor layer formed by impurity diffusion by ion implantation or the like. Therefore, Qs can be improved as compared with a method using normal ion implantation.

  In the solid-state imaging device of the present embodiment, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode and the sidewall insulating film formed on the sidewall thereof, and crystal defects are generated in the semiconductor layer. It is possible to avoid deterioration of pixel characteristics due to.

  In the solid-state imaging device according to the present embodiment, the semiconductor layer formed by epitaxial growth constituting the floating diffusion is formed apart from the transfer gate electrode and the sidewall insulating film formed on the side wall thereof. A decrease in photoelectric conversion efficiency caused by an increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode can be suppressed.

[Method for Manufacturing Solid-State Imaging Device]
Next, a method for manufacturing the solid-state imaging device according to this embodiment will be described with reference to FIGS.
First, the steps up to the step shown in FIG. 8A of the first embodiment are performed in the same manner as in the first embodiment.
Next, as shown in FIG. 13A, silicon oxide is deposited on the entire surface by, eg, CVD to form a first interlayer insulating film 37, and then silicon nitride is deposited to form a second interlayer insulating film 38. Form.

Next, as shown in FIG. 13B, a resist film (not shown) that opens the photodiode region _APD is patterned to form a first interlayer insulating film 37 and a second interlayer insulating film 38 in the photodiode region _APD . Remove.
For example, in order to reduce damage to the photodiode, it is preferable to process the second interlayer insulating film 38 made of silicon nitride by dry etching and the first interlayer insulating film 37 made of silicon oxide by wet etching.
Next, a p-type third semiconductor layer 25a is formed in-situ on the surface layer of the second semiconductor layer 24a by in-situ B-doped epitaxial growth.
The third semiconductor layer 25a has an impurity concentration of 1.0 × 10 ¹⁷ (1 / cm ³ ) and a thickness of 5 nm.
The third semiconductor layer 25a is designed to be connected to the p-type well of the semiconductor substrate.
Next, spike annealing is performed for impurity activation. For example, the RTA process is performed at 1000 to 1070 ° C.

  Next, as shown in FIG. 14A, a third interlayer insulating film 39 is formed by depositing silicon nitride on the entire surface by, eg, CVD.

Next, as shown in FIG. 14B, for example, a resist film that opens the logic region A _LG is patterned, and dry etching processing and wet etching processing are performed to form a first interlayer insulating film 37 in the logic region A _LG , The second interlayer insulating film 38 and the third interlayer insulating film 39 are removed.

Then, a refractory metal silicide layer 26 is formed on the upper surface of the fifth semiconductor layer 24c of the n-type logic region A _LG, to form a refractory metal silicide layer 27 on the upper surface of the gate electrode 22b. Unreacted refractory metal is removed.
The subsequent steps can be performed in the same manner as in the first embodiment.
As described above, the solid-state imaging device having the configuration shown in FIG. 12 can be manufactured.

  In the manufacturing method of the solid-state imaging device according to the present embodiment, the semiconductor layer formed by epitaxial growth that constitutes the photodiode is formed apart from the transfer gate electrode and the sidewall insulating film. Deterioration can be avoided.

  In addition, since the semiconductor layer formed by epitaxial growth constituting the floating diffusion is formed apart from the transfer gate electrode and the sidewall insulating film, the photoelectric conversion efficiency is lowered due to the increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode. Can be suppressed.

<Third Embodiment>
[Configuration of solid-state imaging device]
The plan view of the light receiving surface of the solid-state imaging device according to the present embodiment is substantially the same as the plan view of FIG. 1 according to the first embodiment.
FIG. 15 is a schematic cross-sectional view of a CMOS image sensor, which is a solid-state imaging device according to this embodiment, in which a plurality of pixels are integrated.
In the drawing, a logic region A _LG constituting a peripheral circuit of the pixel region is shown. The pixel region indicates a photodiode region A _PD , a transfer gate electrode region A _TG and a floating diffusion region A _FD .
15 is equivalent to the cross section taken along AB in FIG. 1, and the cross sectional view taken along line CD corresponding to the logic area _ALG is shown in FIG. It corresponds to the area that is not.

An n-type second semiconductor layer 24 d having a convex shape with respect to the semiconductor substrate 10 is formed on the n-type first semiconductor layer 13. The second semiconductor layer 24d is formed of a material having a band gap smaller than that of silicon. For example, Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se ₂ , Cu (In, Ga) (Se, S) ₂ , CuInS ₂ It is formed from. When Si material is used for the light absorption layer, there may be a problem that sensitivity in the infrared region is low or insensitive. The above materials have a larger light absorption coefficient than silicon, particularly in the red wavelength region. Therefore, a photodiode using these materials is a photodiode having high sensitivity to light in the red to infrared region.

In the present embodiment, an n-type fourth semiconductor layer 24 e having a convex shape with respect to the semiconductor substrate 10 is formed on the floating diffusion 14. The fourth semiconductor layer 24e is made of, for example, Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, or InSb, like the second semiconductor layer 24d.
In addition, an n-type fifth semiconductor layer 24 f having a convex shape with respect to the semiconductor substrate 10 is formed on the source / drain region 17. Similarly to the second semiconductor layer 24d, the fifth semiconductor layer 24f is, for example, Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se _2. , Cu (In, Ga) (Se, S) ₂ , CuInS ₂ or the like.
Except for the above, the configuration is the same as that of the first embodiment.

The layout of the n-type second semiconductor layer 24d in the cross section a in FIG. 15 and the layout of the n-type second semiconductor layer 24d in the cross section b in FIG. The layout is the same as that of the illustrated first embodiment.
As described above, the n-type second semiconductor layer 24 dd has a shape that decreases as the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10.

  In the solid-state imaging device of the present embodiment, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode and the sidewall insulating film formed on the sidewall thereof, and crystal defects are generated in the semiconductor layer. It is possible to avoid deterioration of pixel characteristics due to.

  In the present embodiment, the semiconductor layer formed by epitaxial growth constituting the floating diffusion is formed apart from the transfer gate electrode and the sidewall insulating film formed on the side wall thereof. A decrease in photoelectric conversion efficiency caused by an increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode can be suppressed.

As shown in FIG. 15, the source / drain region of the MOS transistor formed in the logic region _ALG reaches a certain depth at the end, but is formed from a relatively shallow diffusion layer in most of the central region. Has been.
Having the source / drain of the above structure is effective in suppressing the short channel effect accompanying the miniaturization of the MOS transistor.
In addition, Si _1-x Ge _x (0 <x <1) is epitaxially grown on the MOSFET of the peripheral circuit that performs image processing to increase the drive current of the MOSFET, thereby improving the peripheral circuit characteristics and image processing. Ability can be improved. In addition, the area of the peripheral circuit can be reduced.

<Fourth embodiment>
[Configuration of solid-state imaging device]
FIG. 16 is a plan view of a region corresponding to four pixels on the light receiving surface of the solid-state imaging device according to the present embodiment.
For example, photodiodes (PD1, PD2, PD3, PD4) are formed in the photodiode region divided for each pixel on the light receiving surface where a plurality of pixels of the semiconductor substrate are integrated.
Transfer gate electrodes (TG1, TG2, TG3, TG4) are formed on the semiconductor substrate in a region adjacent to the photodiode.
A floating diffusion FD is formed in the semiconductor substrate on the opposite side of the transfer gate electrode (TG1, TG2, TG3, TG4) from the photodiode (PD1, PD2, PD3, PD4).
The floating diffusion FD includes, for example, a first floating diffusion FD1 and a second floating diffusion FD2 that are divided into regions and have different impurity concentrations.
A signal reading unit that reads a signal charge generated or accumulated in the photodiode (PD1, PD2, PD3, PD4) or a voltage corresponding to the signal charge from the transfer gate electrode (TG1, TG2, TG3, TG4) and the floating diffusion FD. Composed.

  Here, the photodiode PD1 is a red pixel that sensitizes red light, and a red filter RF is formed in the photodiode PD1 region. The photodiodes PD2 and PD3 are green pixels that are sensitive to green light, and a green filter GF is formed in the photodiode PD2 and 3 regions. The photodiode PD4 is a blue pixel that sensitizes blue light, and a blue filter BF is formed in the photodiode PD4 region.

FIG. 17 is a schematic cross-sectional view of a CMOS image sensor, which is a solid-state imaging device according to this embodiment, in which a plurality of pixels are integrated.
In the drawing, a logic region A _LG constituting a peripheral circuit of the pixel region is shown. The pixel region indicates a photodiode region A _PD , a transfer gate electrode region A _TG and a floating diffusion region A _FD .
In addition, a cross-sectional view taken along a line AB corresponding to the pixel region in FIG. 17 corresponds to a cross-section taken along a line AB in FIG.
A cross-sectional view taken along the line _CD corresponding to the logic region _ALG in FIG. 17 corresponds to a region not shown in FIG.

For example, the n-type first semiconductor layer 13 formed on the semiconductor substrate is formed in the photodiode region _{APD divided} for each pixel on the light receiving surface where a plurality of pixels of the semiconductor substrate 10 made of silicon are integrated. Yes.
The photodiode region _APD is _divided by, for example, an STI type element isolation insulating film or a p ⁺ type semiconductor layer 15.

Here, the recess in the photodiode region A _PD of the red pixel (recess) R _PD is formed, connected to the first semiconductor layer 13, the n-type embedded in recess R _PD buried layer 24g is formed ing. The portion in the concave portion of the buried layer 24g corresponds to the same layer as the first semiconductor layer 13 formed on the substrate, and the portion having a convex shape with respect to the semiconductor substrate 10 is the second semiconductor layer of the first embodiment. This corresponds to 24a. The buried layer 24g can be regarded as a layer in which the first semiconductor layer and the second semiconductor layer are integrally formed.
The buried layer 24g is made of a material having a band gap smaller than that of silicon. For example, Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se ₂ , Cu (In, Ga) (Se, S) ₂ , CuInS ₂ It is formed from. When Si material is used for the light absorption layer, there may be a problem that sensitivity in the infrared region is low or insensitive. The above materials have a larger light absorption coefficient than silicon, particularly in the red wavelength region. For this reason, a photodiode using these materials becomes a photodiode having high sensitivity to light in the red to infrared region, and is a photodiode suitable for a red pixel.
A p-type third semiconductor layer 25 is formed on the surface of the buried layer 24g.
The n-type buried layer 24g and the p-type third semiconductor layer 25 constitute a photodiode with a HAD structure.

The layout of the n-type buried layer 24g in the section a in FIG. 17 and the layout of the n-type buried layer 24g in the section b in FIG. 17 are indicated by a one-dot chain line a and two-dot chain line b in FIG.
The portion of the buried layer 24g having a convex shape with respect to the semiconductor substrate 10 corresponds to the second semiconductor layer 24a of the first embodiment, and the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 is It has a shape that decreases with increasing distance from the semiconductor substrate 10.

On the other hand, a p-type third semiconductor layer 25 is formed on the surface of the first semiconductor layer 13 in the photodiode region _APD of the green pixel and the blue pixel.
The n-type first semiconductor layer 13 and the p-type third semiconductor layer 25 constitute a photodiode with an HAD structure.

Further, for example, the transfer gate electrode 22a is formed on the semiconductor substrate 10 in the transfer gate electrode region _ATG, which is a region adjacent to the photodiode, via the gate insulating film 21a.
In addition, sidewall insulating films including a first sidewall insulating film 30a, a second sidewall insulating film 31a, and a third sidewall insulating film 32a are formed on both sides of the transfer gate electrode 22a. Although the third sidewall insulating film 32a is left in the shape of the first embodiment, the third sidewall insulating film 32a may be removed.

Further, the photodiode of the transfer gate electrode 22a in the semiconductor substrate 10 in the floating diffusion region A _FD on the opposite side, the floating diffusion 14 is formed an n-type semiconductor layer.

  The transfer gate electrode 22a and the floating diffusion 14 constitute a signal reading unit that reads a signal charge generated and stored in the photodiode or a voltage corresponding to the signal charge.

In the present embodiment, the n-type buried layer 24g and the p-type third semiconductor layer 25 are formed apart from the transfer gate electrode 22a and the sidewall insulating films (30a, 31a, 32a) formed on the side walls thereof. Has been.
This is because, for example, the convex portion of the n-type buried layer 24g with respect to the semiconductor substrate 10 is formed by facet epitaxial growth. A portion having a convex shape with respect to the semiconductor substrate 10 has a shape that becomes smaller as the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10.

  In the solid-state imaging device of the present embodiment, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode and the sidewall insulating film formed on the sidewall thereof, and crystal defects are generated in the semiconductor layer. It is possible to avoid deterioration of pixel characteristics due to.

In the solid-state imaging device of the present embodiment, a material having a band gap smaller than that of silicon is used in the red pixel as described above, and the sensitivity to light in the red to infrared region is greatly improved.
In addition, by forming a recess in the photodiode region, it is possible to suppress the height of the convex portion with respect to the surface of the semiconductor substrate 10 while ensuring the film thickness as the buried layer. . For this reason, since the level | step difference resulting from the unevenness | corrugation by convex shape can be suppressed, the thickness of the whole insulating film required for planarization can be suppressed, and characteristics, such as a sensitivity of a photodiode, can be implement | achieved.
By using a material having a high light absorption coefficient, the depth of the recess can be reduced. For example, when the light absorption coefficient is improved by an order of magnitude, the depth of the recess can be reduced by an order of magnitude.
The semiconductor layer formed by the above epitaxial growth can be formed by a low temperature process of about 400 ° C., for example.

In the photodiode region A _PD , transfer gate electrode region A _TG and floating diffusion region A _FD , a first interlayer insulating film 34 made of, for example, silicon oxide is formed on the entire surface. A second interlayer insulating film 35 made of silicon nitride and a third interlayer insulating film 36 made of silicon oxide are formed thereon.
A contact reaching the transfer gate electrode 22a through the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 is opened, the plug 28a is buried, and an upper layer wiring 29a is formed on the upper layer. Is formed.

Similarly, a contact that reaches the n-type fourth semiconductor layer 24b through the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 is opened, and the plug 28b is embedded, An upper layer wiring 29b is formed in the upper layer.
As described above, the light receiving surface including the pixel region is formed.

On the other hand, a logic region A _LG is formed in a region different from the light receiving surface of the semiconductor substrate 10.
In the logic region _ALG , for example, a channel formation region is formed in the p-type region of the semiconductor substrate 10 separated by the STI type element isolation insulating film 12, and a gate electrode 22b is formed in the upper layer via the gate insulating film 21b. Has been.
A sidewall insulating film made up of the first sidewall insulating film 30b and the second sidewall insulating film 31b is formed on both sides thereof.
An n-type extension region 16 is formed in the semiconductor substrate 10 below the sidewall insulating film, and an n-type source / drain region 17 is formed in the semiconductor substrate 10 on the side thereof.

A refractory metal silicide layer 26 is formed on the upper surface of the source / drain region 17.
Similarly, a refractory metal silicide layer 27 is formed on the upper surface of the gate electrode 22b.

A third interlayer insulating film 36 made of, for example, silicon oxide is formed on the entire surface of the logic region _ALG .
A contact reaching the refractory metal silicide layer 26 passing through the third interlayer insulating film 36 and connected to the n-type source / drain region 17 is opened, a plug 28c is embedded, and an upper layer wiring 29c is formed thereon. ing.
A contact reaching the refractory metal silicide layer 27 passing through the third interlayer insulating film 36 and connected to the gate electrode 22b is opened, a plug 28d is buried, and an upper layer wiring 29d is formed in the upper layer.
As described above, MOS transistors are configured, and a logic region that forms a peripheral circuit including these is formed.
In the above description, the NMOS transistor has been described. However, the present invention is not limited to this, and the present invention can be applied to a PMOS transistor.

[Method for Manufacturing Solid-State Imaging Device]
Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS.
First, the process up to the configuration shown in FIG. 18A is performed in the same manner as the process shown in FIG. 5B of the first embodiment.
Next, as shown in FIG. 18B, a silicon oxide film 30 is formed with a thickness of 10 nm, a silicon nitride film 31 is formed with a thickness of 20 nm, and a silicon oxide film 32 is formed with a thickness of 35 nm, for example, by CVD.

Next, as shown in FIG. 19A, a resist film RS that opens the photodiode region of the red pixel is patterned by a photolithography process.
Next, using the resist film RS as a mask, the semiconductor substrate 10 is etched away to a predetermined depth to form a recess _RPD .
Although the shape of the recess _RPD is not particularly limited, for example, when formed by anisotropic etching, a recess having a rectangular cross section as shown in FIG. 19A can be formed.

Next, as shown in FIG. 19 (b), after removing the resist film RS, to form a buried layer 24g of n-type embedded in recess R _PD by epitaxial growth.
Buried layer 24g, the portion of the recess R _PD is formed by conventional epitaxial growth, a portion having a convex shape with respect to the semiconductor substrate 10 is formed by epitaxial growth so as to have a facet.
The epitaxial growth described above can change the angle of the facet plane depending on conditions, and can form a plurality of plane orientations.
For example, when forming the buried layer 24g made of Si _1-x Ge _x (0 <x <1), the growth temperature is 750 ° C., the pressure is 10 Torr, the gas is SiH ₂ Cl ₂ (100 sccm), the HCL (25 sccm), It is formed as 140 sccm using GeH ₄ (50-100 sccm) and boron concentration: B ₂ H ₆ . Further, it can be formed by a low temperature process of about 400 ° C., for example.

Next, as shown in FIG. 20A, the silicon oxide film 30, the silicon nitride film 31, and the silicon oxide film 32 are etched back over the entire surface. As a result, a sidewall insulating film including the first sidewall insulating film 30a, the second sidewall insulating film 31a, and the third sidewall insulating film 32a is formed on both sides of the transfer gate electrode 22a.
In the above, similarly, a sidewall insulating film composed of the first sidewall insulating film 30b, the second sidewall insulating film 31b, and the third sidewall insulating film 32b is formed on both sides of the gate electrode 22b in the logic region _LG. To do.
Here, although the first insulating film 30c, the second insulating film 31c, and the third insulating film 32c are left on the p ⁺ type semiconductor layer 15, they may not be left in this embodiment.
When forming the sidewall insulating film, dry etching and wet etching can be used as appropriate.

Next, as shown in FIG. 20B, a resist film opening a predetermined region is patterned, and n-type impurities or p-type impurities are ion-implanted. As a result, the source / drain region 17 is formed in the logic region _ALG .
In addition, impurities are appropriately ion-implanted into the buried layer 24g, the first semiconductor layer 13, the floating diffusion 14, and the like.
For example, in the source / drain region of the NMOS transistor, P is implanted at a dose of 4.0 × 10 ¹⁵ (/ cm ² ) with an energy of 20 keV. In the source / drain region of the PMOS transistor, B is implanted with energy of 4 keV at a dose of 4.0 × 10 ¹⁵ (/ cm ² ).
Subsequent steps can be manufactured by substantially the same steps as in the first embodiment.
With the above, a solid-state imaging device having the configuration shown in FIG. 17 can be manufactured.

  After the above, wirings, waveguides, on-chip lenses, color filters, and the like are formed as necessary by a commonly used method.

  In the manufacturing method of the solid-state imaging device according to the present embodiment, the semiconductor layer formed by epitaxial growth that constitutes the photodiode is formed apart from the transfer gate electrode and the sidewall insulating film. Deterioration can be avoided.

In addition, the manufacturing method of the solid-state imaging device of the present embodiment uses a material having a band gap smaller than that of silicon in the red pixel as described above, and the sensitivity to light in the red to infrared region is greatly improved.
In addition, by forming a recess in the photodiode region, it is possible to suppress the height of the convex portion with respect to the surface of the semiconductor substrate 10 while ensuring the film thickness as the buried layer. . For this reason, since the level | step difference resulting from the unevenness | corrugation by convex shape can be suppressed, the thickness of the whole insulating film required for planarization can be suppressed, and characteristics, such as a sensitivity of a photodiode, can be implement | achieved.
By using a material having a high light absorption coefficient, the depth of the recess can be reduced. For example, when the light absorption coefficient is improved by an order of magnitude, the depth of the recess can be reduced by an order of magnitude.

In the present embodiment, a recess (recess) is formed in a photodiode region in a red pixel of a solid-state imaging device having a blue pixel, a green pixel, and a red pixel, and a buried layer is embedded. It can be applied to photodiodes of all pixels.
In addition, the above configuration can be preferably applied to at least a pixel in a photosensitive wavelength region having a longer wavelength, where the pixel includes a plurality of pixels having different photosensitive wavelength regions. For example, in a solid-state imaging device having two types of pixels, a long wavelength side pixel and a short wavelength side pixel, it can be preferably applied to a long wavelength side pixel. Further, the present invention can be applied to both a long wavelength side pixel and a short wavelength side pixel.

<Fifth Embodiment>
[Configuration of solid-state imaging device]
The plan view of the light receiving surface of the solid-state imaging device according to the present embodiment is substantially the same as the plan view of FIG. 1 according to the first embodiment.
FIG. 21 is a schematic cross-sectional view of a CMOS image sensor, which is a solid-state imaging device according to this embodiment, in which a plurality of pixels are integrated.
In the drawing, a logic region A _LG constituting a peripheral circuit of the pixel region is shown. The pixel region indicates a photodiode region A _PD , a transfer gate electrode region A _TG and a floating diffusion region A _FD .
Further, a cross-sectional view taken along line AB in FIG. 21 corresponds to a cross section taken along line AB in FIG.
A cross-sectional view taken along the line _CD corresponding to the logic region A _LG in FIG. 21 corresponds to a region not shown in FIG.

For example, the n-type first semiconductor layer 13 formed on the semiconductor substrate is formed in the photodiode region _{APD divided} for each pixel on the light receiving surface where a plurality of pixels of the semiconductor substrate 10 made of silicon are integrated. Yes.
The photodiode region _APD is _divided by, for example, an STI type element isolation insulating film or a p ⁺ type semiconductor layer 15.

Here, a concave portion (recess) R _PD is in the photodiode region A _PD of all pixels is formed, connected to the first semiconductor layer 13, the recess R _PD embedded in the n-type buried layer 24h is formed Has been. The portion in the recess of the buried layer 24h corresponds to the same layer as the first semiconductor layer 13 formed on the substrate, and the portion having a convex shape with respect to the semiconductor substrate 10 is the second semiconductor layer of the first embodiment. This corresponds to 24a. The buried layer 24h can be regarded as a layer in which the first semiconductor layer and the second semiconductor layer are integrally formed.
The buried layer 24h is made of a material having a smaller band gap than silicon. For example, Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se ₂ , Cu (In, Ga) (Se, S) ₂ , CuInS ₂ It is formed from. When Si material is used for the light absorption layer, there may be a problem that sensitivity in the infrared region is low or insensitive. The above materials have a light absorption coefficient larger than that of silicon, particularly in the red wavelength region. For this reason, the photodiode using these materials becomes a highly sensitive photodiode and is a photodiode suitable for a red pixel.
A p-type third semiconductor layer 25 is formed on the surface of the buried layer 24h.
The n-type buried layer 24h and the p-type third semiconductor layer 25 constitute a photodiode with a HAD structure.

The layout of the n-type buried layer 24h in the cross section a in FIG. 21 and the layout of the n-type buried layer 24h in the cross section b are shown by a one-dot chain line a and two-dot chain line b in FIG.
The portion of the buried layer 24 h that has a convex shape with respect to the semiconductor substrate 10 corresponds to the second semiconductor layer 24 a of the first embodiment, and has a cross-sectional area in a plane parallel to the surface of the semiconductor substrate 10. It has a shape that decreases with increasing distance from the semiconductor substrate 10.

Further, for example, the transfer gate electrode 22a is formed on the semiconductor substrate 10 in the transfer gate electrode region _ATG, which is a region adjacent to the photodiode, via the gate insulating film 21a.
In addition, sidewall insulating films made of the first sidewall insulating film 30a and the second sidewall insulating film 31a are formed on both sides of the transfer gate electrode 22a.

Further, the photodiode of the transfer gate electrode 22a in the semiconductor substrate 10 in the floating diffusion region A _FD on the opposite side, the floating diffusion 14 is formed an n-type semiconductor layer.
Here, the recess in the floating diffusion region A _FD (recess) R _FD and is formed by connecting the floating diffusion 14, the buried layer 24i an n-type embedded in recess R _FD is formed. A portion of the embedded layer 24 i that has a convex shape with respect to the semiconductor substrate 10 has a shape that decreases as the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10.

  The transfer gate electrode 22a and the floating diffusion 14 constitute a signal reading unit that reads a signal charge generated and stored in the photodiode or a voltage corresponding to the signal charge.

In the present embodiment, the n-type buried layer 24h and the p-type third semiconductor layer 25 are formed apart from the transfer gate electrode 22a and the sidewall insulating films (30a, 31a) formed on the side walls thereof. Yes.
This is because, for example, a convex portion of the n-type buried layer 24h with respect to the semiconductor substrate 10 is a layer formed by facet epitaxial growth. A portion having a convex shape with respect to the semiconductor substrate 10 has a shape that becomes smaller as the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10.

  In the solid-state imaging device of the present embodiment, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode and the sidewall insulating film formed on the sidewall thereof, and crystal defects are generated in the semiconductor layer. It is possible to avoid deterioration of pixel characteristics due to.

Further, a convex portion of the n-type buried layer 24i with respect to the semiconductor substrate 10 is formed apart from the transfer gate electrode 22a and the side wall insulating films (30a, 31a) formed on the side walls thereof. Yes.
This is because, for example, the convex portion of the n-type buried layer 24i with respect to the semiconductor substrate 10 is formed by facet epitaxial growth. A portion having a convex shape with respect to the semiconductor substrate 10 has a shape that becomes smaller as the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10.

In the prior art, the silicon layer formed by epitaxial growth on the floating diffusion region is configured to be close to the transfer gate electrode through the sidewall insulating film.
Therefore, the parasitic capacitance between the silicon layer and the transfer gate electrode is increased, which causes a problem that the photoelectric conversion efficiency is lowered.

  In the present embodiment, the semiconductor layer formed by epitaxial growth constituting the floating diffusion is formed apart from the transfer gate electrode and the sidewall insulating film formed on the side wall thereof. A decrease in photoelectric conversion efficiency caused by an increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode can be suppressed.

In the photodiode region A _PD , transfer gate electrode region A _TG and floating diffusion region A _FD , a first interlayer insulating film 34 made of, for example, silicon oxide is formed on the entire surface. A second interlayer insulating film 35 made of silicon nitride and a third interlayer insulating film 36 made of silicon oxide are formed thereon.
A contact reaching the transfer gate electrode 22a through the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 is opened, the plug 28a is buried, and an upper layer wiring 29a is formed on the upper layer. Is formed.

Similarly, a contact reaching the n-type buried layer 24i through the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 is opened, and the plug 28b is embedded therein, and the upper layer thereof An upper layer wiring 29b is formed in the upper layer.
As described above, the light receiving surface including the pixel region is formed.

In the solid-state imaging device of the present embodiment, a material having a band gap smaller than that of silicon is used in the red pixel as described above, and the sensitivity to light in the red to infrared region is greatly improved.
In addition, by forming a recess in the photodiode region, it is possible to suppress the height of the convex portion with respect to the surface of the semiconductor substrate 10 while ensuring the film thickness as the buried layer. . For this reason, since the level | step difference resulting from the unevenness | corrugation by convex shape can be suppressed, the thickness of the whole insulating film required for planarization can be suppressed, and characteristics, such as a sensitivity of a photodiode, can be implement | achieved.
By using a material having a high light absorption coefficient, the depth of the recess can be reduced. For example, when the light absorption coefficient is improved by an order of magnitude, the depth of the recess can be reduced by an order of magnitude.
The semiconductor layer formed by the above epitaxial growth can be formed by a low temperature process of about 400 ° C., for example.

On the other hand, a logic region A _LG is formed in a region different from the light receiving surface of the semiconductor substrate 10.
In the logic region _ALG , for example, a channel formation region is formed in the n-type well 10w of the semiconductor substrate 10 separated by the STI type element isolation insulating film 12, and the gate electrode 22b is formed on the upper layer via the gate insulating film 21b. Is formed.
A sidewall insulating film made up of the first sidewall insulating film 30b and the second sidewall insulating film 31b is formed on both sides thereof.
An n-type extension region 16 is formed in the semiconductor substrate 10 below the sidewall insulating film, and a recess (recess) _RSD is formed in the semiconductor substrate 10 on the side portion thereof. Connected to the extension region 16, p-type buried layer 24j embedded in recess R _SD is formed. A portion of the buried layer 24 j that has a convex shape with respect to the semiconductor substrate 10 has a shape that becomes smaller as the area of the cross section in a plane parallel to the surface of the semiconductor substrate 10 becomes farther from the semiconductor substrate 10.

A refractory metal silicide layer 26 is formed on the upper surface of the p-type buried layer 24j.
Similarly, a refractory metal silicide layer 27 is formed on the upper surface of the gate electrode 22b.

A third interlayer insulating film 36 made of, for example, silicon oxide is formed on the entire surface of the logic region _ALG .
A contact reaching the refractory metal silicide layer 26 passing through the third interlayer insulating film 36 and connected to the n-type source / drain region 17 is opened, a plug 28c is embedded, and an upper layer wiring 29c is formed thereon. ing.
A contact reaching the refractory metal silicide layer 27 passing through the third interlayer insulating film 36 and connected to the gate electrode 22b is opened, a plug 28d is buried, and an upper layer wiring 29d is formed in the upper layer.
As described above, MOS transistors are configured, and a logic region that forms a peripheral circuit including these is formed.
In the above description, the PMOS transistor is shown. However, the present invention is not limited to this.
When Ge or Si _1-x Ge _x (0 <x <1) is used as the buried layer 24j, the characteristics of the transistor are improved by the stress applied to the channel formation region by the buried layer 24j in the PMOS transistor. large. For this reason, the image processing capability in the logic circuit is improved, and the area of the logic circuit can be reduced.

[Method for Manufacturing Solid-State Imaging Device]
Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS.
First, the process up to the configuration shown in FIG. 22A is performed in the same manner as the process shown in FIG. 6B of the first embodiment. Here, an n-well 10w is appropriately formed in the PMOS region of the logic substrate.
Next, as shown in FIG. 22B, the semiconductor substrate 10 is etched to a predetermined depth to form the recesses R _PD , the recesses R _FD and the recesses R _SD .
The shape of the concave portion R _PD , the concave portion R _FD and the concave portion R _SD is not particularly limited. However, for example, when formed by isotropic etching, a concave portion having a curved cross section as shown in FIG. it can.

When forming the recess _RSD , when forming the sidewall insulating film, for example, the outer silicon oxide film and silicon nitride film are removed by dry etching. Thereafter, the non-recessed region is mostly made of resist, the inner silicon oxide film is removed by dry etching, and the silicon substrate is further recessed. A method of removing the silicon oxide film protected by the resist by wet etching is conceivable.

  Next, as shown in FIG. 23A, DHF treatment is performed to remove the natural oxide film on the surface of the semiconductor substrate 10. At this time, the third sidewall insulating films (32a, 32b) and the third insulating film 32c are also removed at the same time.

Next, as shown in FIG. 23 (b), immediately after the above DHF cleaning, to form recesses _{R PD} by epitaxial growth, the buried layer embedded in the recess _{R FD} and recess _{R SD} of (24h, 24i, 24j) .
The buried layer 24g is formed by a normal epitaxial growth in the concave portions R _PD , the concave portions R _FD and the concave portions R _SD , and a portion having a convex shape with respect to the semiconductor substrate 10 is formed by epitaxial growth so as to have a facet surface. Form.
The epitaxial growth described above can change the angle of the facet plane depending on conditions, and can form a plurality of plane orientations.
For example, when forming the buried layer 24g made of Si _1-x Ge _x (0 <x <1), the growth temperature is 750 ° C., the pressure is 10 Torr, the gas is SiH ₂ Cl ₂ (100 sccm), the HCL (25 sccm), It is formed as 140 sccm using GeH ₄ (50-100 sccm) and boron concentration: B ₂ H ₆ . Further, it can be formed by a low temperature process of about 400 ° C., for example.
Subsequent steps can be manufactured by substantially the same steps as in the first embodiment.
With the above, a solid-state imaging device having the configuration shown in FIG. 22 can be manufactured.

  After the above, wirings, waveguides, on-chip lenses, color filters, and the like are formed as necessary by a commonly used method.

  In the manufacturing method of the solid-state imaging device according to the present embodiment, the semiconductor layer formed by epitaxial growth that constitutes the photodiode is formed apart from the transfer gate electrode and the sidewall insulating film. Deterioration can be avoided.

Moreover, the manufacturing method of the solid-state imaging device according to the present embodiment uses a material having a band gap smaller than that of silicon as described above, and the sensitivity is greatly improved.
In addition, by forming a recess in the photodiode region, it is possible to suppress the height of the convex portion with respect to the surface of the semiconductor substrate 10 while ensuring the film thickness as the buried layer. . For this reason, since the level | step difference resulting from the unevenness | corrugation by convex shape can be suppressed, the thickness of the whole insulating film required for planarization can be suppressed, and characteristics, such as a sensitivity of a photodiode, can be implement | achieved.
By using a material having a high light absorption coefficient, the depth of the recess can be reduced. For example, when the light absorption coefficient is improved by an order of magnitude, the depth of the recess can be reduced by an order of magnitude.

In the present embodiment, recesses (recesses) are formed in the photodiode regions in all the pixels of the solid-state imaging device having blue pixels, green pixels, and red pixels, and the embedded layer is embedded. However, the present invention is not limited to this. It can be applied to photodiodes of some pixels.
In addition, the above configuration can be preferably applied to at least a pixel in a photosensitive wavelength region having a longer wavelength, where the pixel includes a plurality of pixels having different photosensitive wavelength regions. For example, in a solid-state imaging device having two types of pixels, a long wavelength side pixel and a short wavelength side pixel, it can be preferably applied to a long wavelength side pixel. Further, the present invention can be applied to both a long wavelength side pixel and a short wavelength side pixel.

  In the manufacturing method of the solid-state imaging device according to the present embodiment, the semiconductor layer formed by epitaxial growth that constitutes the photodiode is formed apart from the transfer gate electrode and the sidewall insulating film. Deterioration can be avoided.

  In addition, since the semiconductor layer formed by epitaxial growth constituting the floating diffusion is formed apart from the transfer gate electrode and the sidewall insulating film, the photoelectric conversion efficiency is lowered due to the increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode. Can be suppressed.

As shown in FIG. 22, the source / drain region of the MOS transistor formed in the logic region _ALG reaches a certain depth at the end, but is formed from a relatively shallow diffusion layer in most of the central region. Has been.
Having the source / drain of the above structure is effective in suppressing the short channel effect accompanying the miniaturization of the MOS transistor.
In addition, Si _1-x Ge _x (0 <x <1) is epitaxially grown on the MOSFET of the peripheral circuit that performs image processing to increase the drive current of the MOSFET, thereby improving the peripheral circuit characteristics and image processing. Ability can be improved. In addition, the area of the peripheral circuit can be reduced.

<Sixth Embodiment>
[Configuration of solid-state imaging device]
The plan view of the light receiving surface of the solid-state imaging device according to the present embodiment is substantially the same as the plan view of FIG. 1 according to the first embodiment.
FIG. 24 is a schematic cross-sectional view of a CMOS image sensor, which is a solid-state imaging device according to this embodiment, in which a plurality of pixels are integrated.
In the drawing, a logic region A _LG constituting a peripheral circuit of the pixel region is shown. The pixel region indicates a photodiode region A _PD , a transfer gate electrode region A _TG and a floating diffusion region A _FD .
Ge substrate 10a is used as the semiconductor substrate, the floating diffusion region A _FD and the semiconductor substrate logic region A recess is formed in the _LG epitaxial grown silicon layer 10b is formed is used.
Except for the above, it is substantially the same as the solid-state imaging device of the third embodiment. However, a Ge substrate is used for the photodiode region _APD , and the first semiconductor layer in the third embodiment is a Ge layer in the Ge substrate 10a.

  In the solid-state imaging device of the present embodiment, the semiconductor layer formed by epitaxial growth constituting the photodiode is formed away from the transfer gate electrode and the sidewall insulating film formed on the sidewall thereof, and crystal defects are generated in the semiconductor layer. It is possible to avoid deterioration of pixel characteristics due to.

The fourth semiconductor layer 24e is formed away from the transfer gate electrode 22a and the sidewall insulating films (30a, 31a) formed on the side walls thereof.
This is because, for example, the fourth semiconductor layer 24e is a layer formed by facet epitaxial growth. The second semiconductor layer 24 d has a shape in which the area of a cross section in a plane parallel to the surface of the semiconductor substrate 10 decreases as the distance from the semiconductor substrate 10 increases.

In the prior art, the silicon layer formed by epitaxial growth on the floating diffusion region is configured to be close to the transfer gate electrode through the sidewall insulating film.
Therefore, the parasitic capacitance between the silicon layer and the transfer gate electrode is increased, which causes a problem that the photoelectric conversion efficiency is lowered.

  In the present embodiment, the fourth semiconductor layer 24e on the floating diffusion is formed apart from the transfer gate electrode and the side wall insulating film formed on the side wall thereof. A decrease in photoelectric conversion efficiency caused by an increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode can be suppressed.

  Further, in the solid-state imaging device of the present embodiment, the Ge substrate is used in the photodiode region as described above. Ge has a smaller band gap than silicon and greatly improves the sensitivity to light in the red to infrared region.

The transfer gate region A _TG , the floating diffusion region A _FD , and the logic region A _LG are the same as in the third embodiment.

As described above, MOS transistors are configured, and a logic region that forms a peripheral circuit including these is formed.
In the above description, the NMOS transistor has been described. However, the present invention is not limited to this, and the present invention can be applied to a PMOS transistor.
When Si _1-x Ge _x (0 <x <1) or the like is used as the fifth semiconductor layer 24f, in the PMOS transistor, the transistor characteristics are improved by the stress applied to the channel formation region by the buried layer 24j. large. For this reason, the image processing capability in the logic circuit is improved, and the area of the logic circuit can be reduced.

[Method for Manufacturing Solid-State Imaging Device]
Next, a method for manufacturing the solid-state imaging device according to this embodiment will be described with reference to FIGS.
First, the process up to the configuration shown in FIG. 25A is performed in the same manner as the process shown in FIG. However, the Ge substrate 10a is used as the semiconductor substrate.

Next, as shown in FIG. 25B, a silicon nitride film 40 that protects the photodiode region _APD is patterned.

Next, as shown in FIG. 25 (c), a silicon nitride film is removed by etching from the surface of the Ge substrate 10a as a mask to form a recess 10t to the floating diffusion region _{A FD} and the logic region _{A LG.}

  Next, as shown in FIG. 26A, a silicon layer 10b is formed in the recess 10t by epitaxial growth.

Next, as shown in FIG. 26B, the screen insulating film 20 is removed from the upper surface, and polishing is performed by CMP (Chemical Mechanical Polishing) or the like until the element isolation insulating films (11, 12) G are exposed.
Thus, the floating diffusion region A _FD and the semiconductor substrate logic region A recess is formed in the _LG epitaxial grown silicon layer 10b is formed of a Ge substrate 10 can be formed.
Thereafter, the solid-state imaging device of the present embodiment can be manufactured using the semiconductor substrate in the same manner as in the third embodiment.

<Second Modification>
FIG. 27A to FIG. 27D are schematic views according to a second modification of the present invention.
In the third to sixth embodiments, when Si _1-x Ge _x (0 <x <1) is used as a layer having a convex shape with respect to the semiconductor substrate 10, the composition is continuously in the layer. A changing layer can be used.
For example, FIG. 27A is a schematic diagram of the second semiconductor layer 24d of the third embodiment. When the second semiconductor layer 24d is composed of Si _1-x Ge _x (0 <x <1), when the vertical axis indicates x and the horizontal axis indicates the position of the cross section at y in FIG. FIG. 27B shows a layer in which the composition changes continuously. That is, the Si concentration is high on the substrate side, and the Ge concentration increases as the distance from the substrate increases. In this case, the influence of the mismatch of the crystal lattice with respect to the silicon substrate is reduced, and crystal defects generated in the obtained SiGe layer can be suppressed. Further, the Ge concentration can be easily increased, and the light absorption coefficient can be increased.

For example, FIG. 27C is a schematic diagram of the buried layer 24g of the fourth embodiment. When the buried layer 24g is composed of Si _1-x Ge _x (0 <x <1), the vertical axis represents x, and the horizontal axis represents the position of the cross section at y in FIG. It can be set as the layer from which the composition shown by 27 (d) changes continuously. That is, the Si concentration is high on the bottom side of the recess, and the Ge concentration increases as the distance from the bottom of the recess increases. In this case, the influence of the mismatch of the crystal lattice with respect to the silicon substrate is reduced, and crystal defects generated in the obtained SiGe layer can be suppressed. Further, the Ge concentration can be easily increased, and the light absorption coefficient can be increased.

<Seventh embodiment>
[Configuration of Solid-State Imaging Device Having Optical Waveguide]
FIG. 28 is a schematic cross-sectional view of a CMOS sensor, which is a solid-state imaging device according to the present embodiment, in which a plurality of pixels are integrated, and shows a pixel region.

For example, in the pixel region serving as the light receiving surface, the n-type first semiconductor layer 111 is formed for each pixel in the p-well region 110 of the semiconductor substrate.
An n-type second semiconductor layer having a shape that protrudes on the n-type first semiconductor layer 111 with respect to the semiconductor substrate and that decreases in cross-sectional area in a plane parallel to the surface of the semiconductor substrate as the distance from the semiconductor substrate increases. 112a is formed. The n-type second semiconductor layer 112a is a layer formed by facet epitaxial growth.
A p-type third semiconductor layer 112b is formed on the surface of the n-type second semiconductor layer 112a.
As described above, the photodiode PD having the HAD structure is configured.
Further, a gate insulating film 113 and a gate electrode 114 are formed on the semiconductor substrate adjacent to the photodiode PD.
Here, the n-type second semiconductor layer 112a and the p-type third semiconductor layer 112b are formed apart from the transfer gate electrode.

  For example, a signal reading unit that reads a signal charge generated or accumulated in the photodiode PD or a voltage corresponding to the signal charge, such as a floating diffusion and a CCD charge transfer path, is formed on the semiconductor substrate. The signal charges are transferred by applying a voltage to the gate electrode 114.

  The photodiode PD is covered and an insulating film having the following configuration is laminated on the semiconductor substrate. For example, the first insulating film 115, the second insulating film 116, the third insulating film 117, the fourth insulating film 121, the fifth insulating film 122, the sixth insulating film 126, the seventh insulating film 127, and the eighth insulating film 131 are oxidized. Made of silicon. For example, the first diffusion prevention film 120 and the second diffusion prevention film 125 are made of silicon carbide. For example, the third diffusion barrier film 130 is made of silicon nitride.

A wiring groove 117t is formed in the third insulating film 117, and a first wiring layer made of a barrier metal layer 118 made of tantalum / tantalum nitride and a conductive layer 119 made of copper, for example, formed by a damascene process is embedded. It is.
Similarly, in the fifth insulating film 122, a second wiring layer including a barrier metal layer 123 and a conductive layer 124 is formed in the wiring groove 122t, and a wiring groove 127t is formed in the seventh insulating film 127. A third wiring layer composed of the layer 128 and the conductive layer 129 is formed. Said 1st-3rd diffusion prevention film is a film | membrane for preventing the spreading | diffusion of the copper which comprises a conductive layer (119,124,129).
As described above, the wiring layer is embedded in the laminated insulating film. Each of the first to third wirings may be a wiring structure formed integrally with a contact portion in an opening from the bottom surface of the wiring groove to the lower layer wiring, for example, by a dual damascene process.

Here, for example, in the upper portion of the photodiode PD, a recess H is formed with respect to the fourth to ninth insulating films and the first to third diffusion prevention films formed by stacking as described above.
As described above, the insulating film laminated on the photodiode PD is configured to include the diffusion prevention film of the wiring layer. For example, the first diffusion prevention film 120 which is the lowermost diffusion prevention film has the recess H. It constitutes the bottom.

The concave portion H has an opening diameter of about 0.8 μm and an aspect ratio of about 1 to 2 or more, for example, depending on the area of the photodiode, the pixel size, process rules, and the like.
In addition, for example, the inner wall surface of the recess H is a surface perpendicular to the main surface of the substrate, and the forward tapered opening shape 133a that spreads upward as the edge of the recess H in the portion of the ninth insulating film 133. It has become.

A passivation film 136 having a refractive index higher than that of silicon oxide (refractive index 1.45) is formed so as to cover the inner wall of the recess H. The passivation film 136 is made of, for example, silicon nitride (refractive index 2.0) and has a thickness of about 0.5 μm.
For example, it has a forward taper shape at the edge of the opening, but the profile is thick at the opening edge due to anisotropy at the time of deposition and thin near the bottom of the recess H.

Further, for example, an embedded layer 137 embedded in the recess H in the upper layer of the passivation film 136 and having a refractive index higher than that of silicon oxide is formed. The buried layer 137 fills the recess H, and the film thickness outside the recess H is about 0.5 μm.
The buried layer 137 is made of, for example, a siloxane resin (refractive index 1.7) or a high refractive index resin such as polyimide, and a siloxane resin is particularly preferable.
Further, the above resin contains metal oxide fine particles such as titanium oxide, tantalum oxide, niobium oxide, tungsten oxide, zirconium oxide, zinc oxide, indium oxide, hafnium oxide, and the refractive index is increased. .

  A planarizing resin layer 138 that also functions as an adhesive layer, for example, is formed on the buried layer 137. On the upper layer, for example, color filters (139a, 139b, 139c) of each color of blue (B), green (G), and red (R) are formed for each pixel. A microlens 140 is formed on the upper layer.

  In the solid-state imaging device according to this embodiment, the n-type semiconductor layer 112a formed by epitaxial growth constituting the photodiode is separated from the transfer gate electrode, the sidewall insulating film, and the like, and the pixel characteristics are deteriorated due to crystal defects in the semiconductor layer. Can be avoided.

  Further, the n-type semiconductor layer 112a formed by epitaxial growth constituting the floating diffusion is separated from the transfer gate electrode, the sidewall insulating film, and the like, and an increase in parasitic capacitance between the semiconductor layer and the transfer gate electrode can be suppressed.

  FIG. 28 shows a case where the present invention is applied to the first embodiment, but can be applied to the first to sixth embodiments.

<Eighth Embodiment>
FIG. 29 is a schematic configuration diagram of a camera according to the present embodiment.
A solid-state imaging device 50 in which a plurality of pixels are integrated, an optical system 51, and a signal processing circuit 53 are provided.
In the present embodiment, the solid-state imaging device 50 includes the solid-state imaging device according to any one of the first to sixth embodiments.

The optical system 51 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 50. Thereby, in the photodiode which comprises each pixel on the imaging surface of the solid-state imaging device 50, it converts into a signal charge according to incident light quantity, and the corresponding signal charge is accumulate | stored for a fixed period.
The accumulated signal charge is taken out as an output signal Vout through, for example, a CCD charge transfer path.
The signal processing circuit 53 performs various signal processing on the output signal Vout of the solid-state imaging device 50 and outputs it as a video signal.
According to the camera of the present embodiment, color shading characteristics and spectral characteristics can be improved without causing a decrease in light collection rate and sensitivity of oblique incident light, and a microlens is formed by a simple method and process. It is possible.

According to the solid-state imaging device and the manufacturing method thereof according to each of the above embodiments, the following effects can be further obtained.
1. When the photodiode region is formed of only the silicon layer, there is a problem that the sensitivity from the red region to the infrared region is not good, but this embodiment can be improved.
2. The increase in the number of pixels is demanded to increase the speed of image processing. However, there is a problem that the current drive current of the MOSFET cannot cope with the problem, but this embodiment can be improved.
3. Cost reduction by chip size reduction is required, but in order to maintain the number of pixels, there is no choice but to reduce the area of the peripheral circuit that performs image processing, and in the case of current MOSFET characteristics, the processing capability is simply reduced. The problem arises. However, it can be improved by the solid-state imaging device of the present embodiment.

The present invention is not limited to the above description.
For example, in the embodiment, the present invention can be applied to both a CMOS sensor and a CCD element.
When applied to a CCD element, a semiconductor layer is formed on the surface of a semiconductor substrate to be a photodiode region, away from a transfer gate electrode, a light shielding film, and the like, in a convex shape with respect to the semiconductor substrate. The semiconductor layer has a shape in which the area of a cross section in a plane parallel to the surface of the semiconductor substrate decreases as the distance from the semiconductor substrate increases. Thereby, it is possible to avoid deterioration of pixel characteristics due to crystal defects in the semiconductor layer.
In addition, various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11, 12 ... Element isolation insulating film, 13 ... 1st semiconductor layer, 14 ... Floating diffusion, 15 ... p ⁺ type semiconductor layer, 16 ... Extension area | region, 17 ... Source-drain area | region, 20 ... Screen insulating film 21a, 21b ... gate insulating film, 22a ... transfer gate electrode, 22b ... gate electrode, 23a, 23b ... silicon nitride film, 24a ... second semiconductor layer, 24b ... fourth semiconductor layer, 24c ... fifth semiconductor layer, 25 ... 3rd semiconductor layer, 26, 27 ... refractory metal silicide layer, 28a, 28b, 28c, 28d ... plug, 29a, 29b, 29c, 29d ... upper layer wiring, 30a, 30b ... first sidewall insulating film, 30c ... First insulating film, 31a, 31b, second sidewall insulating film, 31c, second insulating film, 32a, 32b, third sidewall , Insulating film, 32c ... third insulating film, 33 ... resist film, 34 ... first interlayer insulating film, 35 ... second interlayer insulating film, 36 ... third interlayer insulating film, 37 ... first interlayer insulating film, 38 ... 2nd interlayer insulation film, 39 ... 3rd interlayer insulation film, 40 ... 4th interlayer insulation film, 50 ... Solid-state imaging device, 51 ... Optical system, 53 ... Signal processing circuit, 110 ... p well region (semiconductor substrate), 111 ... n-type charge storage layer, 112 ... p ⁺ type surface layer, 113 ... gate insulating film, 114 ... gate electrode, 115 ... first insulating film, 116 ... second insulating film, 117 ... third insulating film, 117t ... wiring 118, barrier metal layer, 119, conductive layer, 120, first diffusion prevention film, 121, fourth insulating film, 122, fifth insulating film, 122t, wiring groove, 123, barrier metal layer, 124,. Conductive layer, 125... Second diffusion prevention film, 126. Edge film, 127... 7th insulating film, 127 t... Wiring trench, 128 .. barrier metal layer, 129... Conductive layer, 130 .. 3rd diffusion prevention film, 131 ... 8th insulating film, 133 ... 9th insulating film, 133 a ... opening shape, 134 ... resist film, 135 ... resist film, 136 ... passivation film, 137 ... buried layer, 138 ... flattened resin layer, 139a, 139b, 139c ... color filter, 140 ... microlens, _ALG ... logic, A _PD : Photodiode region, A _TG : Transfer gate electrode region, A _FD : Floating diffusion region, PD, PD1 to PD4 ... Photo diode, TG1 to TG4: Transfer gate electrode, FD, FD1, FD2 ... Floating diffusion, L ... Light, H ... recess

Claims (29)

A first conductive type first semiconductor layer formed on the semiconductor substrate and a first semiconductor layer formed on the semiconductor substrate in a photodiode region divided for each of the pixels on a light receiving surface formed by integrating a plurality of pixels of the semiconductor substrate; A first conductive type second semiconductor layer formed in a convex shape with respect to the semiconductor substrate and having a shape in which a cross-sectional area in a plane parallel to the surface of the semiconductor substrate becomes smaller from the semiconductor substrate; A photodiode having a second semiconductor layer of a second conductivity type formed on a surface of the second semiconductor layer;
A transfer gate electrode formed on the semiconductor substrate in a region adjacent to the photodiode, and a floating diffusion formed in the semiconductor substrate on the opposite side of the transfer gate electrode from the photodiode, A signal reading unit that reads a signal charge generated and accumulated in a photodiode or a voltage corresponding to the signal charge, and
The solid-state imaging device, wherein the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode. Side wall insulating films are formed on both sides of the transfer gate electrode,
The solid-state imaging device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer are formed apart from the sidewall insulating film. The solid-state imaging device according to claim 1, wherein the second semiconductor layer is a layer formed by facet epitaxial growth. A fourth first conductivity type formed on the floating diffusion so as to be convex with respect to the semiconductor substrate, and having a shape in which a cross-sectional area in a plane parallel to the surface of the semiconductor substrate decreases as the distance from the semiconductor substrate increases. A semiconductor layer is formed,
The solid-state imaging device according to claim 1, wherein the fourth semiconductor layer is formed apart from the transfer gate electrode. Side wall insulating films are formed on both sides of the transfer gate electrode,
The solid-state imaging device according to claim 4, wherein the fourth semiconductor layer is formed to be separated from the sidewall insulating film. The solid-state imaging device according to claim 4, wherein the fourth semiconductor layer is a layer formed by facet epitaxial growth. 2. The solid-state imaging device according to claim 1, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the photodiode is a photodiode having a HAD (hole accumulated diode) structure. The solid-state imaging device according to claim 1, wherein a logic region including a transistor is formed in a region different from the light receiving surface of the semiconductor substrate. The solid-state imaging device according to claim 1, wherein the second semiconductor layer in at least some of the pixels is formed of a material having a band gap smaller than that of silicon. Materials having a band gap smaller than that of silicon are Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se ₂ , Cu (In, Ga) ( The solid-state imaging device according to claim 9, wherein the solid-state imaging device is made of Se, S) ₂ or CuInS ₂ . The pixel according to claim 9, wherein the pixel includes a plurality of pixels having different photosensitive wavelength regions, and the second semiconductor layer is formed of a material having a smaller band gap than silicon in at least a pixel in the photosensitive wavelength region having a longer wavelength. Solid-state imaging device. The solid-state imaging device according to claim 1, wherein a recess is formed in the photodiode region of the semiconductor substrate, and the first semiconductor layer is embedded in the recess. The solid-state imaging device according to claim 12, wherein the first semiconductor layer and the second semiconductor layer are integrally formed. The solid-state imaging device according to claim 13, wherein the first semiconductor layer and the second semiconductor layer in at least some of the pixels are formed of a material having a band gap smaller than that of silicon. Materials having a band gap smaller than that of silicon are Ge, Si _1-x Ge _x (0 <x <1), InGaAs, GaAs, InP, InSb, Cu (In, Ga) Se ₂ , Cu (In, Ga) ( The solid-state imaging device according to claim 14, wherein the solid-state imaging device is made of Se, S) ₂ or CuInS ₂ . The pixel includes a plurality of pixels having different photosensitive wavelength regions, and in at least a pixel in the photosensitive wavelength region having a longer wavelength, the first semiconductor layer and the second semiconductor layer are formed of a material having a smaller band gap than silicon. The solid-state imaging device according to claim 14. Forming a first semiconductor layer of a first conductivity type on the semiconductor substrate in a photodiode region divided for each pixel of the light receiving surface on which a plurality of pixels of the semiconductor substrate are integrated;
Forming a floating diffusion in the semiconductor substrate spaced from the photodiode;
Forming a transfer gate electrode on the semiconductor substrate in a region between the photodiode and the floating diffusion;
A second first conductivity type having a shape that is convex on the first semiconductor layer with respect to the semiconductor substrate, and that the cross-sectional area in a plane parallel to the surface of the semiconductor substrate decreases as the distance from the semiconductor substrate increases. Forming a semiconductor layer;
Forming a second conductive type third semiconductor layer on the surface of the second semiconductor layer,
Forming a photodiode by a step of forming the first semiconductor layer, a step of forming the second semiconductor layer, and a step of forming the third semiconductor layer;
Forming a signal reading unit that reads a signal charge generated or accumulated in the photodiode or a voltage corresponding to the signal charge by forming the transfer gate electrode and forming the floating diffusion;
A method of manufacturing a solid-state imaging device, wherein the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode in the step of forming the second semiconductor layer and the step of forming the third semiconductor layer. Further comprising a step of forming sidewall insulating films on both sides of the transfer gate electrode;
18. The step of forming the second semiconductor layer and the step of forming the third semiconductor layer, wherein the second semiconductor layer and the third semiconductor layer are formed separately from the sidewall insulating film. Manufacturing method of solid-state imaging device. The method for manufacturing a solid-state imaging device according to claim 17, wherein the second semiconductor layer is formed by facet epitaxial growth in the step of forming the second semiconductor layer. The method for manufacturing a solid-state imaging device according to claim 17, wherein the third semiconductor layer is formed by in-situ epitaxial growth in the step of forming the third semiconductor layer. A fourth semiconductor layer of a first conductivity type having a shape that is convex with respect to the semiconductor substrate on the floating diffusion and has a shape in which a cross-sectional area in a plane parallel to the surface of the semiconductor substrate decreases as the distance from the semiconductor substrate increases. Further comprising the step of forming
The method of manufacturing a solid-state imaging device according to claim 17, wherein in the step of forming with the fourth semiconductor layer, the fourth semiconductor layer is formed apart from the transfer gate electrode. Further comprising a step of forming sidewall insulating films on both sides of the transfer gate electrode;
The method of manufacturing a solid-state imaging device according to claim 21, wherein in the step of forming the fourth semiconductor layer, the fourth semiconductor layer is formed apart from the sidewall insulating film. The method for manufacturing a solid-state imaging device according to claim 21, wherein the fourth semiconductor layer is formed by facet epitaxial growth in the step of forming the fourth semiconductor layer. 18. The solid-state imaging device according to claim 17, wherein the first conductivity type is an n-type, the second conductivity type is a p-type, and a photodiode having a hole accumulated diode (HAD) structure is formed as the photodiode. Method. The method for manufacturing a solid-state imaging device according to claim 17, further comprising a step of forming a logic region including a transistor in a region different from the light receiving surface of the semiconductor substrate. The method of manufacturing a solid-state imaging device according to claim 17, wherein in the step of forming the second semiconductor layer, the second semiconductor layer in at least some of the pixels is formed of a material having a band gap smaller than that of silicon. The step of forming the first semiconductor layer includes a step of forming a recess in the photodiode region of the semiconductor substrate, and a step of forming the first semiconductor layer by embedding the recess in the recess. Manufacturing method of solid-state imaging device. 28. The method of manufacturing a solid-state imaging device according to claim 27, wherein the first semiconductor layer and the second semiconductor layer are integrally formed in the step of forming the first semiconductor layer and the step of forming the second semiconductor layer. A solid-state imaging device in which a plurality of pixels are integrated on a light receiving surface;
An optical system for guiding incident light to the imaging unit of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device
A first conductive type first semiconductor layer formed on the semiconductor substrate and a first semiconductor layer formed on the semiconductor substrate in a photodiode region divided for each of the pixels on a light receiving surface formed by integrating a plurality of pixels of the semiconductor substrate; A first conductive type second semiconductor layer formed in a convex shape with respect to the semiconductor substrate and having a shape in which a cross-sectional area in a plane parallel to the surface of the semiconductor substrate becomes smaller from the semiconductor substrate; A photodiode having a second semiconductor layer of a second conductivity type formed on a surface of the second semiconductor layer;
A transfer gate electrode formed on the semiconductor substrate in a region adjacent to the photodiode, and a floating diffusion formed in the semiconductor substrate on the opposite side of the transfer gate electrode from the photodiode, A signal reading unit that reads a signal charge generated and accumulated in a photodiode or a voltage corresponding to the signal charge, and
The camera in which the second semiconductor layer and the third semiconductor layer are formed apart from the transfer gate electrode.

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