JP2011146535A - Pattern forming method for multilayer resist, method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

An object of the present invention is to solve the problems of the prior art in an intermediate layer having a high Si content.
A method for forming a pattern of a multilayer resist according to the present invention includes a step of forming an underlayer film on the surface of a processed film of the multilayer resist provided with a processed film on one surface of a substrate, and a surface of the lower layer film. The step of forming the intermediate layer, the step of heating the multilayer resist on which the intermediate layer has been formed, and the step of applying alkoxysilane, a silane coupling agent, a silylating agent, an acid generator or a base generator to the surface of the intermediate layer And a step of applying a resist on the surface of the intermediate layer, a step of patterning the resist, a step of patterning the intermediate layer, the lower layer film, and the film to be processed.
[Selection figure] None

Description

  The present invention relates to a method for forming a pattern of a multilayer resist. The present invention also relates to a semiconductor device manufacturing method including the pattern forming method and a semiconductor device manufactured by the manufacturing method.

  In lithography technology, a resist provided on a substrate is exposed through a mask, a fine pattern of resist is formed by development, and a film to be processed provided on the substrate is processed using the fine pattern of resist as a mask. Then, a desired fine pattern is formed on the film to be processed.

  In such a lithography technique, on the film to be processed for the purpose of ensuring dry etch resistance with a thin film resist and controlling the reflection of the substrate with respect to incident light in a high NA (> 1.0) region by introducing an immersion exposure technique. The usefulness of a multilayer resist process including an intermediate layer containing Si is increasing.

  In order to form a finer resist pattern with high accuracy, it is necessary to improve the dry etch resistance of the so-called intermediate layer material. This improvement in dry etch resistance increases the Si content in the intermediate layer material. It is known that it can be achieved.

  On the other hand, when the Si content in the intermediate layer material is increased, chemical interaction with the upper layer resist generally increases, causing a decrease in resist adhesion, resist shape abnormality, and resist dimension abnormality. Further, there is a problem that the stability of the intermediate layer material at room temperature deteriorates due to the improvement of the Si content, and the interaction with the resist fluctuates.

  Since the above-mentioned problem has a difference in influence depending on the type of resist, there is also a problem that usable resist types are limited.

  In Non-Patent Document 1, in order to overcome the problem of the intermediate layer having a high Si content, a thin BARC (organic film) is sandwiched between the intermediate layer and the upper layer resist as a protective film, whereby an upper layer resist on the surface of the intermediate layer is obtained. Trying to remove the impact on.

  In Patent Document 1, the surface of the intermediate layer is made hydrophobic in a processing apparatus filled with hexamethyldisilazane vapor to improve the adhesion with the upper layer resist.

JP 2005-203563 A

Makoto Nakajima, 7 others, “Design and Development of Next Generation Bottom Anti-Reflective Coatings for 45nm Process with Hyper NA Lithography”, Proceeding of SPIE, Vol.6153 (2006), p. 61532L-1

  In the method of sandwiching the thin film BARC between the intermediate layer and the upper layer resist as in the method described in the non-patent document, there are disadvantages in that the required film thickness of the resist becomes larger and the cost for forming the thin film. Further, the method disclosed in Patent Document 1 has a problem in that the compounds that can be used for the surface treatment are limited because the surface of the intermediate layer is hydrophobized by a reaction in a gas phase.

  An object of this invention is to solve the subject in an intermediate | middle layer with the above high Si content rate.

  The problem with the intermediate layer having a high Si content as described above is that, according to the study by the present inventors, the unreacted silanol group of the material forming the intermediate layer exists on the surface of the intermediate layer, the intermediate layer and the upper layer resist. It was revealed that the possibility of acid diffusion from the upper resist was high.

  The present invention has been made on the basis of the above-described knowledge, and the multilayer resist pattern forming method of the present invention has a lower layer on the surface of the processed film of the multilayer resist provided with the processed film on one surface on the substrate. A step of forming a film, a step of forming an intermediate layer on the surface of the lower layer film, a step of heating the multilayer resist formed with the intermediate layer, and an alkoxysilane, a silane coupling agent, a silylating agent on the surface of the intermediate layer A step of applying an acid generator or a base generator, a step of applying a resist to the surface of the intermediate layer, a step of patterning the resist, a step of patterning the intermediate layer, the lower layer film, and the film to be processed; It is characterized by providing.

  Since the multilayer resist pattern forming method of the present invention includes a step of applying an alkoxysilane, a silane coupling agent, a silylating agent, an acid generator or a base generator to the surface of the intermediate layer after heating, the surface of the intermediate layer To prevent chemical interaction between the surface of the intermediate layer and the upper layer resist, which is thought to be caused by the effect of the active silanol groups remaining in the layer and the diffusion of acid and base (quencher) in the upper layer resist into the intermediate layer Can do. As a result, in a multilayer resist process using an intermediate layer having a high Si content, it is possible to prevent pattern collapse, shape abnormality, and dimensional variation of the upper layer resist, and to improve the stability and accuracy of the pattern.

  In addition, according to the method for forming a multilayer resist of the present invention, it is not necessary to devise to reduce the interaction between the intermediate layer and the resist due to the composition of the upper layer resist or the intermediate layer material itself. The degree of freedom in material design is increased, and the inherent performance of the upper layer resist such as high resolution and low defects can be improved. Similarly, a cheaper material can be used on the intermediate layer side.

(A)-(c) is a schematic diagram for demonstrating a part of process included in the formation method of the multilayer resist of this invention. It is a schematic diagram for demonstrating another process included in the formation method of the multilayer resist of this invention. (A)-(d) is a schematic diagram for demonstrating an example of the process of the intermediate | middle layer surface in the formation method of the multilayer resist of this invention. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention, and is a schematic diagram of the board | substrate provided with each layer and film | membrane including the process of the intermediate | middle layer surface in this invention. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention, and is a schematic diagram which shows pattern formation of an upper resist film. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention, and is a schematic diagram which shows the pattern formation by the dry etching of an intermediate | middle layer and a lower layer film. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention, and is a schematic diagram which shows formation of a gate electrode. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention, and is a schematic diagram which shows formation of a sidewall insulating layer. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention, and is a schematic diagram which shows formation of a contact hole. It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor device of this invention, and is a schematic diagram which shows formation of an electrode. (A) And (b) is a schematic diagram for demonstrating the principal part of the pattern formation method of the multilayer resist of this invention, (a) is a case where the process of apply | coating the intermediate | middle layer surface with an acid generator is included. It is a schematic diagram, (b) is a schematic diagram in the case of including the process of apply | coating an intermediate | middle layer with a base generator.

  Hereinafter, the present invention will be described in more detail. In the following description of the embodiments, the description is made with reference to the drawings. In the drawings of the present application, the same reference numerals denote the same or corresponding parts.

<Embodiment 1>
In the first embodiment, a pattern forming method in the case where the surface of the intermediate layer is treated with alkoxysilane, a silane coupling agent, or a silylating agent will be described. In the first embodiment, the surface of the intermediate layer is treated with an alkoxysilane, a silane coupling agent, or a silylating agent, thereby capping the active silanol groups on the surface of the intermediate layer, so as to interact with the upper layer resist. Prevent action. This embodiment will be described in detail below.

(Step of forming the lower layer film)
The multilayer resist pattern forming method of the present invention includes a step of forming a lower layer film on the surface of the processed film of the multilayer resist provided with the processed film on one surface on the substrate. As the substrate, a semiconductor substrate is used. That is, the multilayer resist has a film to be processed on the main surface of the semiconductor substrate. As the film to be processed, a conventionally known film to be processed may be appropriately formed depending on a semiconductor device to be manufactured. For example, a film to be processed in which a polysilicon film, a SiO ₂ film, a Si ₃ N ₄ film or the like is laminated is illustrated can do.

  The lower layer film formed on the surface of the film to be processed is provided in order to improve the adhesion between the film to be processed and an intermediate layer described later and the formation stability of the intermediate layer. As such a lower layer film, any conventionally known film can be adopted depending on a combination with an intermediate layer or a further upper layer resist (hereinafter sometimes referred to as an upper layer resist). The process of forming the lower layer film is composed of amorphous carbon that can be formed by a vapor phase chemical growth method (CVD method), or a polymer containing an aromatic ring such as a phenyl group or a naphthyl group that can be formed by a spin coating method. The In the case of the spin coating method, for example, a product name “HM8005” manufactured by JSR is applied by spin coating, and heating is performed at 250 ° C. for 90 seconds to form a 180 nm lower layer film. The thickness and formation conditions of the lower layer film can be changed and applied by a conventionally known method depending on the material used.

(Step of forming the intermediate layer)
In the multilayer resist pattern forming method of the present invention, as shown in FIG. 1A, an intermediate layer 4a is formed on the surface of the lower layer film 3 provided on the surface of the film 2 to be processed on the substrate 1. Process. The step of forming the intermediate layer 4a can be performed by a spin coating method in the same manner as the step of forming the lower layer film. For example, a product name “NFSCOG041” manufactured by JSR is applied to the surface of the lower layer film by spin coating. A multilayer resist in which a layer is formed and a film to be processed, a lower layer film, and an intermediate layer are stacked on the substrate is manufactured.

  The material for forming the intermediate layer is not limited to the above examples, and SOG (Spin On Glass) with a high Si content (approximately 30% by mass or more in the intermediate layer material) that can be formed in a relatively thin film, Any conventionally known intermediate layer material such as an organic cross-linked hard mask material having a low Si content (about 25% by mass or less in the intermediate layer material) can be used. A material having a high Si content has good processability, but is inferior in matching with a resist and storage stability. On the other hand, a material having a low Si content can be handled in the same way as BARC (Bottom Anti Reflective Coating), and has a good matching with a resist but low etching resistance. When SOG having a high Si content is used, the effect of the pattern forming method of the present invention is remarkable. This is because when the Si content in the material constituting the intermediate layer is high, the interaction between the resist and the intermediate layer increases compared to the case where the Si content is low, and matching is inferior. This is because this interaction can be suppressed or prevented. Further, since the interaction is prevented, there is no problem such as pattern collapse even in a thin intermediate layer having a high Si content, and the pattern formation of the multilayer resist can be performed more satisfactorily.

(Process of heating the multilayer resist)
Then, the step of heating the multilayer resist on which the intermediate layer is formed is included. By this heating, the material constituting the intermediate layer formed by the spin coating method is thermally cured (FIG. 1 (b)). The intermediate layer 4a using the above exemplified material is heated at 250 ° C. for 90 seconds. Is performed to form a 110 nm thermally cured intermediate layer 4b. The heating conditions may be selected in accordance with the curing characteristics of the material constituting the intermediate layer. In general, as the heating conditions for forming such an intermediate layer, the influence on other films to be processed is taken into consideration. It is set in the range of about 180 ° C to 250 ° C. Moreover, depending on the material of the intermediate layer to be used, not only heat curing but also curing such as photocuring may be performed.

(Process of applying the intermediate layer treatment liquid to the surface of the intermediate layer)
The method for forming a multilayer resist of the present invention comprises a step of applying an intermediate layer treatment liquid such as alkoxysilane, silane coupling agent, or silylating agent to the surface of the intermediate layer formed as described above. To do. By performing such a surface treatment on the intermediate layer, silanol groups on the surface of the intermediate layer can be capped as shown in FIGS. 3 (a) to 3 (d).

  FIG. 3A to FIG. 3D are schematic views for explaining the treatment of the surface of the intermediate layer using alkoxysilane. The alkoxysilane shown in FIG. 3 (a) optionally becomes a compound having a hydroxyl group as shown in FIG. 3 (b) by hydrolysis with a solvent such as water. In this state, a hydrogen bond is formed with the hydroxyl group of the silanol group present on the surface of the intermediate layer. 3A to 3D, Y represents a functional group of alkoxysilane, and R represents an alkyl group. Thereafter, heating is optionally performed, and dehydration results in a state in which the silanol groups of the intermediate layer are capped as shown in FIG. In such a state, interaction with the upper layer resist can be prevented.

  Specifically, the low molecular surface treatment material includes, as a silane coupling agent, vinyltrichlorosilane, trimethoxyvinylsilane, 3-chloropropyltrimethoxysilane, dimethyl-3-mercaptopropylmethylsilane, 3-mercaptopropyltrisilane. Methoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyldiethoxymethylsilane, 3- (2-aminoethylaminopropyl) dimethoxymethylsilane, 3- (2-aminoethylaminopropyl) diethoxymethylsilane, 3 -Acryloxypropyldimethoxymethylsilane, 3-acryloxypropyltrimethoxysilane, 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropyltriethoxysilane, 3-aminopropyltriethoxysilane, -Methacryloxypropyldimethoxymethylsilane, 3-methacryloxypropyltrimethoxysilane, 3-ureidopropyltriethoxysilane, p-styryltrimethoxysilane, 2- (3,4-epoxycyclohexyl) ethyltrimethoxysilane, diethoxy-3 Examples of alkoxysilanes such as glycidoxypropylmethylsilane, 3- (2-aminoethylaminopropyl) triethoxysilane, and 3-phenylaminopropyltrimethoxysilane include methoxytrimethylsilane dimethoxydimethylsilane, methyltrimethoxysilane, mercapto Methyltrimethoxysilane, tetramethoxysilane, methoxydimethylvinylsilane, ethoxytrimethylsilane, diethoxymethylsilane, ethyltrimethoxysilane, ethoxydimethyl Ruvinylsilane, diethoxydimethylsilane, n-propyltrimethoxysilane, methyltriethoxysilane, tetraethoxysilane, dimethoxymethylphenylsilane, phenyltrimethoxysilane, n-propyltriethoxysilane, hexyltrimethoxysilane, phenyltriethoxysilane As silylating agents such as hexyltriethoxysilane, decyltrimethylsilane, dimethoxydiphenylsilane, diphenylethoxymethylsilane, diethoxydiphenylsilane, trimethylchlorosilane, trimethylsilyltrifluoromethanesulfonate, tert-butyldimethylchlorosilane, N′N -Bis (trimethylsilyl) urea etc. can be illustrated.

(Process for heating multilayer resist (additional process))
Since these low molecular surface treatment materials may be used alone or in combination of two or more, the function of capping the silanol group of the intermediate layer is exhibited. Played. Depending on the reactivity of the low-molecular surface treatment material, the substrate with the multilayer resist after coating may be baked (heated) using a hot plate or the like under high temperature conditions (approximately 100 ° C. to 250 ° C.). Further, the heat treatment may not be performed after the treatment of the intermediate layer surface (FIG. 2). The presence or absence of this heat treatment may be determined by the progress of the dehydration reaction shown in FIG. 3 described later, but it is desirable to perform the heat treatment in order to ensure the dehydration reaction.

  The treatment of the intermediate layer surface is, for example, by contacting the intermediate layer with a 0.5% by mass isobutyl alcohol solution of 3-glycidoxypropyltriethoxysilane as a low molecular surface treatment material, and performing the intermediate layer surface treatment. Next, the substrate to be processed is heated by a hot plate at a high temperature of 100 ° C. The contact treatment can be performed by applying the solution by spin coating or spraying.

  When a silylating agent and alkoxysilane are used to treat the surface of the intermediate layer, these materials increase the reactivity, that is, in order to convert the alkoxy group into a hydroxyl group, water (hydroxyl group) is used as a solvent. It is desirable to use those containing. That is, it is preferable to use various water or organic solvents such as water, ethers, alcohols and the like depending on the reactivity of the low molecular surface treatment material or the affinity with the solvent (reaction mechanism: FIG. ) To FIG. 3 (d)). A silane coupling agent may also be used after the viscosity is reduced by adding a solvent in order to improve the application by spin coating.

  The solution concentration of the low-molecular surface treatment material to be surface-treated is not particularly limited, and it is preferable to adjust the concentration so as to be sufficient for capping silanol groups present on the surface of the intermediate layer. According to the study by the inventors, such an effect can be performed efficiently and economically satisfactorily by using a solution of up to about 0.5% by mass of the material regardless of the solvent. it can.

(Process for forming resist film, patterning process)
Subsequently, a step of forming a resist film (upper layer resist film) on the surface of the surface-treated intermediate layer and a step of patterning the formed resist film are performed, and then the intermediate layer, the lower layer film, and the film to be processed are patterned. Pattern transfer is performed by the process of performing. Film formation and pattern formation of these resists can be performed by a conventionally known multilayer resist process as described later.

  As the material constituting the upper resist film, any material having photosensitivity and conventionally used for forming on the BARC (antireflection film) or the intermediate layer can be used. That is, ArF light chemically amplified positive resist, PAR-855 (manufactured by Sumitomo Chemical Co., Ltd.) and the like are exemplified. A so-called top coat may be provided on the upper resist film.

  The upper layer resist can be formed by spin coating. After the material is applied by spin coating, the upper resist film is formed by heating.

  The pattern is formed by patterning by exposure processing and development processing, and pattern transfer to a film to be processed by dry etching processing.

  A desired pattern is exposed to the formed upper resist film using, for example, an ArF excimer laser and a mask. After the exposure, a developing solution is supplied to the upper resist film and allowed to stand for several tens of seconds for development. Pure water is supplied to remove the developer and the like, and a pattern is formed on the upper resist film.

  The intermediate layer, the lower layer film, and the film to be processed are sequentially dry-etched using the upper layer resist film on which a desired pattern is formed as a mask, whereby the pattern formed on the upper layer resist film is transferred to the film to be processed.

<Embodiment 2>
The pattern formation method including the surface treatment of the intermediate layer in the present invention and the semiconductor device manufacturing method using the multilayer resist process will be described with reference to FIGS. In the following description, a method for manufacturing an n-channel MOS (Metal Oxide Semiconductor) transistor portion included in a semiconductor device will be described.

A well is formed by introducing predetermined impurities into the main surface of substrate 1 (for example, a p-type silicon substrate), and an element isolation structure is formed so as to define an element formation region. When STI (Shallow Trench Isolation) is adopted as the element isolation structure, a trench is formed by etching the main surface of the substrate, and an insulating film such as a silicon oxide film is embedded in the trench. Further, boron is ion-implanted into the formation region of the MOS transistor with an implantation energy of, for example, 30 to 60 keV and a doping amount of 2 × 10 ¹² cm ⁻² or less for adjusting the threshold voltage of the MOS transistor.

  Next, as shown in FIG. 4, the insulating film 7 is formed on the main surface of the substrate 1 by using a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, or the like. Examples of the insulating film include a high dielectric thin film silicon oxide film, an HfO (hafnium oxide) -based insulating film, an HfN (hafnium nitride) -based insulating film, an HfON (hafnium oxynitride) -based insulating film, Examples thereof include a zirconium-based insulating film. Thereafter, a conductive film 8 made of a low-resistance conductive material such as doped polysilicon, tungsten, nickel, nickel silicide, titanium nitride, or tantalum silicon nitride is formed on the insulating film 7 by sputtering or CVD. Etc. are used for film formation.

  Next, as shown in FIG. 5, after forming the lower resist film 9 and the intermediate layer 10 on the conductive film 8, the surface of the intermediate layer is treated with the low molecular surface treatment material by the above-described method in the present invention. . Further, an upper resist film 12 is applied thereon, and a desired pattern provided on the photomask is transferred to the upper resist film by the exposure and development processes described above (FIG. 6) to form an upper resist film pattern 12a.

Using the upper resist film pattern 12a as a mask, as shown in FIG. 7, the intermediate layer 10 is dry-etched with an alkyl fluoride gas such as CF ₄ , C ₄ F ₈ , CHF ₃ . Thereby, the intermediate layer pattern 10a is formed. Thereafter, the gas is switched to H ₂ / N ₂ system or O ₂ / N ₂ system in the same etching chamber, and the lower resist film (lower film 9) of the three-layer resist is dry developed to form a lower resist film pattern (lower film) Pattern 9a) is formed.

  The conductive film 8 is dry-etched using each pattern obtained as described above as an etching mask to form a gate electrode 8a as shown in FIG. Then, the excess lower layer resist film pattern 9a and the like are peeled off.

Next, as shown in FIG. 9, a predetermined n-type impurity is implanted into the substrate 1 in a self-aligned manner with respect to the gate electrode 8a using the gate electrode 8a as a mask. For example, arsenic (As) is ion-implanted with an implantation energy of 20 to 50 keV and a doping amount of 1 × 10 ¹⁴ cm ⁻² or more and 5 × 10 ¹⁴ cm ⁻² or less. Thereby, the n-type low concentration impurity region 13a can be formed.

  Thereafter, an insulating film such as a silicon oxide film is formed by CVD or the like so as to cover the gate electrode 8a, and anisotropic etching is performed on the insulating film. Thereby, a sidewall insulating film 14 is formed on the sidewall of the gate electrode 8a. At this time, the insulating film 7 is also etched to form a gate insulating film 7a.

Using the sidewall insulating film 14 and the gate electrode 8a as a mask, a predetermined n-type impurity is implanted into the substrate 1 in a self-aligned manner with respect to the sidewall insulating film 14 and the gate electrode 8a. For example, arsenic (As) is ion-implanted with an implantation energy of 30 to 50 keV and a doping amount of 1 × 10 ¹⁵ cm ⁻² or more and 5 × 10 ¹⁵ cm ⁻² or less. Thereby, n-type high concentration impurity region 13b can be formed.

  Next, as shown in FIG. 10, a silicon oxide-based interlayer insulating film 15 is formed by CVD or the like so as to cover the sidewall insulating film 14 and the gate electrode 8a. A second lower layer film 9b and a second intermediate layer 10b are formed on the interlayer insulating film 15 in the same manner as described above, and the surface of the intermediate layer 10b is processed using the above-described low molecular surface treatment material. The contact hole 18 can be formed by applying the second upper resist film 17 on the surface and then performing exposure, development, and dry etching treatment.

  A conductive film is formed in the contact hole 18 using a CVD method, a sputtering method, or the like. Examples of the conductive film include a polysilicon film doped with impurities, a refractory metal film such as a tungsten (W) film, a titanium nitride (TiN) film, and a copper (Cu) film. By patterning this conductive film, an electrode 19 can be formed as shown in FIG. The exposure method described above can also be used during this patterning.

  When manufacturing a device having a multilayer wiring structure, an interlayer insulating film is formed so as to cover the conductive film (electrode 19) in the state shown in FIG. 11, a through hole is formed in the interlayer insulating film, and the through-hole is formed. A conductive film such as a copper (Cu) film may be embedded in the hole. Thereby, a semiconductor device such as a CMOS (Complementary Metal-Oxide Semiconductor) device having a multilayer wiring structure can be manufactured.

  In the above-described embodiment, an example in which the multilayer resist process in which the intermediate layer surface is processed in the present invention is used for forming the gate electrode 8a and the contact hole 18 is shown. Even in a semiconductor device manufacturing process including a fine pattern forming process such as a forming process, a metal wiring forming process, and a via hole forming process, the method for treating an intermediate layer surface in the present invention can be used.

  The manufacturing method of the present invention can be applied to semiconductor devices in general and can form a fine pattern, and thus is particularly suitable for devices of 45 nm node and beyond.

<Embodiment 3>
In this Embodiment 3, since it is the same as that of Embodiment 1 except performing the surface treatment of an intermediate | middle layer using an acid generator or a base generator instead of a low molecular surface treating agent, about the overlapping part Will not repeat that explanation. In addition, the semiconductor manufacturing apparatus including the intermediate layer surface processing method according to the third embodiment can be manufactured in the same manner as in the second embodiment.

  In Embodiment 3 of the present invention, the pH of the intermediate layer surface is controlled or adjusted by treating the intermediate layer surface with an acid generator or a base generator, so that the upper resist film enters the intermediate layer. Since diffusion of acid and base can be prevented, abnormal shape of the upper resist and insufficient adhesion can be prevented.

  As the acid generator or the base generator, a photo-induced acid generator or a photo-induced base generator, a heat-induced acid generator or a heat-induced base generator can be used.

  Photo-induced acid generators and heat-induced acid generators include onium salt photoacid generators, halogen-containing compound photoacid generators, diazoketone compound photoacid generators, and sulfonic acid compound photoacid generators. And sulfonate compound-based photoacid generators.

  Examples of the photo-induced base generator and the heat-induced base generator include carbamate derivatives such as 1-methyl-1- (4-biphenylyl) ethyl carbamate and 1,1-dimethyl-2-cyanoethyl carbamate, urea and N, N- Examples include urea derivatives such as dimethyl-N′-methylurea, dihydropyridine derivatives such as 1,4-dihydronicotinamide, quaternized ammonium salts of organic silane and organic borane, dicyandiamide, and the like. In addition, guanidine trichloroacetate, methylguanidine trichloroacetate, potassium trichloroacetate, guanidine phenylsulfonylacetate, guanidine p-chlorophenylsulfonylacetate, guanidine p-methanesulfonylphenylsulfonylacetate, potassium phenylpropiolate, guanidine phenylpropiolate, phenylpropiolic acid Examples include cesium, guanidine p-chlorophenylpropiolate, guanidine p-phenylene-bis-phenylpropiolate, tetramethylammonium phenylsulfonylacetate, and tetramethylammonium phenylpropiolate.

  The above acid generator and base generator may be used alone or in combination of two or more of the same kind of generator. These acid generators or base generators are usually used in the form of a solution dissolved in a solvent, and depending on the concentration of the acid or base to be generated, it is desirable to use as a solution of about 10 to 300 ppm. As the solvent, a conventionally known solvent that dissolves each of the above acid generators or base generators may be used. Specifically, ethyl lactate, ethyl pyruvate, n-amyl acetate, n-butyl acetate, propylene glycol monomethyl ether acetate, γ-butyrolactone, cyclohexanone and the like that are generally used in resists can be exemplified. . These acid generators or base generators can be applied to the intermediate layer surface by spin coating or spraying.

  The acid generator or base generator may be appropriately selected depending on the material constituting the upper resist film to be used. If the cross-sectional shape of the upper resist is a trailing shape and the resolution in a narrow space is reduced, the acid generator or base generator may be selected. When the generator is used, the resist shape is improved (see FIG. 12A). In addition, if the cross-sectional shape of the upper layer resist is inversely tapered, and there is a problem with the adhesion of the resist pattern such as peeling or falling of the resist pattern with a small contact area, the resist shape can be improved by using a base generator. (See FIG. 12B).

  In the same manner as in the first embodiment, it is possible to carry out a multilayer resist pattern formation and a semiconductor device manufacturing method including the pattern formation, including the treatment of the intermediate layer surface. The manufacturing method can be applied to all semiconductor devices as in the first embodiment, and can form a fine pattern, and thus is particularly suitable for a device of 45 nm node or later.

  As described above, the embodiments of the present invention have been described, but it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The method for forming a pattern of a multilayer resist according to the present invention is not limited to a semiconductor device, and is a field in which a fine pattern is required, and a step of forming a pattern by sensitizing a resist provided with an intermediate layer as in the present invention. It can be applied when

  1 substrate, 3 silicon oxide film, 5 polysilicon film, 6 upper layer film, 7 insulating film, 7a gate insulating film, 8 conductive film, 8a gate electrode, 9, 9b lower layer film, 9a lower layer film pattern, 10, 10b intermediate layer 10a Intermediate layer pattern, 12, 17 Upper resist film, 12a Upper resist film pattern, 13a Low concentration impurity region, 13b High concentration impurity region, 14 Side wall insulating film, 15 Interlayer insulating film, 18 Contact hole, 19 Electrode.

Claims (6)

Forming a lower layer film on the surface of the processed film of the multilayer resist provided with the processed film on one surface on the substrate;
Forming an intermediate layer on the surface of the lower layer film;
Heating the multilayer resist formed with the intermediate layer;
Applying an alkoxysilane, a silane coupling agent, a silylating agent, an acid generator or a base generator to the surface of the intermediate layer;
Forming a resist film on the surface of the intermediate layer;
Patterning the resist film;
A method for forming a pattern of a multilayer resist, comprising a step of patterning the intermediate layer, the lower layer film, and the film to be processed.   The multilayer resist pattern forming method according to claim 1, wherein the applying step is performed using a solution containing alkoxysilane and a silylating agent.   The multilayer resist pattern forming method according to claim 1, further comprising a step of heating the multilayer resist after the applying step.   The multilayer resist pattern forming method according to claim 2, wherein the solution includes at least one of water, ether, and alcohol.   A method for manufacturing a semiconductor device, comprising the multilayer resist pattern forming method according to claim 1.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 5.

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