JP2011139067A - 半導体デバイスの製造方法および半導体デバイス - Google Patents
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Abstract
【解決手段】III−V族材料の伝導層2を成長させる工程と、伝導層2の上に、伝導層2の第1部分が露出するようにマスクを形成する工程と、伝導層2の第1露出部分を部分的に分解してする工程とを含む。好適には、分解を伴う1つの工程で再堆積が起こり、複数の成長結晶3の結晶ファセット31に基づきテクスチュア表面を得る。結果のデバイスは、好適には、発光素子を含む。この伝導層は、上側に存在するのが好ましい。
【選択図】図2
Description
III−V族材料の伝導層を成長する工程と、
成長層の上に、伝導層の第1部分を露出させたマスクを形成する工程と、
伝導層の第1露出部分を部分的に分解し、粗面化した表面を得る工程と、を含む。
表面プラズモン構造としてテクスチュア層を用いて、第1主表面の方向に向かって、ナノ構造の上に電磁放射を向ける工程と、
ナノ構造を通って分子の位置を変える工程と、
第2主面から離れるようにナノ構造から生じる電磁放射を検出する工程であって、ナノ構造を通る電磁放射の伝導は、少なくともナノ構造中の表面プラズモンポラリトンの励起による工程と、を含む方法であると説明される。
Claims (18)
- 1またはそれ以上のIII−V族材料のヘテロ層スタックを含み、層スタックの少なくとも1つの伝導層が、光伝導を増加するために、粗面化された表面またはテクスチュア表面を有する半導体デバイスの製造方法であって、
III−V族材料の伝導層を成長させる工程と、
伝導層の上に、伝導層の第1部分が露出するようにマスク層を形成する工程と、
伝導層の第1露出部分を部分的に分解して、粗面化された表面を得る工程と、を含む方法。 - 部分的な分解の結果のIII−V族材料の再堆積が行われて、テクスチュア表面を形成する結晶ファセットを形成する請求項1に記載の方法。
- 再堆積が、伝導層の第1露出部分の分解を有する1つの工程中に起きる請求項2に記載の方法。
- 分解と再堆積が、窒素を含む雰囲気中で行われる請求項2または3に記載の方法。
- 雰囲気が、アンモニア(NH3)を含む請求項4に記載の方法。
- 雰囲気が、更に水素(H2)を含む請求項4または5に記載の方法。
- III−V族材料が、大気圧中で1250℃より低い分解温度を有する請求項1〜6のいずれかに記載の方法。
- III−V族材料が、GaN、InGaN、AlxGa1−xN(x≦0.3)、AlxInyGa1−x−yN(x≦0.3、y≦1)、InNのグループから選択される請求項7に記載の方法。
- 伝導層が、伝導層を分解した場合に無傷で残るストップ層の上に形成される請求項1に記載の方法。
- ストップ層は、伝導層の材料とは異なり、かつこれより高い分解温度を有する材料を含む請求項9に記載の方法。
- 少なくともマスクの一部が、少なくとも1つの金属コンタクトで置き換えられる請求項1に記載の方法。
- 1またはそれ以上のIII−V族材料のヘテロ層スタックを含み、層スタックの少なくとも1つの伝導層は光伝導を増加させるために、粗面化された表面またはテクスチュア表面を有する半導体デバイスであって、
表面は、伝導層の第1露出部分に成長させた複数の結晶の結晶ファセットにより形成されるテクスチュア表面であり、複数の結晶は0.01.106〜1000.106/mm2の範囲内にある半導体デバイス。 - 伝導層が、伝導層の材料とは異なる材料を含むストップ層の上に存在する請求項12に期し阿の半導体デバイス。
- 伝導層の第2部分が、実質的に平坦な表面を有し、かつ金属コンタクトで覆われる請求項12または13に記載の半導体デバイス。
- III−V族材料が、大気圧中で1250℃より低い分解温度を有し、かつ好適には、GaN、InGaN、AlxGa1−xN(x≦0.3)、AlxInyGa1−x−yN(x≦0.3、y≦1)、InNのグループから選択される請求項12〜14のいずれかに記載の半導体デバイス。
- 層のスタックが、順序通りでn型ドープ層、量子井戸構造、およびp型ドープ層を有する発光層を含み、伝導層が、p型ドープ層を構成し、またはp型ドープ層の上に存在する請求項12〜15のいずれかに記載の半導体デバイス。
- 更に、反射光学素子を含み、発光層スタックが、反射光学素子と伝導層のテクスチュア表面との間に存在する請求項16に記載の半導体デバイス。
- 更に、層スタックの中にナノ構造を含み、少なくとも1つの表面プラズモン構造として働くテクスチュア表面の手段により、放射がナノ構造に導かれる請求項14に記載の半導体デバイス。
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EP09180938.4A EP2341558B1 (en) | 2009-12-30 | 2009-12-30 | Method of manufacturing a semiconductor device |
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Also Published As
Publication number | Publication date |
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EP2341558B1 (en) | 2019-04-24 |
JP5635394B2 (ja) | 2014-12-03 |
EP2341558A1 (en) | 2011-07-06 |
US20110156000A1 (en) | 2011-06-30 |
US10461220B2 (en) | 2019-10-29 |
US20150179883A1 (en) | 2015-06-25 |
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