JP2011134218A - Design device, design method and program of semiconductor integrated circuit using reconfigurable memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a small-area and high-performance semiconductor integrated circuit by utilizing a reconfigurable memory where storage capacity and port position are variable. <P>SOLUTION: The design device 100 of the semiconductor integrated circuit includes: an input part 101 which inputs information about a set of sharable memory blocks, which is configured of information about a net list comprising logic modules and memory blocks and information about memory blocks for exclusive use; a floor planning part 102 which determines arrangement positions of logic modules and memory blocks on the basis of the information about the net list; a memory sharing index setting part 103; a shared memory selection part 104; a delay and wiring property evaluation and determination part 106; a non-shared memory selection part 107; a net list updating part 105; and an output part 108 which outputs the net list updated by the net list updating part 105 and a floor planning result, as a design result. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design apparatus, a semiconductor integrated circuit design method, and a computer program for designing a semiconductor integrated circuit, and in particular, using a reconfigurable memory having a variable storage capacity and port position, and a small area. The present invention also relates to a design apparatus, a design method, and a computer program for realizing a high-performance semiconductor integrated circuit.

  The components of the semiconductor integrated circuit are roughly classified into a memory block that stores a logical value and a logic module that performs a logical operation.

  A plurality of memory blocks and logic modules are mounted on one semiconductor integrated circuit, and a connection for performing data transfer between the memory block and the logic module is added on the semiconductor integrated circuit, so that a desired A logic circuit that performs the functions is realized.

  The connection also exists between the logic modules in order to transfer data between the logic modules. Each connection is called a net, and a set of nets is called a netlist. Hereinafter, the term netlist may include a logical module and a memory block itself in addition to a connection set.

  As typical memory blocks mounted on a semiconductor integrated circuit, there are a static random access memory (SRAM) and a dynamic random access memory (DRAM). Memory blocks mounted on a semiconductor integrated circuit have various storage capacities, and each logic module configures an integrated circuit using a memory block having a necessary capacity.

  FIG. 13 shows an example of a net list of a semiconductor integrated circuit. Here, eight logic modules logic1 to logic8 are included in the netlist, and each logic module is connected to each of the memories mem1 to mem8. There are also nets that connect the logic modules, but are omitted here for the sake of simplicity.

  FIG. 14 shows an example in which the net list of FIG. 13 is arranged. Existing techniques for arranging such memory blocks and logic modules are described in Patent Document 1, Patent Document 2, Patent Document 3, and the like.

  In recent years, there has been proposed a memory capable of changing the storage capacity and the port position by changing the connection inside the memory. For example, Non-Patent Document 1 proposes such a memory configuration technique. A memory capable of changing the storage capacity and the port position is referred to as a reconfigurable memory.

  FIG. 11 shows an example of a reconfigurable memory. In the reconfigurable memory CMEM, embedded memory elements MA to ML to which memory blocks are allocated and memory ports P1 to P12 for connecting to the logic modules are regularly arranged.

  Reconfigurable memory CMEM configures a network between memory elements by switching the connection of network switches N1 to N12, and combines a plurality of memory elements to realize memory blocks with a desired storage capacity in various configurations Is possible.

  FIG. 12 shows an example of realizing a memory block on a reconfigurable memory. Each of the memory elements MA to ML has a storage capacity of 2 KWords and 32 bits.

  In FIG. 12A, 12 memory elements MA to ML are connected by a network to constitute a 24 KWord, 32 bit memory block A1.

  In FIG. 12B, the memory block B1 is configured by connecting six memory elements MA to MF via a network, and the memory block B2 is configured by connecting six memory elements MG to ML via a network. is doing. The storage capacity is 12 KWord and 32 Bit for both the memory block B1 and the memory block B2.

  The memory port is used by each memory block one by one. That is, FIG. 12A uses one memory port, and FIG. 12B uses two memory ports.

  As the memory port used by each memory block, one of the memory port groups arranged in the area to which the memory block is allocated may be arbitrarily selected. For example, in FIG. 12A, the memory port P1 is used, but one of the other 11 memory ports P2 to P12 shown in FIG. 11 in the memory block area may be selected and used. . In FIG. 12B, the memory block B1 uses the memory port P5, and the memory block B2 uses the memory port P8.

  Here, in a semiconductor integrated circuit, when there is a set of memory blocks that are not used at the same time, that is, when a logic module that uses each memory block operates exclusively, these memory blocks can be reconfigured. By sharing using a memory, the area of the semiconductor integrated circuit can be reduced.

  For example, if all the memory blocks included in the circuit of FIG. 13 are not used at the same time, as shown in FIG. 15, a reconfigurable memory is used to share one memory block between logical modules. As a result, the area of the semiconductor integrated circuit can be reduced.

  As described above, since the reconfigurable memory can realize memory blocks having various storage capacities, even when the storage capacities of the memory blocks required by the respective logic modules are different, such memory blocks can be shared. Is possible.

JP 2008-129725 A JP 2006-323643 A JP 2005-149273 A

H. Saito, et al. “A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors,” International Solid State Circuits Conference, 2009

  However, the above technique has room for improvement in the following points.

  As a first problem, by sharing the memory block, the connection is concentrated on one memory block, and the wiring property of the semiconductor integrated circuit may be deteriorated. In FIG. 15, eight connections are concentrated in the reconfigurable memory arranged in the center. Concentration of wiring in one place leads to deterioration of wiring performance, and further, deterioration of wiring performance leads to deterioration of wiring delay due to wiring detouring, which is a serious problem.

  The second problem is that the distance between the arranged memory block and the logic module is increased, and the delay between the memory block and the logic module is deteriorated. In FIG. 15, since logic 6 is arranged away from the memory block, there may be a delay problem in the connection between logic 6 and the memory block. This is a problem that occurs when it is impossible to arrange all the logical modules in the vicinity of one memory block when many logical modules share one memory block. In order to solve this problem, for example, as shown in FIG. 16, it is necessary to appropriately share and unshare memory blocks and arrange them.

  In FIG. 16, a set of logic1, logic6, and logic2, a set of logic3 and logic4, and a set of logic5 and logic7 share memory blocks using reconfigurable memories 1 to 4, respectively.

  In the case of FIG. 16, the area is larger than when all the memory blocks are assigned to one reconfigurable memory (FIG. 15), but this sharing method is better from the viewpoint of wiring property and delay. There may be. Further, compared to the case of not sharing memory at all in FIG. 14, the amount of memory blocks used is reduced, leading to a reduction in the overall area.

  As described above, it is necessary to appropriately share the memory block so that the wiring property is good and the delay is small in consideration of the arrangement of the memory block and the logic module. However, until now, no technique has been proposed for performing such a design.

(Object of invention)
The present invention has been made in view of the above circumstances, and an object thereof is to realize a small area and high performance semiconductor integrated circuit using a reconfigurable memory having variable storage capacity and port position. The present invention provides a design apparatus, a design method, and a computer program.

  A first semiconductor integrated circuit design apparatus according to the present invention is a set of sharable memory blocks composed of information relating to a netlist composed of logic modules and memory blocks, and information relating to memory blocks used exclusively. Input means for inputting information about, floor planning means for determining the placement positions of logical modules and memory blocks based on information about the netlist, memory sharing index setting means for setting a memory block sharing index, floor Based on the floor planning result determined by the planning means and the memory block sharing index, the shared memory selection means for selecting a memory block to be shared as a shared memory set, and the wiring property and delay of the floor planning result are evaluated. Wiring and delay evaluation / judgment means, and Non-shared memory selection means for selecting a memory block to be shared as a non-shared memory set from the planning result and the wiring property and delay evaluation result, and the selected shared memory set or non-shared memory set Netlist updating means for updating the netlist based on the above information, netlist updated by the netlist updating means, and output means for outputting the floor planning result as a design result.

A first method for designing a semiconductor integrated circuit according to the present invention is a set of sharable memory blocks composed of information relating to a netlist composed of logic modules and memory blocks, and information relating to memory blocks used exclusively. An input step for inputting information on the floor, a floor planning step for determining the placement positions of the logic modules and memory blocks based on the information on the netlist, a memory sharing index setting step for setting a memory block sharing index, and a floor Based on the floor planning result determined in the planning step and the memory block sharing index, the shared memory selection step for selecting the memory block to be shared as a shared memory set, and the wiring property and delay of the floor planning result are evaluated. Routability and delay A non-shared memory selection step for selecting a memory block to be unshared as a non-shared memory set from the price / judgment step, the floor planning result, the wiring property and the delay evaluation result, and the selected shared memory set Alternatively, the method includes a net list update step for updating the net list based on information of the unshared memory set, a net list updated by the net list update step, and an output step for outputting the floor planning result as a design result.

  A first program according to the present invention includes a computer, which is a semiconductor integrated circuit design apparatus, that includes information relating to a netlist composed of logic modules and memory blocks, and information relating to memory blocks used exclusively. Input processing that inputs information about a set of possible memory blocks, floor planning processing that determines the placement positions of logical modules and memory blocks based on information about the netlist, and memory sharing that sets a memory block sharing index Based on the index setting process, the floor planning result determined in the floor planning process, and the memory block sharing index, the shared memory selection process for selecting the memory block to be shared as a shared memory set, and the wiring of the floor planning result Wiring to evaluate safety and delay And non-shared memory selection processing for selecting a non-shared memory block as a non-shared memory set from the delay evaluation / determination processing, the floor planning result, the wiring property and the delay evaluation result, and the selected sharing A netlist update process for updating a netlist based on information on a memory set or a non-shared memory set, a netlist updated by the netlist update process, and an output process for outputting a floor planning result as a design result. Let it run.

  According to the present invention, in the design of a semiconductor integrated circuit using a reconfigurable memory having a variable storage capacity and port position, considering the arrangement of the memory block and the logic module, the wiring property is good and the delay is small. Thus, it becomes possible to share memory blocks. This makes it possible to design a semiconductor integrated circuit having a small area and high performance.

It is a functional block diagram which shows the structure of the design apparatus of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a flowchart which shows an example of the process sequence of the design method of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a figure which shows an example of the initial floor planning which does not share a memory block. It is a figure which shows an example of the shared memory selection result based on the memory sharing parameter | index with loose distance restrictions. FIG. 5 is a diagram illustrating an example of a result of floor planning after a memory block is shared based on the memory sharing information of FIG. 4 and a netlist is updated. It is a figure which shows an example of the result of having selected the logic module connected to the memory which evaluates wiring property and a delay, and is not shared. It is a figure which shows an example of the result of having made a memory block unshared and updating a net list based on the unshared memory information of FIG. FIG. 8 is a diagram illustrating an example of floor planning for the netlist after memory non-sharing in FIG. 7 and a shared memory selection result based on a floor planning result and a memory sharing index with severe distance constraints. FIG. 9 is a diagram illustrating an example of a result of sharing a memory and updating a netlist based on the memory sharing information of FIG. 8. It is a figure which shows an example of the result of having performed floor planning with respect to the updated net list of FIG. It is a figure which shows the example of a reconfigurable memory. It is a figure which shows the example which implement | achieves one 24KWord, 32-bit memory block in a reconfigurable memory, and the example which implement | achieves two 12KWord, 32-bit memory blocks. It is a figure which shows an example of the net list which consists of a logic module and a memory block. It is a figure which shows an example of the floor planning result by the background art with respect to FIG. It is a figure which shows an example of the result of having performed the floor plan by sharing all the memory blocks of FIG. FIG. 14 is a diagram illustrating an example of a result of performing a floor plan by partially sharing the memory block set of FIG. 13.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a functional block diagram showing a configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention.

  The semiconductor integrated circuit design apparatus 100 according to the present embodiment has an input unit 101 for inputting information on a netlist composed of logic modules and memory blocks, and memory blocks used exclusively, that is, a sharable memory block set. And a floor planning unit 102 for determining the arrangement position of the logical module and the memory block based on netlist information composed of the logical module and the memory block, a memory sharing index setting unit 103 for setting a memory sharing index, A shared memory selection unit 104 that selects a memory to be shared based on a floor planning result and a memory sharing index, a wiring property and delay evaluation unit 106 that evaluates wiring property and delay of the floor planning result, a floor planning result and wiring Non-sharing from sex and lazy evaluation results A non-shared memory selection unit 107 that selects a memory to be selected, a net list update unit 105 that updates a net list based on information of the selected shared memory set or non-shared memory set, an updated net list, and And an output unit 108 that outputs a floor planning result as a design result.

  The semiconductor integrated circuit design device 100 of the present embodiment can be configured by a general computer including a control device, a storage device, an input device, and a display device. These parts are not shown. Each unit is constructed and controlled on a storage device such as a ROM (Read Only Memory) and a RAM (Random Access Memory) by a control device that operates according to a computer program stored in the storage device. In the following drawings, the configuration of parts not related to the essence of the present invention is omitted and is not shown.

  That is, each component of the semiconductor integrated circuit design device 100 includes a CPU (Central Processing Unit) of an arbitrary computer, a memory, a program that realizes the components of this figure loaded in the memory, and a hard disk that stores the program. It is realized by any combination of hardware and software, centering on the storage unit and network connection interface. It will be understood by those skilled in the art that there are various modifications to the implementation method and apparatus. Each drawing described below shows a functional unit block, not a hardware unit configuration.

  The input unit 101 receives and stores information relating to a netlist composed of logic modules and memory blocks, and memory blocks used exclusively, that is, a sharable memory block set. The input unit 101 may receive and input data from various recording media or storage devices or other devices via a network or the like via an input / output interface (not shown) of the semiconductor integrated circuit design device 100, for example. Alternatively, data input by the user may be accepted. The input information does not necessarily have to be received and updated every time, and information stored in a storage unit or the like of the computer can be used.

  The floor planning unit 102 determines an arrangement position of the logic module and the memory block based on net list information including the logic module and the memory block. The floor planning unit 102 can use an existing floor planning technique, and is not related to the essence of the present invention, and thus detailed description thereof is omitted.

  The memory sharing index setting unit 103 sets a memory block sharing index. For example, the distance between memory blocks in the floor planning result can be used as an index. That is, it is considered that a set of sharable blocks arranged within a distance equal to or smaller than a certain threshold is set as a sharing target, and this threshold is set.

  The shared memory selection unit 104 selects a memory block to be shared based on the floor planning result and the memory sharing index. For example, when using the distance between memory blocks as an index in the floor planning result, a set of sharable blocks arranged within a distance equal to or less than the threshold set by the memory sharing index setting unit 103 is set as a sharing target. select.

  The wiring property and delay evaluation / determination unit 106 evaluates the wiring property and delay of the floor planning result, and determines whether the wiring property and delay satisfy the design constraints.

  For this wiring property and delay evaluation, it is possible to use a conventionally proposed technique such as using a schematic wiring, and the detailed description is omitted because it is not related to the essence of the present invention.

  The unshared memory selection unit 107 selects a memory to be unshared from the floor planning result, the wiring property, and the delay evaluation result. Here, select a logical module that has caused a wiring constraint violation or delay constraint violation with the shared memory block, and select the memory used by the corresponding logical module as a memory block to be separated from the shared memory. .

  The netlist update unit 105 updates the netlist based on information on the selected shared memory set or non-shared memory set. When sharing a memory block, the netlist is updated by merging the target memory block in the netlist into one memory block. When the memory block is unshared, the net list is updated by separating the target memory block in the net list from the shared memory block.

  The output unit 108 outputs the updated netlist and its floor planning result as a design result.

  In the semiconductor integrated circuit design device 100 according to the present embodiment, the CPU can realize each function of each unit by reading out a program stored in the hard disk into the memory and executing it.

  The computer program according to the present embodiment includes a netlist composed of logic modules and memory blocks and a memory block used exclusively by the computer for realizing the semiconductor integrated circuit design device 100, that is, a sharable memory block. A procedure for inputting information related to the set, a procedure for determining the arrangement position of the logical module and the memory block based on the netlist information composed of the logical module and the memory block, a procedure for setting a memory sharing index, and floor planning Select the memory to be shared based on the result and memory sharing index, the procedure to evaluate the wiring property and delay of the floor planning result, and select the memory to be unshared from the floor planning result and the wiring property and delay evaluation result Procedure and selected sharing A step of updating the netlist based on memory collection or information of the non-sharing memory set, updated netlist and a step of outputting the floorplanning result resulting design is described so as to run.

(Description of the operation of the first embodiment)
Next, the operation of the present embodiment will be described in detail with reference to the drawings.

  The operation of the semiconductor integrated circuit design apparatus 100 according to the present embodiment will be described in detail with reference to the drawings. FIG. 2 is a flowchart showing an example of the processing procedure of the method for designing a semiconductor integrated circuit according to the embodiment of the present invention.

  The semiconductor integrated circuit design method of the present embodiment inputs a netlist composed of logic modules and memory blocks, and sharable memory block information (step S201), sets a memory sharing index (step S202), and a memory. Blocks and logic modules are arranged (step S203), a memory to be shared is selected based on the memory sharing index (step S204), and the netlist is updated based on the memory sharing information (step S205). The memory blocks and logic modules in the netlist are rearranged (step S206), the delay and wiring property between the memory block and the logic module are evaluated (step S207), and the delay and wiring property evaluation result is the delay and wiring property constraint. Whether or not is satisfied (step S208) If the constraint is not satisfied (step S208 “NO”), a memory block to be unshared is selected based on the delay and wiring property evaluation result (step S209), and a netlist is selected based on the selected unshared memory block information. (Step S2010), the process returns to step S202 again, and the processing from step 2 to step 10 is repeated. However, the index in step S202 is adjusted so that the number of memory blocks included in one shared memory set gradually decreases. The processing from step S202 to step S210 is repeated until it is determined in the delay and wiring property determination in step S208 that the constraints regarding delay and wiring property are satisfied. If it is determined in step S208 that the floor planning result of the netlist corresponding to memory sharing satisfies the constraints on delay and wiring (step S208 “YES”), the memory sharing and floor planning result is designed. The result is output (step S211).

  This will be specifically described below with reference to FIGS.

  First, the input unit 101 receives and stores input of information relating to a memory block and a logic module of a semiconductor integrated circuit to be designed and a netlist expressing a connection between them and a sharable memory set (step S201).

  Here, FIG. 3 shows an example of a net list. In FIG. 3, it is assumed that all memory blocks can be shared. Actually, there is a connection for transferring data between the logic modules, but in FIG. 3, the connection between the logic modules is omitted for simplicity.

  Next, the memory sharing index setting unit 103 sets a memory index to be shared (step S202). Here, the distance between the memory blocks in the floor planning result is used as a memory sharing index. That is, a set of sharable blocks arranged within a distance equal to or smaller than a certain threshold is set as a sharing target, and this threshold is set. First, the length surrounding the entire arrangement area is set as this threshold value.

  Next, with respect to the net list stored by the input unit 101, the floor planning unit 102 performs the arrangement of the logic modules and memory blocks based on the connections between the memory blocks and the logic modules in the net list as shown in FIG. A floor planning result is generated (step S203).

  Next, based on the index set in step S202 and the floor planning result obtained in step S203, the shared memory selection unit 104 selects a memory to be shared (step S204).

  Here, FIG. 4 shows the result of the selection. In FIG. 4, the memory sharing index setting unit 103 uses the distance between memory blocks in the floor planning result as a sharing index, and sets memory blocks arranged within a length surrounding the entire arrangement area as sharing targets. Therefore, all memory blocks are shared.

Next, the net list update unit 105 updates the net list by merging the sharing target memories selected in step S204 (step S205).

  Next, the floor planning unit 102 arranges memory blocks and logic modules for the net list obtained by updating the net list (step S206). Here, FIG. 5 shows the floor planning result for the net list obtained by the net list update.

  Next, the delay and wiring property evaluation / determination unit 106 evaluates the delay and wiring property between the memory block and the logic module (step S207).

  Next, the delay and wiring property evaluation / determination unit 106 determines whether or not the delay and wiring property restriction is satisfied based on the delay and wiring property evaluation result (step S208). Here, it is assumed that it is determined that a wiring property or a delay violation has occurred between logic 1, logic 2, logic 5, logic 6, logic 8 and the reconfigurable memory.

  Next, the unshared memory selection unit 107 selects a memory block to be unshared based on the delay and wiring property evaluation results (step S209). Here, FIG. 6 shows a logic module connected to a memory block selected as a non-sharing target.

  In FIG. 6, the delay and wiring property evaluation / determination unit 106 determines that a wiring property or a delay violation has occurred between logic1, logic2, logic5, logic6, and logic8 and the reconfigurable memory. Memory blocks connected to logic1, logic2, logic5, logic6, and logic8 are selected as non-sharing targets.

  Next, the net list update unit 105 updates the net list based on the memory sharing information (step S210). Here, FIG. 7 shows the net list after the update in step S210.

  Next, returning to step S202, the memory sharing index setting unit 103 updates the memory sharing index. Here, as in the previous case, the distance between the memory blocks in the floor planning result is used as a memory sharing index. In other words, a set of sharable blocks arranged within a distance equal to or smaller than a certain threshold is set as a sharing target, and this threshold is updated. However, this time, 1/2 of one side of the arrangement area is set as this threshold value.

  Next, the floor planning unit 102 rearranges the logic modules and the memory blocks with respect to the net list updated by the memory block non-sharing (step S203).

  Next, a memory to be shared is selected based on the index set in step S202 and the floor planning result obtained in step S203 (step S204). Here, FIG. 4 shows the result of selection.

  In FIG. 4, the memory sharing index setting unit 103 uses the distance between memory blocks in the floorplanning result as a sharing index, and the memory blocks arranged within the length of one side of the arrangement area are displayed. Since it is set as a sharing target, a set of mem1 and mem6, a set of mem5 and mem8, and a set of mem2 and a reconfigurable memory are set as sharing sets.

  Next, the net list update unit 105 updates the net list by merging the sharing target memories selected in step S204 (step S205). FIG. 10 shows a net list obtained by updating the net list.

  Next, the floor planning unit 102 arranges memory blocks and logic modules again for the net list obtained by updating the net list (step S206). FIG. 10 shows the floor planning result.

  Next, the delay and wiring property evaluation / determination unit 106 evaluates the delay and wiring property between the memory block and the logic module (step S207).

  Next, the delay and wiring property evaluation / determination unit 106 determines whether or not the delay and wiring property restriction is satisfied based on the delay and wiring property evaluation result (step S208). Here, if it is determined that the wiring property and the delay violation have not occurred (step S208 “YES”), the net list and the floor planning result of FIG. 10 are output as the design result (step S211).

(Effects of the first embodiment)
Next, the effect of this embodiment will be described.

  According to the semiconductor integrated circuit design apparatus and design method of the present embodiment, in designing a semiconductor integrated circuit to be designed using a reconfigurable memory having a variable storage capacity and port position, the memory block and the logic module In consideration of the arrangement, it is possible to share the memory blocks so that the wiring property is good and the delay is small. This makes it possible to design a semiconductor integrated circuit having a small area and high performance.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  The various components of the present invention do not necessarily have to be independent of each other. A plurality of components are formed as a single member, and a single component is formed of a plurality of members. It may be that a certain component is a part of another component, a part of a certain component overlaps with a part of another component, or the like.

  Moreover, although the several procedure is described in order in the method and computer program of this invention, the order of the description does not limit the order which performs a several procedure. For this reason, when implementing the method and computer program of this invention, the order of the several procedure can be changed in the range which does not interfere in content.

  Furthermore, the plurality of procedures of the method and the computer program of the present invention are not limited to being executed at different timings. For this reason, another procedure may occur during the execution of a certain procedure, or some or all of the execution timing of a certain procedure and the execution timing of another procedure may overlap.

(Appendix 1)
In the memory sharing index setting step,
9. The method of designing a semiconductor integrated circuit according to claim 8, wherein a distance between memory blocks in the floor planning result is used as the memory block sharing index.

(Appendix 2)
In the shared memory selection step,
The set of the sharable memory blocks in which the distance between the memory blocks in the floor planning result is equal to or less than the memory block sharing index is selected as the shared memory set. A method for designing a semiconductor integrated circuit.

(Appendix 3)
In the unshared memory selection step,
In the floor planning result, the logical module that causes a wiring constraint violation or a delay constraint violation with a shared memory block is selected, and the memory block used by the selected logical module is unshared. 9. The method for designing a semiconductor integrated circuit according to claim 8, wherein the memory set is selected as a memory set.

(Appendix 4)
In the netlist update step,
When sharing the memory block, the netlist is updated in such a manner that the target memory block in the netlist is merged into one memory block,
The non-shared memory block includes updating the net list by separating the target memory block in the net list from the shared memory block. 2. A method for designing a semiconductor integrated circuit according to item 1.

(Appendix 5)
Based on the updated netlist output as the design result and the floor planning result,
The processing by the memory sharing index step, the processing by the floor planning step, the processing by the shared memory selection step, the processing by the unshared memory selection step, the processing by the netlist update step, and the wiring 5. The method for designing a semiconductor integrated circuit according to claim 8, further comprising a step of repeatedly executing the processing by the performance and delay evaluation / determination step. 6.

(Appendix 6)
In the memory sharing index setting step,
The method for designing a semiconductor integrated circuit according to appendix 5, wherein the memory block sharing index is adjusted so that the number of shared memories gradually decreases.

(Appendix 7)
In the memory sharing index setting process,
The program according to claim 9, wherein a distance between memory blocks in the floor planning result is used as the memory block sharing index.

(Appendix 8)
In the shared memory selection process,
The additional memory according to claim 7, wherein a set of the sharable memory blocks whose distance between the memory blocks in the floor planning result is equal to or smaller than the memory block sharing index is selected as the shared memory set. program.

(Appendix 9)
In the unshared memory selection process,
In the floor planning result, the logical module that causes a wiring constraint violation or a delay constraint violation with a shared memory block is selected, and the memory block used by the selected logical module is unshared. The program according to claim 9 or appendix 7 or appendix 8, wherein the program is selected as a memory set.

(Appendix 10)
In the netlist update process,
When sharing the memory block, the netlist is updated in such a manner that the target memory block in the netlist is merged into one memory block,
10. When the memory block is unshared, the net list is updated in such a manner that the target memory block in the net list is separated from the shared memory block. The program according to item 1.

(Appendix 11)
Based on the updated netlist output as the design result and the floor planning result,
The memory sharing index process, the floor planning process, the shared memory selection process, the non-shared memory selection process, the netlist update process, the wiring property and delay evaluation / determination process, The program according to any one of claims 9 or 7 to 10, wherein a process to be repeatedly executed is executed.

(Appendix 12)
In the memory sharing index setting process,
The program according to appendix 11, wherein the memory block sharing index is adjusted so that the number of shared memories gradually decreases.

DESCRIPTION OF SYMBOLS 100: Design apparatus 101: Input part 102: Floor planning part 103: Memory sharing parameter | index setting part 104: Shared memory selection part 105: Net list update part 106: Delay and wiring property evaluation / determination part 107: Unshared memory Selection unit 108: Output unit

Claims (9)

Input means for inputting information on a set of sharable memory blocks composed of information on a netlist composed of logic modules and memory blocks, and information on the memory blocks used exclusively;
Floor planning means for determining an arrangement position of the logic module and the memory block based on information on the netlist;
A memory sharing index setting means for setting a memory block sharing index;
Shared memory selecting means for selecting a memory block to be shared as a shared memory set based on the floor planning result determined by the floor planning means and the memory block sharing index;
Wiring property and delay evaluation / determination means for evaluating wiring property and delay of the floor planning result,
Unshared memory selection means for selecting a memory block to be unshared as a non-shared memory set from the floor planning result and the wiring property and delay evaluation result;
Netlist update means for updating the netlist based on information of the selected shared memory set or unshared memory set;
An apparatus for designing a semiconductor integrated circuit, comprising: an output unit that outputs the net list updated by the net list update unit and the floor planning result as a design result. The memory sharing index setting means includes:
2. The apparatus for designing a semiconductor integrated circuit according to claim 1, wherein a distance between memory blocks in the floor planning result is used as the memory block sharing index. The shared memory selection means includes
3. The set of sharable memory blocks whose distance between the memory blocks in the floor planning result is equal to or less than the memory block sharing index is selected as the shared memory set. Semiconductor integrated circuit design equipment. The unshared memory selection means includes:
In the floor planning result, the logical module that causes a wiring constraint violation or a delay constraint violation with a shared memory block is selected, and the memory block used by the selected logical module is unshared. 4. The semiconductor integrated circuit design apparatus according to claim 1, wherein the apparatus is selected as a memory set. The netlist update means includes
When sharing the memory block, the netlist is updated in such a manner that the target memory block in the netlist is merged into one memory block,
5. The method according to claim 1, wherein when the memory block is unshared, the net list is updated in such a manner that a target memory block in the net list is separated from the shared memory block. The semiconductor integrated circuit design apparatus described in 1. Based on the updated netlist output as the design result and the floor planning result,
The processing by the memory sharing index means, the processing by the floor planning means, the processing by the shared memory selection means, the processing by the unshared memory selection means, the processing by the netlist update means, and the wiring 6. The apparatus for designing a semiconductor integrated circuit according to claim 1, further comprising means for repeatedly executing the processing by the performance and delay evaluation / determination means. The memory sharing index setting means includes:
7. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein the memory block sharing index is adjusted so that the number of shared memories gradually decreases. An input step for inputting information on a set of sharable memory blocks composed of information on a netlist composed of logic modules and memory blocks, and information on the memory blocks used exclusively;
A floor planning step for determining an arrangement position of the logic module and the memory block based on information on the netlist;
A memory sharing index setting step for setting a memory block sharing index;
A shared memory selection step of selecting a memory block to be shared as a shared memory set based on the floor planning result determined in the floor planning step and the memory block sharing index;
Wiring property and delay evaluation / determination step for evaluating wiring property and delay of the floor planning result,
A non-shared memory selection step of selecting a memory block to be unshared as a non-shared memory set from the floor planning result and the wiring property and delay evaluation result;
A netlist update step for updating the netlist based on information of the selected shared memory set or unshared memory set;
A design method of a semiconductor integrated circuit, comprising: an output step of outputting the net list updated by the net list update step and the floor planning result as a design result. In a computer that is a design device for semiconductor integrated circuits,
An input process for inputting information on a set of sharable memory blocks composed of information on a netlist composed of logic modules and memory blocks, and information on the memory blocks used exclusively;
A floor planning process for determining an arrangement position of the logic module and the memory block based on information on the netlist;
A memory sharing index setting process for setting a memory block sharing index;
A shared memory selection process for selecting a memory block to be shared as a shared memory set based on the floor planning result determined in the floor planning process and the memory block sharing index;
Wiring property and delay evaluation / determination processing for evaluating wiring property and delay of the floor planning result;
A non-shared memory selection process for selecting a memory block to be shared as a non-shared memory set from the floor planning result and the wiring property and delay evaluation result;
A netlist update process for updating the netlist based on information of the selected shared memory set or the unshared memory set;
A program for executing the output process for outputting the net list updated by the net list update process and the floor planning result as a design result.

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