JP2011129024A - Data processing system and data processing method - Google Patents

Abstract

A data processing apparatus is provided that can acquire spin locks in the order in which the spin locks were acquired.
The reserved area of the spin lock variable is a FIFO configuration, and the order in which the spin locks are acquired is stored therein, so that the spin locks are transferred in the order in which the processing unit has acquired the spin locks. It is a thing. This is different from the configuration in which the spin locks are distributed to the processing units in the round robin order based on the predetermined processing unit numbers.
[Selection] Figure 1

Description

  The present invention relates to a spin lock and unlock technique in which a plurality of processing units perform exclusive control on a shared resource, and relates to a technique that is effective when applied to, for example, a semiconductor data processing apparatus in which a multiprocessor system is on-chip.

  In a multiprocessor system having a plurality of processing units, when there is a possibility that one processing resource may access one resource, one processing unit obtains the right to access the resource exclusively from another processing unit. Access from. Such an exclusive access right is given by acquiring a lock. Locks are acquired by the only processing unit that has successfully performed an atomic read-modify-write on a lock variable in memory. A processing unit that fails an atomic read-modify-write tries an atomic read-modify-write to the lock variable while spinning the loop until the lock is successfully acquired after the lock is released. Such a lock implementation is called a spin lock. When multiple processing tries to acquire the same spin lock, only a specific processing unit acquires the spin lock, and the problem of starvation that other processing units cannot acquire the spin lock indefinitely occurs. In other words, assuming that there is a predetermined priority for acquiring the bus access right, if a processing unit with a high priority regarding the bus access right tries to acquire the spin lock continuously, the priority of the bus access right is higher than that. Other low processing units cannot acquire the bus right to perform an atomic read-modify-write on the lock variable in the memory, and spin lock is applied as long as the bus access by a processing unit with a higher bus access right is required. I can't get it.

  There exists a technique of patent document 1 as a technique which relieves the starvation state. According to this, a core number of a processing unit (also simply referred to as a core) waiting for a spin lock is encoded in a bit position in the reserved area of the spin lock variable to indicate a spin lock waiting state. A core that happens to take a spinlock by chance while the spinlock is released can acquire the spinlock without any problem. On the other hand, when the other core has already acquired the spin lock and the own core cannot be acquired, the bit position of the own core number in the reserved area of the spin lock variable is set to 1 and the release of the spin lock is awaited. When another core that has acquired the spin lock releases the spin lock, the bit position of the reserved area of the lock variable is searched in round robin order, and the core in which the bit is set acquires the lock.

US Pat. No. 6,777,090

  The technique described in Patent Document 1 is characterized in that the core can acquire the spin lock in the round robin order. For this reason, in the prior art, the problem is that the spin locks cross between cores is not the order in which the spin locks were acquired, but the spin locks passed in a predetermined order. The processing core cannot acquire the spin lock efficiently.

  An object of the present invention is to provide a data processing apparatus capable of acquiring spin locks in the order in which the spin locks were acquired.

  Another object of the present invention is to provide a data processing method capable of acquiring spin locks in the order in which the spin locks were acquired.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, the reserved area of the spin lock variable has a FIFO configuration, and the order in which the spin locks are acquired is stored therein, so that the spin locks are passed in the order in which the processing unit went to acquire the spin locks. Is. This is different from the configuration in which the spin locks are distributed to the processing units in the round robin order based on the predetermined processing unit numbers.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, spinlocks can be acquired fairly in the order in which the plurality of processing units went to acquire the spinlock.

FIG. 1 is an explanatory diagram showing a detailed example of the spin lock variable region LOCK_FLD used in the first embodiment. FIG. 2 is an explanatory diagram illustrating a program Q executed in parallel by the respective processing units CPU_00 to CPU_11 in order to access the peripheral circuit PRPH which is a common resource. FIG. 3 is a flowchart illustrating an initialization flow of the spin lock variable area. FIG. 4 is a flowchart illustrating the control flow of the spin lock process when the function spinlock is executed in the first embodiment. FIG. 5 is a flowchart illustrating a control flow of unlock processing when the function unlock is executed in the first embodiment. 6 is a block diagram illustrating a schematic configuration of the data processing system. FIG. 7 is an operation explanatory diagram for specifically explaining operations by spin lock processing and unlock processing in the first embodiment. FIG. 8 is an operation explanatory diagram showing a continuation of FIG. FIG. 9 is an operation explanatory diagram showing a continuation of FIG. FIG. 10 is an operation explanatory view showing the continuation of FIG. FIG. 11 is an operation explanatory diagram showing a continuation of FIG. FIG. 12 is an operation explanatory diagram showing a continuation of FIG. FIG. 13 is an operation explanatory view showing the continuation of FIG. FIG. 14 is an operation explanatory diagram showing a continuation of FIG. FIG. 15 is an operation explanatory view showing the continuation of FIG. FIG. 16 is an operation explanatory view showing the continuation of FIG. FIG. 17 is an operation explanatory view showing the continuation of FIG. FIG. 18 is an operation explanatory diagram showing a continuation of FIG. FIG. 19 is an explanatory diagram showing a detailed example of the spin lock variable region LOCK_FLDS used in the second embodiment. FIG. 20 is a flowchart illustrating the control flow of the spin lock process when the function spinlock is executed in the second embodiment. FIG. 21 is a flowchart illustrating a control flow of unlock processing when the function unlock is executed in the second embodiment.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] In a data processing system (SYS) according to a typical embodiment, a plurality of processing units (CPU_00 to CPU_11) sharing resources (PRPH) operate spin lock variable areas (LOCK_FLD, LOCK_FLDS). The spin lock is acquired, the spin lock variable area has a registration area (BUFF, RING_BUFF) in the waiting order for the spin lock, and the processing unit performs the processing in the order of failure when acquisition of the spin lock fails. Register the unit name in the registration area of the waiting order, wait for the registered own order to be updated to the earliest order, acquire the spin lock, and release the acquired spin lock The first place in the waiting order of each registered in the registration area To shift to.

  From the above, the registration area of the waiting order, which is the reserved area of the spin lock variable, is configured as a FIFO, the order in which the spin lock was acquired is registered there, and the processing unit that is reserved and registered first is the next spin unit. Since the locks can be acquired, the spin locks are transferred in the order in which the processing unit went to acquire the spin lock. Since the spin locks are not distributed to the processing units in the round robin order based on the predetermined processing unit numbers, the spin locks can be acquired fairly in the order in which the plurality of processing units went to acquire the spin locks.

  [2] A data processing system (SYS) according to a more specific embodiment includes a plurality of processing units (CPU_00 to CPU_11), a resource (PRPH) shared by the plurality of processing units, and the plurality of processing units. And a spin lock variable region (LOCK_FLD, LOCK_FLDS) operated by the processing unit. The spin lock variable area includes a lock bit (LOCK_BIT) for indicating whether or not the resource can be used, and a waiting order registration area (BUFF) for holding the order of processing units waiting for the resource to be used. , RING_BUFF). The processing unit performs a spin lock process (spinlock) and an unlock process (unlock) when using a resource. In the spin lock process, when the lock bit is read to detect that the spin lock state is released, the lock bit is manipulated to acquire the spin lock state, and the lock bit is read and the spin lock has already been performed. When it is detected that the status has been acquired, the processing unit is registered in the waiting-order registration area, and the spinlock status is acquired after waiting for it to be moved up first. In the unlock process, when releasing the spin lock state acquired in the spin lock process, if there is a processing unit registered in the waiting order registration area and waiting, the waiting order is incremented by one. Otherwise, it is a process of releasing the spin lock state by operating the lock bit.

  From the above, the registration area of the waiting order, which is the reserved area of the spin lock variable, is configured as a FIFO, the order in which the spin lock was acquired is registered there, and the processing unit that is reserved and registered first is the next spin unit. Since the locks can be acquired, the spin locks are transferred in the order in which the processing unit went to acquire the spin lock. Since the spin locks are not distributed to the processing units in the round robin order based on the predetermined processing unit numbers, the spin locks can be acquired fairly in the order in which the plurality of processing units went to acquire the spin locks.

[3] <Atomic processing in spin lock processing>
In the data processing system according to item 2, when the processing unit detects that the spin lock state is released by reading the lock bit in the spin lock process, the processing unit acquires the spin lock state by operating the lock bit. When the lock bit is read and it is detected that the spin lock state has already been acquired, the access right to the spin lock variable area is given when performing processing for registering the processing unit in the waiting registration area. Occupy. The spin lock process can be performed without contradiction.

[4] <Atomic processing in unlock processing>
In the data processing system according to item 2, the processing unit occupies an access right to the spin lock variable area and performs the unlock process. Unlock processing can be performed without contradiction.

[5] <FIFO method with shift register>
In the data processing system according to Item 2, the processing unit moves up the waiting order by shifting the processing unit name registered in the registration area of the waiting order in one direction.

  [6] In the data processing system according to item 3, the spin lock variable area further includes a current unit name holding area (CURRENT_CPU_ID) indicating a processing unit that currently acquires the spin lock state. At this time, when the spin lock process detects that the spin lock state is released by reading the lock bit, the spin lock state is manipulated to acquire the spin lock state, and the processing unit name is set to the current Record in the unit name holding area (S12), and when the lock bit is read to detect that the spin lock state has already been acquired, the processing unit is registered in the waiting order registration area (S13), This process waits until it is first moved up (S14, S15) and acquires the spin lock state. In the unlock process, when the spin lock state acquired in the spin lock process is released, if there is a processing unit that is registered and waiting in the registration area of the waiting order, the waiting process is incremented by one and the earliest processing unit The current unit name holding area is rewritten with the name (S23). If there is no waiting processing unit, the spinlock variable area is initialized (S22) to release the spinlock state.

  [7] In the data processing system according to item 5, the spin lock variable area further includes a wait number holding area (FIFO_LENGTH) for holding the number of processing units registered and waiting in the waiting order registration area. At this time, the processing unit determines whether or not there is a processing unit that is registered in the waiting-order registration area and is waiting based on the number held in the waiting number holding area.

[8] <FIFO method with ring buffer>
In the data processing system according to item 3, the registration area in the waiting order has a number of entry areas (RING_BUFF) corresponding to the number of the plurality of processing units (CP_00 to CPU_11). Furthermore, a first pointer (TOP) indicating the address of the entry area and a second pointer (BOTTOM) indicating the address of the entry area are included. At this time, when the spin lock process reads the lock bit and detects that the spin lock state is released, it operates the lock bit to acquire the spin lock state and sets the processing unit name to It is stored in the entry area pointed to by the initial value of one pointer (S32), and when it is detected that the spin lock state has already been acquired by reading the lock bit, the value of the second pointer is advanced to the second pointer. The processing unit name is registered in the entry area pointed to by the value of (S33), waits for it to be pointed by the first pointer (S34, S35), and acquires the spin lock state. In the unlock process, when releasing the spin lock state acquired in the spin lock process, if the value of the first pointer is not equal to the value of the second pointer, the value of the first pointer is advanced (S43) and waiting. If there is no processing unit, the spin lock variable area is initialized (S42) to release the spin lock state.

  [9] A data processing method according to a representative embodiment is a method in which a plurality of processing units that share resources manipulate a spin lock variable area to acquire a spin lock, and the spin lock variable area When the spin lock acquisition fails, the processing unit names are registered in the order of failure in the registration area of the waiting order, which is the reserved area for the spin lock variable assigned to, and next to the processing unit that is reserved first. Get the spinlock of

  [10] A data processing method according to a more specific embodiment is a method in which a plurality of processing units sharing resources perform spin lock processing and unlock processing by operating a spin lock variable area, The spin lock variable area includes a lock bit for indicating whether or not the resource can be used, and a waiting order registration area for holding the order of processing units waiting for the resource. In the spin lock process, when the processing unit reads the lock bit and detects that the spin lock state is released, the spin unit operates the lock bit to acquire the spin lock state and reads the lock bit. When it is detected that the spin lock state has already been acquired, the processing unit is registered in the registration area in the waiting order, and the process of acquiring the spin lock state after waiting for it to be advanced first. is there. In the unlock process, when the acquired spin lock state is released, if there is a waiting processing unit registered in the waiting order registration area, the waiting order is incremented by one, and if there is no waiting processing unit, the lock bit is set. This is a process to release the spin lock state by operating.

[11] <Atomic process in spin lock process>
In the data processing method according to item 10, in the spin lock process, the processing unit occupies an access right to the spin lock variable area and reads the lock bit to detect that the spin lock state is released. When the lock bit is manipulated to acquire the spin lock state, and when the lock bit is read to detect that the spin lock state has already been acquired, the processing unit is registered in the registration area in the waiting order. Perform processing.

[12] <Atomic processing in unlock processing>
In the data processing method according to item 11, the processing unit occupies an access right to the spin lock variable area and performs the unlock process.

[13] <FIFO method with shift register>
A data processing method according to another specific embodiment is a method in which a plurality of processing units sharing resources perform spin lock processing and unlock processing by operating a spin lock variable area, The lock variable area includes a lock bit for indicating whether or not the resource can be used, a waiting area registration area for holding the order of processing units waiting for the resource, and a spin lock state. A current unit name holding area indicating the acquired processing unit. In the spin lock process, when the processing unit reads the lock bit and detects that the spin lock state is released, the spin lock state is manipulated to acquire the spin lock state, and the processing unit name is changed. When recording the current unit name holding area and detecting that the spin lock state has already been acquired by reading the lock bit, the processing unit is registered in the waiting order registration area, This is a process of acquiring the spin lock state after waiting for the advance. In the unlock process, when the acquired spin lock state is released, if there is a waiting processing unit registered in the waiting order registration area, the waiting unit is incremented by one and the current unit name is the first processing unit name. This process rewrites the holding area and releases the spin lock state by operating the lock bit if there is no processing unit waiting.

[14] <FIFO method with ring buffer>
A data processing method according to yet another specific embodiment is a method in which a plurality of processing units sharing resources perform spin lock processing and unlock processing by operating a spin lock variable area, The spin lock variable area includes a lock bit for indicating whether or not the resource can be used, and a waiting order registration area for holding the order of processing units waiting for the resource. The waiting-order registration area has a number of entry areas corresponding to the number of the plurality of processing units, a first pointer indicating an address of the entry area, and a second pointer indicating an address of the entry area. . In the spin lock process, when the processing unit reads the lock bit and detects that the spin lock state is released, the spin lock state is manipulated to acquire the spin lock state, and the processing unit name is changed. The entry stored in the entry area pointed to by the first pointer and reading the lock bit and detecting that the spin lock state has already been acquired, advances the value of the second pointer to indicate the entry pointed to by the value of the second pointer The processing unit name is registered in the area and waits for the processing unit name to be pointed by the first pointer to acquire the spin lock state. In the unlock process, when the acquired spin lock state is released, the value of the first pointer is advanced if the value of the first pointer is not equal to the value of the second pointer, and the lock bit is set if there is no processing unit waiting. This is a process to release the spin lock state by operating.

2. Details of Embodiment << First Embodiment >>
FIG. 6 illustrates a data processing system according to the first embodiment. The data processing system shown in the figure is a microcomputer composed of a single chip or a multichip, although not particularly limited. The microcomputer composed of a single chip is not particularly limited, but the microcomputer composed of a single-chip semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique, etc. Although not limited, a plurality of semiconductor integrated circuits are mounted on a multilayer wiring board or the like. In any configuration, the data processing system SYS constitutes a multiprocessor system.

  The data processing system SYS is not particularly limited, but a plurality of, for example, four processing units CPU_00 to CPU_11 and peripheral circuits typically shown as resources (shared resources) shared by the plurality of processing units CPU_00 to CPU_11 The PRPH and a memory MRY such as a RAM (Random Access Memory) accessible by a plurality of processing units CPU_00 to CPU_11 are connected to a bus BUS.

  Each of the processing units CPU_00 to CPU_11 is not particularly limited, but has at least a central processing unit (Central Processing Unit) for executing instructions, and a processor including a cache memory and a memory management unit as necessary. Configured as a core. In this data processing system, when there is a possibility that multiple processing units may access one resource, it is necessary that one processing unit obtains the right to access the resource exclusively from other processing units before accessing it. become. In order to control the acquisition and release of such exclusive access right by acquiring and releasing the spin lock, the memory MRY is assigned a spin lock variable area LOCK_FLD operated by the processing units CPU_00 to CPU_11. The spin lock variable region LOCK_FLD shown here representatively shows, for example, one related to one peripheral circuit PRPH. The spin lock variable area LOCK_FLD is not particularly limited, but is actually preferably allocated for each resource that is subject to access control using the spin lock.

  A bus arbiter or a bus router (not shown) is arranged on the bus BUS, arbitrating bus access requests that compete with each other according to the adopted bus protocol, and assigning bus rights and controlling routing of signal paths. The spin lock control using the spin lock variable region LOCK_FLD is such that the access requesting entity autonomously controls the contention of access to the shared resource.

  FIG. 1 shows a detailed example of the spin lock variable area LOCK_FLD. The spin lock variable area LOCK_FLD has, for example, a 32-bit area in total, a FIFO (First In-First Out) buffer BUFF (FIFO_1st to FIFO_3rd) in bits B31-26, a current unit number CURRENT_CPU_ID, bits in bits 25-24 The number of waiting entries FIFO_LENGTH is assigned to B17-16, and the lock bit LOCK_BIT is assigned to bit B0.

  The FIFO buffer BUFF has three entry areas FIFO_1st to FIFO_3rd. In the entry areas FIFO_1st to FIFO_3rd, the IDs of the processing units waiting due to the spin lock acquisition are registered in the waiting order. The FIFO entry area FIFO_1st holds the ID of the first priority, the FIFO entry area FIFO_2nd holds the ID of the second priority, and the FIFO entry area FIFO_3rd holds the ID of the third priority. Here, the ID of the processing unit CPU_00 is “00”, the ID of the CPU_01 is “01”, the ID of the CPU_10 is “10”, and the ID of the CPU_11 is “11”. Although details will be described later, the FIFO operation for the FIFO entry areas FIFO_1st to FIFO_3rd is performed by a right shift operation of the registration ID to the higher order side.

  The current unit number CURRENT_CPU_ID indicates the ID of the processing unit that is currently acquiring the spin lock.

  The number of waiting entries FIFO_LENGTH indicates the number of processing units waiting for the subsequent acquisition after failing to acquire the spin lock, that is, the number of processing IDs held in the FIFO buffer BUFF. It has the significance of distinguishing whether "00" held in the FIFO entry areas FIFO_1st to FIFO_3rd is the ID "00" or just the initial value "00".

  The lock bit LOCK_BIT is “1” indicating the acquisition state of the spin lock, and “0” indicates the release state of the lock.

  Next, a specific example of the spin lock control procedure using the spin lock variable region LOCK_FLD will be described.

  FIG. 2 illustrates a program Q executed in parallel by the respective processing units CPU_00 to CPU_11 in order to access the peripheral circuit PRPH which is a common resource. LOOP_0 of Line_1 is a label of the loop start address. Line_2 executes the function spinlock. The execution of this function spinlock is not completed until the spinlock is acquired, and is completed when it is acquired. Acquisition of the spin lock and release of the lock are equated with acquisition and release of the exclusive access right to the peripheral circuit PRPH. In Line_3, the function “print” is executed, and for example, its own processing ID is output to the peripheral circuit PRPH to control devices such as a printer. This operation is time-consuming until the other three processing units can sequentially perform atomic read-modify-write to the same address until completion. In short, while controlling a device such as a printer, the bus right is temporarily released, and a state in which another processing unit can access the spinlock variable area LOCK_FLD and execute the function spinlock is given. . In Line_4, execute the function unlock to release the acquired lock. Thereafter, the process returns to the loop start address LOOP_0 at Line_5.

  FIG. 3 illustrates an initialization flow of the spin lock variable area LOCK_FLD. Before each processing unit CPU_00 to CPU_11 starts executing the program of FIG. 2, a predetermined processing unit initializes the spin lock variable area LOCK_FLD to all bits “0” as illustrated in FIG. 6 (S1). .

  FIG. 4 shows a control flow of the spin lock process when the function spinlock is executed. The processing unit that has acquired the bus right reads the spin lock variable area LOCK_FLD to determine whether it is the initial value. That is, it is determined whether or not the lock bit LOCK_BIT is set to “0” (the spin lock state is released) (S11). When it is determined that the spin lock state has been released, its own processing unit ID (own CPU_ID) is recorded in the area of the current unit number CURRENT_CPU_ID, and the lock bit LOCK_BIT is rewritten to “1” (S12). Get lock status. When the spin lock state is not released (when acquisition of the spin lock has failed), its own processing unit ID (own CPU_ID) is registered at the end of the FIFO buffer BUFF, and 1 is added to the number of waiting entries FIFO_LENGTH. (S13). For the end of the FIFO buffer BUFF, a FIFO entry area having a rank indicated by a value obtained by adding 1 to the value of the number of entries FIFO_LENGTH may be selected. For example, when the CPU_ID is registered in the FIFO entry area FIFO_1st and the number of waiting entries is one, the value “2” obtained by adding 1 to the value “1” of the number of entries FIFO_LENGTH is set to the second-order FIFO entry area FIFO_2nd. The own CPU_ID may be stored. That is, when acquisition of the spin lock fails, the processing unit IDs are registered in the FIFO buffer BUFF in the order of failure. After that, it waits for the processing ID held in the area of the current unit number CURRENT_CPU_ID to be updated to its own processing ID (local CPU_ID) (S14, S15). In short, its own order registered in the FIFO buffer BUFF The spinlock can be acquired by waiting for the first to be updated. The current unit number CURRENT_CPU_ID is updated when another processing unit releases the acquired spin lock in the unlock process described later.

  Steps S11, S12, and S13 are atomic processes, and the processing unit does not pass the access right to the spinlock variable area LOCK_FLD to other processing units until the processes of steps S11, S12, and S13 are completed. The processing units CPU_00 to CPU_11 have a load instruction and a store instruction in an instruction set that can be used to realize such read, modify, and write access as atomic processing.

  FIG. 5 shows a control flow of unlock processing when the function unlock is executed. In the unlocking process, the value of the number of entries FIFO_LENGTH is read, and it is determined whether there is a processing unit registered and waiting in the FIFO buffer BUFF depending on whether the value is “0” (S21). If there is none, the spin lock variable area LOCK_FLD is initialized (S22), and the spin lock is released. If there is a waiting processing unit, the processing ID held in the area of the current unit number CURRENT_CPU_ID is updated to the processing ID registered in the entry area FIFO_1st, and the values held in the entry areas FIFO_1st to FIFO_3rd are shifted, The waiting order is incremented by one, and the entry number FIFO_LENGTH is decremented by 1 and updated, and the unlocking process is terminated (S23). By performing the process of step S23 several times, the rank of the waiting order of the processing units that have failed to acquire the spin lock is sequentially raised toward the top.

  As described above, each of the processing units CPU_00 to CPU_11 registers the IDs of the processing units in the FIFO buffer BUFF in the order of failure when the spin lock acquisition fails, and the registered order of the processing unit CPU_00 to CPU_11 is the earliest. Wait for the rank to be updated and acquire the spin lock. When releasing the acquired spin lock, the rank of each waiting order registered in the FIFO buffer BUFF is shifted one by one to the other direction. Provides an opportunity for processing units to acquire spinlocks. Accordingly, the spin locks are transferred in the order in which the processing unit went to acquire the spin lock. Since the spin locks are not distributed to the processing units in the round robin order based on the predetermined processing unit numbers, the spin locks can be acquired fairly in the order in which the plurality of processing units went to acquire the spin locks.

  The operations of the spin lock process and the unlock process by the processing units CP_00 to CPU_11 will be specifically described with reference to FIGS.

  The spin lock variable area LOCK_FLD is initialized to the state shown in FIG. 6, and the respective processing units CPU_00 to CPU_11 execute the program Q shown in FIG. 2 in parallel. At this time, the implementation of the bus BUS is not fair to the respective processing units CPU_00 to CPU_11. There is a priority order unique to the bus, and the priority order for acquiring the bus right when the atomic read-modify-write to the same address competes among the plurality of processing units CPU_00 to CPU_11 is, for example, CPU_00, CPU_01, CPU_10. , CPU_11 in order. Generality is not lost with this assumption.

  In accordance with this priority order, the processing unit CPU_00 acquires the bus right and executes the function spinlock, and executes atomic read / modify / write to the spin lock variable area LOCK_FLD through the paths (a) and (b) of FIG. To do. As a result, in the spin lock variable area LOCK_FLD, as shown in FIG. 7, the lock bit LOCK_BIT is rewritten from “0” to “1”, and the processing of the function spinlock of the Line_2 of the program Q is completed. Next, the processing unit CPU_00 acquires the exclusive access right to the peripheral circuit PRPH, executes the function print of the Line_3 of the program Q, and outputs its own processing ID (own CPU_ID) to the peripheral circuit PRPH via the path (c). To do.

  When the processing unit CPU_00 executes the function print in the Line_3 of the program Q, it takes time as described above, and during that time, the other three processing units CPU_01, CPU_10, and CPU_11 execute the function spinlock of the program. Among the processing units CPU_01, CPU_10, and CPU_11, the CPU_01 having the highest priority order acquires the bus right, but because the acquisition of the spin lock fails, step S13 in FIG. 4 is executed, and (d) and (d) in FIG. Atomic read-modify-write is executed in the path e). As a result, the contents of the spin lock variable area LOCK_FLD are changed as shown in FIG. That is, the ID “01” of the processing unit CPU_01 is registered in the first entry area FIFO_1st in the FIFO buffer BUFF, and the number of waiting entries FIFO_LENGTH becomes 01 (one). Thereafter, the processing unit CPU_01 reads the spin lock variable area LOCK_FLD through the path (f) in FIG. 8, but the current unit number CURRENT_CPU_ID of the spin lock variable area LOCK_FLD is “00” and is not equal to “01” of the own CPU_ID. A loop passing through steps S14 and S15 of 4 is performed (spin). The processing unit CPU_00 goes around the loop and waits for the current unit number CURRENT_CPU_ID to be equal to “01” of its own CPU_ID.

  The processing units CPU_10 and CPU_11 are executing the function spinlock of the program Q. Among them, the processing unit CPU_10 having a higher priority order acquires the bus right to execute the atomic read-modify-write, and executes step S13 in FIG. Then, atomic read-modify-write is executed along the paths (g) and (h) in FIG. As a result, as shown in FIG. 9, the content of the spin lock variable area LOCK_FLD is registered with the ID “10” of the processing unit CPU_10 in the second entry area FIFO_2nd and the number of waiting entries FIFO_LENGTH is 10 (two). Become. Thereafter, the processing unit CPU_10 reads the spin lock variable area LOCK_FLD through the path (i) in FIG. 9, but the current unit number CURRENT_CPU_ID is “00” and is not equal to “10” of its own CPU_ID. Rotate (spin) the loop of S15. The processing unit CPU_10 goes around the loop and waits for the current unit number CURRENT_CPU_ID to be equal to “10” of its own CPU_ID.

  The last remaining processing unit CPU_11 is executing the function spinlock of the program Q. Among them, the bus right for executing the atomic read-modify-write is acquired, and step S13 in FIG. j) Atomic read-modify-write is executed along the path (k). As a result, as shown in FIG. 10, the contents of the spin lock variable area LOCK_FLD are registered with the ID “11” of the processing unit CPU_11 in the third entry area FIFO_3rd, and the waiting entry number FIFO_LENGTH is 11 (three). Become. Thereafter, the processing unit CPU_11 reads the spin lock variable area LOCK_FLD through the path (m) in FIG. 10, but the current unit number CURRENT_CPU_ID is “00” and is not equal to “11” of its own CPU_ID. Rotate (spin) the loop of S15. The processing unit CPU_11 goes around the loop and waits for the current unit number CURRENT_CPU_ID to be equal to “11” of its own CPU_ID.

  When the processing unit CPU_00 completes the execution of the function print of the Line_3 of the program Q, the processing unit CPU_00 executes the unlock processing of the function unlock of the Line_4, and releases the exclusive access right to the peripheral circuit PRPH, that is, releases the spin lock. The processing unit CPU_00 executes the step S23 of FIG. 5 because the number of waiting entries FIFO_LENGTH is not “0” in the process of the function unlock, and executes the admic read-modify-write through the paths (n) and (o) of FIG. To do. As a result, the contents of the spin lock variable area LOCK_FLD are rewritten as shown in FIG. That is, “01” which is the value of the first entry area FIFO_1st is transferred to the current unit number CURRENT_CPU_ID, the waiting order in the FIFO buffer BUFF is incremented by one, and the value “10” of the second entry area FIFO_2nd is transferred. Is shifted to the first entry area FIFO_1st, the value “11” of the third entry area FIFO_3rd is shifted to the second entry area FIFO_2nd, and finally the waiting entry number FIFO_LENGTH value “11” is set to 1. Pull to “10”. The third entry area FIFO_3rd is empty.

  At this time, the processing unit CPU_01 performs the processing of the loop of FIG. 4 (steps S14 and S15) by the spin lock processing, but the current unit number CURRENT_CPU_ID is “01” which is the own CPU_ID of the processing unit CPU_01 by the processing of FIG. Therefore, the processing unit CPU_01 completes the spin lock process and acquires the spin lock by detecting it by reading the spin lock variable area LOCK_FLD through the path (f). As a result, the processing unit CPU_01 obtains the exclusive access right to the peripheral circuit PRPH, starts the processing of Line_3 of the program Q, and outputs its own CPU_ID to the peripheral circuit PRPH through the path (p) of FIG.

  The processing unit CPU_10 reads the spin lock variable area LOCK_FLD through the path (i), but the value of the current unit number CURRENT_CPU_ID is “01”, which is different from “10” of its own CPU_ID. The process (steps S14 and S15) is continued. Similarly, the processing unit CPU_11 reads the spin lock variable area LOCK_FLD through the path (m), but the value of the current unit number CURRENT_CPU_ID is “01”, which is different from “11” of its own CPU_ID. The loop processing (steps S14 and S15) is continued.

  The processing unit CPU_00 executes Line_5 of the program Q following the previous step, returns to the label LOOP_0 of Line_1, and executes the spinlock process of the function spinlock of Line_2. Since the spin lock variable area LOCK_FLD is not the initial value 0x0000, the admic read-modify-write is executed in the paths (q) and (r) of FIG. 12 as the process of step S13 of FIG. The area LOCK_FLD is rewritten as shown in FIG. That is, “00” of its own CPU_ID is registered in the third entry area FIFO_3rd, and 1 is added to the waiting entry number FIFO_LENGTH to make “11”. Thereafter, the processing unit CPU_00 goes through the loop of steps S14 and S15.

  When the processing unit CPU_01 completes the execution of the function print of the Line_3 of the program Q, the processing unit CPU_01 executes the unlock processing of the function unlock of the Line_4 and releases the exclusive access right to the peripheral circuit PRPH, that is, releases the spin lock. The processing unit CPU_01 executes the step S23 of FIG. 5 because the number of waiting entries FIFO_LENGTH is not “0” in the process of the function unlock, and executes the admic read-modify-write through the paths (t) and (u) of FIG. To do. As a result, the contents of the spin lock variable area LOCK_FLD are rewritten as shown in FIG. That is, “10”, which is the value of the first entry area FIFO_1st, is transferred to the current unit number CURRENT_CPU_ID, the waiting order in the FIFO buffer BUFF is incremented by one, and the value “11” of the second entry area FIFO_2nd is transferred. Is shifted to the first entry area FIFO_1st, the value “00” of the third entry area FIFO_3rd is shifted to the second entry area FIFO_2nd, and finally the waiting entry number FIFO_LENGTH value “11” is set to 1. Pull to “10”. The third entry area FIFO_3rd is empty.

  At this time, the processing unit CPU_10 performs the processing of the loop of FIG. 4 (steps S14 and S15) by the spin lock processing, but the current unit number CURRENT_CPU_ID is “10” which is the own CPU_ID of the processing unit CPU_10 by the processing of FIG. Therefore, the processing unit CPU_10 completes the spin lock process and acquires the spin lock. As a result, the processing unit CPU_10 acquires the exclusive access right to the peripheral circuit PRPH, starts the processing of Line_3 of the program Q, and outputs its own CPU_ID to the peripheral circuit PRPH through the path (v) of FIG.

  The processing unit CPU_11 reads the spin lock variable area LOCK_FLD through the path (m), but the value of the current unit number CURRENT_CPU_ID is “10”, which is different from “11” of its own CPU_ID. The process (steps S14 and S15) is continued. Similarly, the processing unit CPU_00 is reading the spin lock variable area LOCK_FLD in the path (s), but the value of the current unit number CURRENT_CPU_ID is “10”, which is different from “00” of its own CPU_ID. The loop processing (steps S14 and S15) is continued.

  The processing unit CPU_01 executes Line_5 of the program Q following the previous step, returns to the label LOOP_0 of Line_1, and executes the spinlock process of the function spinlock of Line_2. Since the spin lock variable area LOCK_FLD is not the initial value 0x0000, the admic read-modify-write is executed in the paths (w) and (x) of FIG. 14 as the process of step S13 of FIG. The area LOCK_FLD is rewritten as shown in FIG. That is, “01” of its own CPU_ID is registered in the third entry area FIFO_3rd, and 1 is added to the number of waiting entries FIFO_LENGTH to make “11”. Thereafter, the processing unit CPU_01 goes through the loop of steps S14 and S15.

  When the processing unit CPU_10 completes the execution of the function print of the Line_3 of the program Q, the processing unit CPU_10 executes the unlock process of the function unlock of the Line_4, and releases the exclusive access right to the peripheral circuit PRPH, that is, releases the spin lock. The processing unit CPU_10 executes the step S23 of FIG. 5 because the number of waiting entries FIFO_LENGTH is not “0” in the process of the function unlock, and executes the admic read-modify-write along the paths (z) and (aa) of FIG. To do. As a result, the contents of the spin lock variable area LOCK_FLD are rewritten as shown in FIG. That is, “11”, which is the value of the first entry area FIFO_1st, is transferred to the current unit number CURRENT_CPU_ID, the waiting order in the FIFO buffer BUFF is incremented by one, and the value “00” of the second entry area FIFO_2nd Is shifted to the first entry area FIFO_1st, the value “01” of the third entry area FIFO_3rd is shifted to the second entry area FIFO_2nd, and finally, the value “11” from the value “11” of the waiting entry number FIFO_LENGTH is changed. Pull to “10”. The third entry area FIFO_3rd is empty.

  At this time, the processing unit CPU_11 performs the processing of the loop of FIG. 4 (steps S14 and S15) by the spin lock processing, but the current unit number CURRENT_CPU_ID is “11” which is the own CPU_ID of the processing unit CPU_11 by the processing of FIG. Therefore, the processing unit CPU_11 completes the spin lock process and acquires the spin lock. As a result, the processing unit CPU_11 acquires the exclusive access right to the peripheral circuit PRPH, starts the processing of Line_3 of the program Q, and outputs its own CPU_ID to the peripheral circuit PRPH through the path (ab) in FIG.

  The processing unit CPU_00 reads the spin lock variable area LOCK_FLD through the path (s), but the value of the current unit number CURRENT_CPU_ID is “11”, which is different from “00” of the own CPU_ID. The process (steps S14 and S15) is continued. Similarly, the processing unit CPU_01 reads the spin lock variable area LOCK_FLD through the path (y), but the value of the current unit number CURRENT_CPU_ID is “11”, which is different from “01” of the own CPU_ID. The loop processing (steps S14 and S15) is continued.

  The processing unit CPU_10 executes Line_5 of the program Q following the previous step, returns to the label LOOP_0 of Line_1, and executes spinlock processing of the function spinlock of Line_2. Since the spin lock variable area LOCK_FLD is not the initial value 0x0000, the admic read-modify-write is executed in the paths (ac) and (ad) of FIG. 16 as the process of step S13 of FIG. The area LOCK_FLD is rewritten as shown in FIG. That is, “10” of its own CPU_ID is registered in the third entry area FIFO_3rd, and 1 is added to the number of waiting entries FIFO_LENGTH to make “11”. Thereafter, the processing unit CPU_10 goes through a loop of steps S14 and S15.

  When the processing unit CPU_11 completes the execution of the function print of the Line_3 of the program Q, the processing unit CPU_11 executes the unlock process of the function unlock of the Line_4, and releases the exclusive access right to the peripheral circuit PRPH, that is, releases the spin lock. The processing unit CPU_11 executes the step S23 of FIG. 5 because the number of waiting entries FIFO_LENGTH is not “0” in the process of the function unlock, and executes the admic read-modify-write along the paths (af) and (ag) of FIG. To do. As a result, the contents of the spin lock variable area LOCK_FLD are rewritten as shown in FIG. That is, “00”, which is the value of the first entry area FIFO_1st, is transferred to the current unit number CURRENT_CPU_ID, the waiting order in the FIFO buffer BUFF is incremented by one, and the value “01” of the second entry area FIFO_2nd Is shifted to the first entry area FIFO_1st, the value “10” of the third entry area FIFO_3rd is shifted to the second entry area FIFO_2nd, and finally the waiting entry number FIFO_LENGTH value “11” is set to 1. Pull to “10”. The third entry area FIFO_3rd is empty.

  At this time, the processing unit CPU_00 performs the processing of the loop of FIG. 4 (steps S14 and S15) by the spin lock processing, but the current unit number CURRENT_CPU_ID is “00” which is the own CPU_ID of the processing unit CPU_00 by the processing of FIG. Therefore, the processing unit CPU_00 completes the spin lock process and acquires the spin lock. As a result, the processing unit CPU_00 acquires the exclusive access right to the peripheral circuit PRPH, starts the processing of Line_3 of the program Q, and outputs its own CPU_ID to the peripheral circuit PRPH through the path (ah) in FIG.

  The processing unit CPU_01 reads the spin lock variable area LOCK_FLD through the path (y), but the value of the current unit number CURRENT_CPU_ID is “00”, which is different from “01” of the own CPU_ID. The process (steps S14 and S15) is continued. Similarly, the processing unit CPU_10 reads the spin lock variable area LOCK_FLD through the path (ae), but the value of the current unit number CURRENT_CPU_ID is “00”, which is different from “10” of the own CPU_ID. The loop processing (steps S14 and S15) is continued.

  The processing unit CPU_11 executes Line_5 of the program Q following the previous step, returns to the label LOOP_0 of Line_1, and executes the spinlock processing of the function spinlock of Line_2. Since the spin lock variable area LOCK_FLD is not the initial value 0x0000, the admic read-modify-write is executed in the paths (ai) and (aj) in FIG. 18 as the processing of step S13 in FIG. The area LOCK_FLD is rewritten as shown in FIG. That is, “11” of its own CPU_ID is registered in the third entry area FIFO_3rd, and 1 is added to the number of waiting entries FIFO_LENGTH to make “11”. Thereafter, the processing unit CPU_10 goes through a loop of steps S14 and S15.

  Thereafter, the same processing is repeated, so that the processing unit CPU_00 acquires the exclusive access right to the peripheral circuit PRPH as described in FIG. 7, and the processing unit CPU_01 is exclusive to the peripheral circuit PRPH as described in FIG. The access right is acquired, the processing unit CPU_10 acquires the exclusive access right to the peripheral circuit PRPH as described in FIG. 14, and the processing unit CPU_11 as the exclusive access right to the peripheral circuit PRPH as described in FIG. 18 so that the processing unit CPU_00 acquires the exclusive access right to the peripheral circuit PRPH as described in FIG. 18, so that the spin locks are transferred in the order in which the processing unit went to acquire the spin lock. Become. The starvation problem is completely eliminated and spinlocks are not distributed in round-robin order based on a predetermined processing core number, so fairness is the order in which multiple processing units went to acquire spinlocks. Spin lock can be acquired.

<< Second Embodiment >>
The data processing system according to the second embodiment is different from the data processing system according to the first embodiment in the configuration of the spin lock variable region LOCK_FLD and the procedure of spin lock processing and unlock processing using the same. Is different. Hereinafter, the difference will be mainly described.

  FIG. 19 illustrates a spin lock variable area LOCK_FLDS used in the data processing system according to the second embodiment. The spin lock variable area LOCK_FLDS is formed in the memory MRY as described above, and is operated by, for example, four processing units CPU_00 to CPU_11.

  The spin lock variable area LOCK_FLDS has, for example, a 32-bit area in total, the ring buffer RING_BUFF (RING_BUFF [0] to RING_BUFF [3]) in bits B31-24, the bottom counter BOTTOM, and bits B9− in bits 17-16. A top counter TOP is assigned to 8, and a lock bit LOCK_BIT is assigned to bit B0.

  The lock bit LOCK_BIT is “1” indicating the acquisition state of the spin lock, and “0” indicates the release state of the lock.

  The ring buffer RING_BUFF has four FIFO stages RING_BUFF [0] to RING_BUFF [3], and is used as a queuing buffer. The top counter TOP and the bottom counter BOTTOM are FIFO stage pointers for causing the ring buffer RING_BUFF to function as a queuing buffer. Although not particularly limited, the initial values of the top counter TOP and the bottom counter BOTOM are “0”, and “0” to “3” are wrapped around. The top counter TOP indicates the first queuing FIFO stage in the ring buffer RING_BUFF (actually its number 0 to 3), and the bottom counter BOTTOM is the last queuing FIFO stage in the ring buffer RING_BUFF (actually its number 0). To 3). The queuing operation of the ring buffer RING_BUFF will be described in detail later. The initial values are both “0”, and the own CPU_ID of the processing unit that acquired the spin lock when the spin lock was first acquired in the lock release state. Is stored in the first FIFO stage RING_BUFF [0], and when another processing unit fails to acquire the spin lock after that, the CPU_ID of the other processing unit is stored in the FIFO stage indicated by the value of the bottom counter BOTTOM incremented by 1. If there is a processing unit waiting for a spin lock in the ring buffer RING_BUFF when storing and releasing the lock (if TOP and BOTTOM are not equal), the value of the top counter TOP is incremented by 1. The processing unit is waiting to acquire a lock to win the spin lock with that CPU_ID pointed to by the top counter TOP matches in their own CPU_ID. The increment calculation method is not particularly limited, but is the remainder when the original counter value is divided by four. That is, TOP = [(TOP + 1) mod4], BOTTOM = [(BOTTOM + 1) mod4]. For example, when TOP = 0, the next TOP is 1, and when TOP = 1, the next TOP is 2. When TOP = 2, the next TOP is 3, and when TOP = 3, the next TOP is 0.

  Next, a specific example of the spin lock control procedure using the spin lock variable region LOCK_FLDS will be described. As described with reference to FIG. 2, the respective processing units CPU_00 to CPU_11 execute the program Q in parallel in order to access the peripheral circuit PRPH which is a common resource. The initialization flow of the spin lock variable area LOCK_FLDS is the same as that described with reference to FIG. 3, and all bits are initialized to “0”.

  FIG. 20 shows a control flow of the spin lock process when the function spinlock is executed. The processing unit that has acquired the bus right reads the spin lock variable area LOCK_FLDS to determine whether it is the initial value. That is, it is determined whether or not the lock bit LOCK_BIT is set to “0” (the spin lock state is released) (S31). When it is determined that the spin lock state is released, its own processing unit ID (own CPU_ID) is stored in the first FIFO stage RING_BUFF [0], and the lock bit LOCK_BIT is rewritten to “1” ( S32), the spin lock state is acquired. When the spin lock state is not released (when acquisition of the spin lock has failed), its own processing unit ID (own CPU_ID) is stored in the FIFO stage indicated by the value of the bottom counter BOTTOM incremented by 1 (S33). Thus, the CPU_ID that first acquired the spin lock is queued in the ring buffer RING_BUFF, and then the processing unit IDs are queued in the order in which the spin lock acquisition failed. Thereafter, the processing unit that has failed to acquire the spin lock waits for the processing ID of the FIFO stage pointed to by the top counter TOP to be matched with its own processing ID (S34, S35). In short, it is registered in the ring buffer RING_BUFF. It is possible to acquire the spin lock after waiting for the order of the person who is present to be updated to the highest order.

  Steps S31, S32, and S33 are atomic processes, and the processing unit does not pass the access right to the spin lock variable area LOCK_FLDS to other processing units until the processes of steps S31, S32, and S33 are completed. The processing units CPU_00 to CPU_11 have a load instruction and a store instruction in an instruction set that can be used to realize such read, modify, and write access as atomic processing.

  FIG. 21 shows a control flow of unlock processing when the function unlock is executed. In the unlocking process, the value of the top counter TOP and the value of the bottom counter BOTTOM are read, and it is determined whether or not there is a processing unit waiting for the acquisition of the spin lock depending on whether the two values match ( If there is nothing waiting, the spin lock variable area LOCK_FLDS is initialized (S42), and the spin lock is released. If there is a waiting processing unit, the value of the top counter TOP is incremented by 1, the waiting order is incremented by 1, and the unlocking process is terminated (S43). By performing the processing in step S43 several times, the value of the top counter TOP is incremented in the direction of the waiting order of the processing units that have failed to acquire the spin lock. As described in step S34, the processing unit waiting for the acquisition of the spin lock can acquire the spin lock when the CPU_ID pointed to by the top counter TOP matches its own CPU_ID.

  As described above, each of the processing units CPU_00 to CPU_11 queues the IDs of the processing units in the ring buffer RING_BUFF in the order of failure when the spin lock acquisition fails, and the queued order of the processing units CPU_00 to CPU_11 is top. The spin lock is acquired after waiting for the counter TOP to be updated (S43) and the acquired spin lock is released. When releasing the acquired spin lock, the top ranks of the respective waiting orders queued in the ring buffer RING_BUFF are topped. By updating the counter TOP (S43), one shifts in the earliest direction to provide an opportunity for acquiring the spin lock by another processing unit. Accordingly, the spin locks are transferred in the order in which the processing unit went to acquire the spin lock. Since the spin locks are not distributed to the processing units in the round robin order based on the predetermined processing unit numbers, the spin locks can be acquired fairly in the order in which the plurality of processing units went to acquire the spin locks.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, it is determined in step 31 of FIG. 20 whether the lock bit LOCK_BIT is in a released state, the registration destination of its own CPU_ID is set according to the value of the top pointer TOP in step S32 of FIG. 20, and the spin lock variable is determined in step 43 of FIG. The initialization target for the area may be only the lock bit LOCK_BIT. Further, the number of processing units is not limited to four and may be any appropriate number. The number of bits in the spin lock variable area and the bit arrangement such as lock bits can be changed as appropriate. The type of shared resource is not limited at all, and may be a memory or the like.

SYS data processing device CPU_00 to CPU_11 Processing unit PRPH Peripheral circuit as a resource (shared resource) MRY memory LOCK_FLD Spin lock variable area BUFF FIFO buffer FIFO_1st to FIFO_3rd entry area CURRENT_CPU_ID Current unit number FIFO_LENTHCK LOCK_LENDLOCK TH CK RING_BUFF ring buffer RING_BUFF [0] to RING_BUFF [3] FIFO stage BOTTOM bottom counter TOP top counter

Claims (14)

A data processing apparatus in which a plurality of processing units that share resources manipulate a spinlock variable area to acquire a spinlock,
The spin lock variable area has a registration area for waiting for spin lock,
The processing unit registers the processing unit names in the waiting order registration area in the order of failure when the spin lock acquisition fails, and the registered order of the processing unit is updated to the first order. A data processing apparatus that waits to acquire a spin lock, and shifts the order of each waiting order registered in the waiting order registration area in the earliest direction when releasing the acquired spin lock. A data processing system having a plurality of processing units, a resource shared by the plurality of processing units, and a spin lock variable area operated by the plurality of processing units,
The spin lock variable area has a lock bit for indicating whether or not the resource can be used, and a waiting area registration area for holding the order of processing units waiting for the resource,
When the processing unit reads the lock bit and detects that the spin lock state is released, the processing unit operates the lock bit to acquire the spin lock state, and reads the lock bit to already spin lock. When it is detected that the state is acquired, the processing unit is registered in the registration area in the waiting order, and the spin lock state is acquired after waiting for it to be advanced first, When releasing the spin lock state acquired by spin lock processing, if there is a processing unit registered in the waiting order registration area and waiting, the waiting order is incremented by one, and if there is no waiting processing unit, the lock bit is operated. Data processing to release the spin lock state and unlock processing Stem.   When the processing unit that performs the spin lock process reads the lock bit and detects that the spin lock state is released, the processing unit operates the lock bit to acquire the spin lock state and reads the lock bit. 3. When it is detected that the spin lock state has already been acquired, the access right to the spin lock variable area is occupied when the processing unit is registered in the waiting registration area. Data processing system.   The data processing system according to claim 3, wherein the processing unit occupies an access right to the spin lock variable area and performs the unlock process.   The data processing system according to claim 2, wherein the processing unit moves up the waiting order by shifting the processing unit name registered in the registration area of the waiting order in one direction. The spin lock variable area further includes a current unit name holding area indicating a processing unit that is currently acquiring the spin lock state,
In the spin lock process, when the lock bit is read and it is detected that the spin lock state is released, the spin lock state is obtained by operating the lock bit, and the current processing unit name is retained. When it is detected that the spin lock state has already been acquired by reading the lock bit and registering the processing unit in the waiting order registration area, It is a process to wait and acquire the spin lock state,
In the unlock process, when the spin lock state acquired in the spin lock process is released, if there is a processing unit that is registered and waiting in the registration area of the waiting order, the waiting process is incremented by one and the earliest processing unit 4. The data processing system according to claim 3, wherein the current unit name holding area is rewritten with a name, and if there is no waiting processing unit, the spin lock variable area is initialized and the spin lock state is released. The spin lock variable area further includes a wait number holding area for holding the number of processing units registered and waiting in the waiting order registration area,
The data processing system according to claim 5, wherein the processing unit determines whether there is a processing unit that is registered in the waiting registration area and is waiting based on the number held in the waiting number holding area. The waiting-order registration area has a number of entry areas corresponding to the number of the plurality of processing units, a first pointer indicating the address of the entry area, and a second pointer indicating the address of the entry area. And
In the spin lock process, when it is detected that the spin lock state is released by reading the lock bit, the spin lock state is obtained by operating the lock bit, and the name of the processing unit is indicated by the first pointer. When the lock bit is read and it is detected that the spin lock state has already been acquired by reading the lock bit, the value of the second pointer is advanced to the entry area pointed to by the value of the second pointer. A process of registering a unit name, waiting for it to be pointed by the first pointer, and acquiring a spin lock state;
The unlock process advances the value of the first pointer if the value of the first pointer is not equal to the value of the second pointer when releasing the spin lock state acquired in the spin lock process, and the processing unit waiting 4. The data processing system according to claim 3, which is a process for initializing a spin lock variable area and releasing a spin lock state if there is not. A data processing method in which a plurality of processing units sharing a resource manipulate a spinlock variable area to acquire a spinlock,
The spinlock variable area has a waiting-order registration area that is a reserved area for spinlock variables;
A data processing method for registering processing unit names in the waiting order registration area in the order of failure when acquisition of a spin lock fails, and causing a processing unit registered for reservation first to acquire the next spin lock. A data processing method in which a plurality of processing units sharing a resource operate a spin lock variable area to perform spin lock processing and unlock processing,
The spin lock variable area has a lock bit for indicating whether or not the resource can be used, and a waiting area registration area for holding the order of processing units waiting for the resource,
In the spin lock process, when the processing unit reads the lock bit and detects that the spin lock state is released, the spin unit operates the lock bit to acquire the spin lock state and reads the lock bit. When it is detected that the spin lock state has already been acquired, the processing unit is registered in the registration area in the waiting order, and the process of acquiring the spin lock state after waiting for it to be advanced first. Yes,
In the unlock process, when the acquired spin lock state is released, if there is a waiting processing unit registered in the waiting order registration area, the waiting order is incremented by one, and if there is no waiting processing unit, the lock bit is set. A data processing method that is a process of operating to release a spin lock state.   In the spin lock process, the processing unit occupies the access right to the spin lock variable area, and operates the lock bit when it detects that the spin lock state is released by reading the lock bit. 11. The process of registering the processing unit in a waiting order registration area is performed when the spin lock state is acquired and the lock bit is read to detect that the spin lock state has already been acquired. Data processing method.   The data processing method according to claim 11, wherein the processing unit occupies an access right to the spin lock variable area and performs the unlock process. A data processing method in which a plurality of processing units sharing a resource operate a spin lock variable area to perform spin lock processing and unlock processing,
The spin lock variable area includes a lock bit for indicating whether or not the resource can be used, a registration area in a waiting order for holding an order of processing units waiting for the resource, and a spin lock state. A current unit name holding area indicating the processing unit currently acquiring
In the spin lock process, when the processing unit reads the lock bit and detects that the spin lock state is released, the spin lock state is manipulated to acquire the spin lock state, and the processing unit name is changed. When recording the current unit name holding area and detecting that the spin lock state has already been acquired by reading the lock bit, the processing unit is registered in the waiting order registration area, It is a process to acquire the spin lock state after waiting for it to be raised,
In the unlock process, when the acquired spin lock state is released, if there is a waiting processing unit registered in the waiting order registration area, the waiting unit is incremented by one and the current unit name is the first processing unit name. A data processing method, which is a process of rewriting a holding area and operating a lock bit to release a spin lock state if there is no processing unit waiting. A data processing method in which a plurality of processing units sharing a resource operate a spin lock variable area to perform spin lock processing and unlock processing,
The spin lock variable area has a lock bit for indicating whether or not the resource can be used, and a waiting area registration area for holding the order of processing units waiting for the resource,
The waiting-order registration area has a number of entry areas corresponding to the number of the plurality of processing units, a first pointer indicating the address of the entry area, and a second pointer indicating the address of the entry area. And
In the spin lock process, when the processing unit reads the lock bit and detects that the spin lock state is released, the spin lock state is manipulated to acquire the spin lock state, and the processing unit name is changed. The entry stored in the entry area pointed to by the first pointer and reading the lock bit and detecting that the spin lock state has already been acquired, advances the value of the second pointer to indicate the entry pointed to by the value of the second pointer Registering the processing unit name in the area, waiting for it to be pointed by the first pointer, and obtaining a spin lock state;
In the unlock process, when the acquired spin lock state is released, the value of the first pointer is advanced if the value of the first pointer is not equal to the value of the second pointer, and the lock bit is set if there is no processing unit waiting. A data processing method that is a process of operating to release a spin lock state.

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