JP2011124597A - Field-effect transistor and method of manufacturing the same - Google Patents

Abstract

An FET that can perform a switching operation with a high withstand voltage and a high current and is easy to manufacture.
A source region (1) of a first conductivity type, a channel region (10) of a first conductivity type, and a second conductivity type for limiting the channel region, which are provided on one main surface of a semiconductor thin body. And a first conductivity type drain region (3) provided on the other main surface, and a first conductivity type drift region (4) continuous in the thickness direction. The impurity concentration of (4) and the channel region (10) is lower than the impurity concentration of the source region (1), the drain region (3) and the limited region (5), and the impurity concentration of the channel region (10) is the drift region ( 4) Impurity concentration is lower.
[Selection] Figure 16

Description

  The present invention relates to a field effect transistor (FET) that performs a high-current, high-voltage switching operation used for DC-AC conversion, inverters, and the like in power transmission.

  A junction field effect transistor (JFET) used for switching of an inverter or the like is required to withstand a high current and a high voltage. FIG. 20 is a diagram showing a normal lateral JFET. A ground potential is applied to the source region 1 and a positive potential is applied to the drain region 3. A pn junction is formed below the gate region 2. When the element is turned off, a negative voltage is applied to the gate electrode 12 so that the junction is in a reverse bias state. The electrons in the source region 1 are attracted to the positive potential of the drain region 3, pass through the channel region 9 below the gate region 2, and reach the drain region 3.

  In the above lateral JFET, as shown in FIG. 20, since the source, gate, and drain electrodes are on the same plane, the drain electrode and the other electrode come close to each other through air. Since the withstand pressure of air is at most 3 kV / mm, when a voltage of 3 kV or more is applied between the drain electrode and another electrode in the OFF state where no current flows, it is necessary to separate the drain electrode from the other electrode by 1 mm or more. was there.

FIG. 21 is a diagram showing a vertical JFET, also known as a static induction transistor (hereinafter referred to as SIT (Static Induction Transistor)), which has been proposed and put into practical use to improve the disadvantages of the lateral JFET. In SIT, a plurality of gate regions 2 are formed with p ⁺ regions into which high-concentration p-type impurities are implanted, and n ⁻ regions to which low-concentration n-type impurities are added are formed around them. . Since the n-type impurity concentration in the n ⁻ region is low, the depletion layer always spreads and the channel region disappears. For this reason, a drain current saturation phenomenon due to pinch-off that occurs in the lateral JFET does not occur. The method of applying potentials in the source, gate, and drain regions is the same as that of the lateral JFET shown in FIG.

  The electrons in the source region 1 exceed the potential barrier in the gate region and are attracted to the drain potential to drift through the depletion layer. When the drain potential is set to a high positive potential, the potential barrier with respect to electrons in the gate region is reduced, and the drift current can be increased. Even if the drain potential is increased, the saturation phenomenon of the drain current does not occur. The drain current is usually controlled by the gate potential and the drain potential.

  When the lateral JFET shown in FIG. 20 is used and the distance between the drain electrode and the other electrode is increased, the length of the channel region 9 from the source region 1 to the drain region 3 becomes longer, and only a slight current can flow. Therefore, the high current generally required for what is called a power transistor could not be passed.

  When the SIT shown in FIG. 21 is used for switching, in order to obtain a large current, it is necessary to increase the voltage in order to cause the electrons to exceed the potential barrier, and even if it is slight, it is avoided that a loss is generated. I couldn't.

  Further, even a JFET structure that can solve the above problem is not actually used if the manufacturing process becomes complicated due to the complicated structure and the manufacturing cost increases. For this reason, after solving said problem, it is necessary to set it as the structure which can be manufactured by a simple manufacturing process.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an FET capable of switching with a high withstand voltage and a high current that operates with a lower loss than the prior art, using the principle of the FET, regardless of the structure of the JFET. Furthermore, another object is to provide an FET that can be easily manufactured while achieving the above-mentioned object. In the following description, “FET” means FET or JFET, and FET and JFET are not distinguished unless otherwise specified.

  The FET of the present invention includes a gate region provided on one main surface of a semiconductor thin body, a first conductivity type source region provided on one main surface side, and a region provided on one main surface. A first conductivity type channel region that is continuous with the source region and the gate region, a second conductivity type limitation region that limits the range of the channel region, and a first region provided on the other main surface of the semiconductor thin body. A drain region of one conductivity type, and a drift region of a first conductivity type continuous in the thickness direction of the semiconductor thin body from the channel region to the drain region. The impurity concentration of the first conductivity type in the drift region and the channel region is lower than the impurity concentration of the first conductivity type in the source region and the drain region and the impurity concentration of the second conductivity type in the limited region.

  With this configuration, a depletion layer is formed from the gate electrode on one main surface toward the channel region by applying a reverse bias voltage to the gate region in the OFF state, and from the source region to the drain region through the channel region and the drift region. It is possible to block the flow of the carrier that heads. In addition, when a high voltage is applied to the drain region in the OFF state, a high reverse bias voltage is applied to the interface between the limited region and the drift region, and a depletion layer is formed from the limited region to the drift region. The pressure resistance performance can be improved. In the ON state, carriers are moved from the source region to the drain region through the channel region and the drift region so that the source region and the gate region are set to substantially the same potential and no depletion layer is formed. The amount of carrier movement, that is, the current is controlled by the drain potential. As the drain potential is increased, the pinch-off potential is reached, the depletion layer extends from the interface between the limited region and the drift region toward the drift region, and the drain current is saturated. Such an operation is essentially different from a conventional vertical JFET in which there is no pinch-off and the drain current is not saturated. The above-described improvement in the withstand voltage performance due to the voltage load on the depletion layer in the OFF state and the saturation phenomenon of the drain current in the ON state when the current flows vertically are the first operations that are possible with the FET of the present invention. . The saturation of the drain current can prevent the FET itself and surrounding elements from being burned out. What should be noted is that in the ON state, there is no obstacle to the flow of carriers in the path from the source region to the drain region, and the on-resistance becomes extremely low. For this reason, power consumption can be further reduced as compared with conventional SIT or the like forcing carriers to pass through the potential barrier in the depletion layer. Here, when the first conductivity type impurity and the second conductivity type impurity are included, the impurity concentration cancels both impurities and indicates the concentration of the remaining dominant impurity unless otherwise specified.

  Further, in the FET of the present invention, the gate region provided on one main surface of the semiconductor thin body overlaps with the channel region and contains an impurity of the first conductivity type, and on the one main surface, It is conducting and the limited region limits the width of the drift region and the source and channel regions.

  With the above configuration, in the ON state, a large drain current can be obtained by applying a low drain voltage while keeping the gate voltage substantially the same as the source voltage. Further, when turning off, a reverse bias voltage is applied to the gate electrode. By applying this reverse bias voltage, it becomes possible to form a depletion layer in the gate region having a low impurity concentration and to block the electron flow. In this FET, the depletion layer is formed long in the direction in which electrons flow, and electrons with high energy do not flow into the gate region (channel region), so that it cannot pass through the depletion layer due to drift. . As a result, ON / OFF control can be performed by forming a depletion layer under the gate region. On the other hand, in SIT, the drain current is controlled by the gate voltage value and the drain voltage value as described above. The present invention and SIT basically differ in this drain current control mechanism. Because of this fundamental difference, the FET of the present invention can further reduce power consumption compared to SIT. Further, when a high voltage is applied to the drain electrode in the OFF state, a depletion layer is formed on the drift region side of the pn junction (interface between the limited region and the drift region) on the drain region side. It is possible to bear a high voltage.

  In the above-described FET, the gate electrode in contact with the gate region forms a Schottky contact with the gate region.

  With this configuration, a depletion layer can be formed in the gate region (channel region) below the gate electrode by applying a reverse bias voltage to the gate electrode. As a result, ON-OFF control can be performed.

  In each of the above FETs, in a situation where it is not easy to apply a potential independently to the limited region, the limited region extends to a region adjacent to the source region on the one main surface, and the source electrode is the source region. And the limited region have the same potential so that they are provided over both.

  By employing the above-described structure, a potential that is convenient for ON-OFF operation can be easily applied without separately providing a wiring, a system, and the like for applying a potential to the limited region.

  In an aspect in which it is important to reliably withstand the high voltage applied to the drain electrode in the OFF state, for example, the drain region has a structure in which the surface inside the semiconductor is covered by a drift region extending in the thickness direction of the semiconductor thin body Is desirable.

  As a result, the depletion layer formed at the interface between the limited region and the drift region on the drain region side covers the drain region entirely inside the semiconductor thin body and does not cause a short circuit locally through a portion having a low breakdown voltage.

  When it is important to limit each side of the drift region by independent electrodes, for example, it is desirable that two or more regions including a source region and a gate region are provided on the one main surface. .

  As a result, separate potentials are applied independently from separate electrodes to each side of the common drift region, the number of semiconductor operation methods is increased, and a desirable potential can be reliably applied to both sides of the drift region. Become.

  In the FET, the gate region includes the second conductivity type impurity, and the limited region further limits the gate region from the inside of the semiconductor thin body when used in the aspect of the present invention where the simplicity of the structure is important. Is enclosed.

  With this configuration, the channel region and the gate region are formed on one main surface, and the limited region is formed so as to surround the gate region from the inside, thereby simplifying the configuration and reducing the number of mask formation steps during manufacturing. Thus, manufacturing is facilitated and yield is improved. In addition, the gate region is conductive including the impurity element having the same conductivity type as that of the limited region, and a depletion layer is extended from the limited region toward the channel region to realize an OFF state. Furthermore, when a high voltage is applied to the drain region in this OFF state, a high reverse bias voltage is applied to the interface between the limited region and the drift region, and a depletion layer is formed from the limited region to the drift region, Since the voltage is borne, the withstand voltage performance can be improved. In the ON state, carriers are moved from the source region to the drain region through the channel region and the drift region so that the source region and the gate region are set to substantially the same potential and no depletion layer is formed. The amount of carrier movement, that is, the current is controlled by the drain potential. As the drain potential is increased, the pinch-off potential is reached, the depletion layer extends from the interface between the limited region and the drift region toward the drift region, and the drain current is saturated. Such an operation is essentially different from a conventional vertical JFET in which there is no pinch-off and the drain current is not saturated. The above-mentioned FET, like the above FET, has improved the breakdown voltage performance due to the voltage load on the depletion layer in the above-mentioned OFF state, and the drain current saturation phenomenon in the ON state when a current flows in the thickness direction of the semiconductor. This is the first operation that is possible. The saturation of the drain current can prevent the FET itself and surrounding elements from being burned out. In the ON state, there is no obstacle to the flow of carriers in the path from the source region to the drain region, and the on-resistance is extremely low as in the above-described FET. For this reason, power consumption can be further reduced as compared with conventional SIT or the like forcing carriers to pass through the potential barrier in the depletion layer.

  In the FET, in the FET described above, the source region is formed so as to protrude on one main surface, and the channel region is formed continuously below the source region.

  With this configuration, the mask used for patterning the source region using dry etching can also be used for implanting the second conductivity type impurity element into the gate region and the limited region surrounding the gate region. As a result, the number of masking steps can be reduced, and mask alignment can be facilitated, thereby improving yield.

  In the FET, the gate region is composed of two regions in the above-described FET, and the channel region is disposed between the two limited regions in contact with the limited region surrounding and limiting each of the two gate regions. ing.

  With this configuration, the structure of the FET is further simplified, mask alignment is facilitated, and the manufacturing man-hours can be reduced and the yield can be improved.

  In the FET, in the FET described above, the gate electrode in contact with the gate region forms an ohmic contact with the gate region.

  With this configuration, an OFF state is realized by projecting a depletion layer from the limited region toward the channel region at the limited region / channel region interface forming the pn junction with high controllability by applying a reverse bias voltage to the gate electrode. It becomes possible. Since the second conductivity type impurity concentration in the gate region is high, it is easy to make an ohmic contact.

  Also in a simple FET having this structure, it is desirable that the n-type impurity concentration in the drift region is higher than the impurity concentration in the channel region. With this concentration configuration, the depletion layer can reliably project toward the channel region by applying a reverse bias voltage to the gate electrode when the OFF state is set. Therefore, the OFF state can be realized reliably and at high speed. Even in the ON state, the depletion layer can be eliminated in a short time, so that high-speed switching is possible. In addition, since the first conductivity type impurity concentration in the drift region is lower than the second conductivity type impurity concentration in the limited region, a depletion layer is formed in the drift region as the reverse bias voltage is increased, and this depletion layer has a breakdown voltage. This contributes to high pressure resistance. When the drain voltage is increased in the ON state, the depletion layer extends from the limited region to the drift region, pinch-off occurs, the drain current is saturated, and troubles such as burning can be avoided.

  The FET manufacturing method of the present invention has a concentration lower than the concentration Cs on a first conductivity type semiconductor substrate (first conductivity type semiconductor substrate having a concentration Cs) containing the first conductivity type impurity having a concentration Cs. Forming a first conductivity type first semiconductor layer of C1, and a first conductivity type first concentration of C2 having a concentration lower than Cs and C1 on the first semiconductor layer of the first conductivity type; A step of forming a second semiconductor layer, and a step of forming a first conductive type third semiconductor layer having a concentration C3 higher than the concentrations C1 and C2 on the first conductive type second semiconductor layer. Including. The manufacturing method further includes a step of removing a first conductive type third semiconductor layer other than the source region by etching using a mask that shields the source region on the first conductive type third semiconductor layer, A step of doping a second conductivity type impurity into the first conductivity type second semiconductor layer on both sides to form a second conductivity type gate region and a second conductivity type limited region having a concentration C4 higher than the concentration C2. With.

  According to this manufacturing method, the number of processes is reduced, and the number of masks is reduced accordingly. Therefore, the mask alignment is simplified and the FET can be easily manufactured. For this reason, a yield improves and it becomes possible to reduce manufacturing cost.

  In addition, in the FET manufacturing method, for example, it is desirable to perform ion implantation in the second conductivity type impurity doping using the mask for etching the first conductivity type third semiconductor layer as it is.

  By this manufacturing method, since etching and ion implantation can be performed with the same mask, the number of steps can be reduced, and a decrease in yield due to misalignment or the like can be avoided. As a result, the manufacturing cost can be reduced.

  According to the FET of the present invention, it is possible to provide an FET that can withstand a high-current, high-voltage switching operation with lower loss than before. Further, since the FET of the present invention has a simple structure, it is easy to manufacture and can be provided at low cost.

FIG. 3 is a configuration cross-sectional view of an FET in the first embodiment. FIG. 2 is a structural cross-sectional view showing a stage in which an n layer is formed on a substrate by a CVD method in manufacturing the FET shown in FIG. 1. FIG. 3 is a configuration cross-sectional view after the step of FIG. 2 in which an n ⁺ region is formed by ion implantation (production method 1). FIG. 4 is a configuration cross-sectional view after forming FIG. 3 and forming a p ⁺ region that becomes a limited region by ion implantation (production method 1). FIG. 3 is a configuration cross-sectional view after forming the p ⁺ region by ion implantation after FIG. 2 (Production Method 2). FIG. 6 is a structural cross-sectional view after the step of FIG. 5 where an n-layer has been grown (production method 2). FIG. 7 is a configuration cross-sectional view after the step of FIG. 6 in which an n ⁺ region is formed by ion implantation (production method 2). FIG. 8 is a configuration cross-sectional view after the step shown in FIG. 7 in which a p ⁺ region is enlarged and formed by ion implantation (production method 2). It is a figure which shows the voltage example of the ON state of FET of FIG. It is a figure which shows the depletion layer formed in a pinch-off state. It is a figure which shows the relationship of drain voltage-drain current. It is a figure which shows the depletion layer formed in an OFF state. It is a figure which shows the depletion layer formed at the time of the high voltage application of an OFF state. FIG. 5 is a diagram showing another example of an FET similar to the FET of the first embodiment. It is a figure which shows the depletion layer formed at the time of the high voltage application of the OFF state of FET of FIG. FIG. 6 is a configuration cross-sectional view of an FET in a second embodiment. FIG. 17 is a cross-sectional view of a stage in which films for forming a source region are stacked in an intermediate manufacturing stage of the FET of FIG. 16. FIG. 18 is a cross-sectional view of a stage in which a source region is patterned by RIE after FIG. 17. FIG. 19 is a cross-sectional view at a stage where an impurity is doped after FIG. 18 to form a gate region and a limited region. It is a figure which shows the conventional horizontal JFET. It is a figure which shows the conventional vertical JFET.

Next, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a structural cross-sectional view showing an FET according to the first embodiment of the present invention. The source electrodes 11a and 11b and the gate electrodes 12a and 12b are provided on one main surface of the semiconductor thin body, and the drain electrode 13 is provided on the other main surface. The limited region 5 defines the width of the drift region 4 and the width and depth of the gate region, extends to one main surface adjacent to the source region, and contacts the source electrode at the main surface. The potential of the limited region may be applied independently of the source potential, but is usually the same potential as the source potential, so that no separate wiring or system is required, as shown in FIG. The source electrode is provided across the source region and the main surface portion of the limited region.

  Further, in FIG. 1, two source electrodes and two gate electrodes are provided so as to sandwich the drain region 4 and the same potential is applied to each of them. However, the electrodes are different from each other in the same kind as long as the operation is not hindered. It is desirable to apply a potential and apply different potentials independently from separate electrodes to each side of the common drift region. As a result, the number of semiconductor operation methods is increased, and a desirable potential can be reliably applied to both sides of the drift region.

  Of course, both the source and the drain may be one electrode. In the case of this one electrode, in FIG. 1, the source and drain electrodes are each one of them on the basis of the position of the drift region 4, and the entire main surface on one side where the source and gate electrodes are removed. Further, it is desirable that the limited region 5 has an extended structure.

  The thin semiconductor body used in the field effect transistor shown in FIG. 1 was increased in thickness by crystal growth on a Si substrate. However, the material of the semiconductor thin body is not limited to Si, and SiC, GaAs, or the like may be used. Rather, SiC is preferred when pursuing pressure resistance.

Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described. First, a substrate having a thickness corresponding to the drain region 3 containing about 10 ¹⁹ pieces / cm ³ of phosphorus (P) as an impurity is prepared. This substrate forms a drain region 3 having an impurity concentration n ⁺ . As shown in FIG. 2, an n layer having a phosphorus concentration of about 10 ¹⁶ atoms / cm ³ is grown on the substrate by a CVD (Chemical Vapor Deposition) method while flowing a carrier gas such as phosphine (PH ₃ ).

  Thereafter, there are two methods for manufacturing the field effect transistor having the structure shown in FIG. 1 (Production Method 1 and Production Method 2).

First, Production Method 1 will be described. As shown in FIG. 3, about 10 ¹⁹ ions / cm ³ of phosphorus as n-type impurities are implanted into the semiconductor substrate at the stage shown in FIG. 2 to form the source regions 1a and 1b. Thereafter, as shown in FIG. 4, a p ⁺ region to be the limited region 5 is formed by ion implantation. Aluminum (Al) is used as the p-type impurity, and its concentration is made an order of magnitude higher than the impurity concentration of the n layer (the manufacturing method 1).

Next, Production Method 2 will be described. In the manufacturing method 2, as shown in FIG. 5, first, aluminum ions are implanted into the semiconductor substrate at the stage shown in FIG. A p ⁺ region is formed. Thereafter, as shown in FIG. 6, an n layer having a P concentration of about 10 ¹⁶ atoms / cm ³ is grown by flowing a carrier gas such as phosphine (PH ₃ ) by CVD. Next, as shown in FIG. 7, about 10 ¹⁹ ions / cm ³ are implanted as n-type impurities in order to form n ⁺ regions to be the source regions 1a and 1b. Next, as shown in FIG. 8, the limited region 5 is extended to the main surface in order to limit the outer portions of the source regions 1a and 1b. The extension of the limited region is performed by implanting aluminum ions outside the source region at a concentration higher by one digit or more than the impurity concentration of the n layer (the manufacturing method 2).

  Thereafter, as shown in FIG. 1, the electrodes 11, 12, and 13 are formed on the respective regions to produce the field effect transistor of the present invention. Here, the gate electrode 12 is provided so as to form a Schottky contact with the gate region 2 (channel region). As described above, since the impurity concentration of this region is low, the Schottky contact can be easily made. Ni is preferable as the electrode material, but other metal films may be used, or a laminate of several kinds of metal films may be used. The source electrode and the drain electrode other than the gate electrode form ohmic contact with each contact region.

  FIG. 9 is a diagram illustrating the source, gate, and drain voltages in the ON state of the field effect transistor shown in FIG. Usually, the source electrode is grounded, and the gate voltage is used in the vicinity of zero, which is substantially the same as the source voltage. In the ON state, electrons pass from the source regions 1a and 1b, which are n-type impurity regions, and the gate regions 2a and 2b to the drain region 3 through the drift region 4 having a length of about 10 μm extending in the thickness direction of the semiconductor thin body 20. To reach. Unlike the narrow channel region directly below the gate region, the drift region refers to a relatively wide region from the gate region to the drain region where charge carriers are attracted to the drain potential and move. The width of the drift region 4 is defined by a limited region 5 which is a p-type impurity region.

  When the gate voltage is used near zero, when the drain voltage is increased to a positive value, the electron current flows through the drift region 4 defined by the limited region 5 which is a p-type impurity region. Since the potential distribution in the drift region 4 increases steeply in the vicinity of the drain region, the electron flow is accelerated and a reverse bias electric field is generated in a portion of the drift region near the gate region. This depletion layer grows as the drain voltage increases, and pinch-off is established when the depletion layer reaches the width of the drift region. When pinch-off occurs, the drain current does not increase even if the drain voltage is increased further, and a constant saturation current is maintained. FIG. 10 is a diagram illustrating a state where pinch-off occurs and the depletion layer 6 is formed in the drift region 4 which is a low impurity concentration region of the pn junction. The electron current is narrowed by the depletion layer 6 and the drain current is saturated.

  FIG. 11 is a diagram illustrating the relationship between the drain current and the drain voltage. If the drain voltage is increased when the gate voltage is near zero, the drain current rises linearly. However, when the drain voltage reaches the pinch-off voltage, as described above, the depletion layer grows from the pn junctions on both sides of the drift region to the drift region side, plugs the drift region, and the drain current is saturated. The slope of the rise of the drain current is larger than that of the conventional field effect transistor. That is, a high current can be obtained with a low drain voltage, and as a result, a large current can be supplied with a smaller loss than in the prior art.

  FIG. 11 also shows an OFF state in which almost no drain current flows when the gate voltage is increased to Vgoff or higher (however, Vgoff is not increased beyond a certain level). In such an OFF state, as shown in FIG. 12, a reverse bias voltage is applied to the Schottky contact portion between the gate electrode 12 and the gate region 2, and the depletion layer 7 is formed in the gate region 2. The depletion layer formed here is long in the direction of the electron flow, and the gate voltage does not exceed Vgoff as described above, so that electrons having high energy flow into the depletion layer. There is nothing. Therefore, a state where the electron flow is blocked by this depletion layer appears.

  In the conventional vertical JFET SIT, as described above, the drain current and base voltage are controlled by the drain voltage and the base voltage, while the field effect transistor of the present invention forms the depletion layer. ON-OFF control is performed depending on whether or not there is. As a result, the field effect transistor of the present invention can reliably control high voltage and high current.

  When a high voltage is applied to the drain when the current is cut off in the OFF state, as shown in FIG. 13, the pn junction that is the interface between the drift region 4 and the limited region 5 near the drain region is used. A depletion layer 8 is formed. Since this depletion layer 8 bears a high voltage, it becomes a field effect transistor excellent in pressure resistance. This depletion layer 8 is formed wider on the low impurity concentration side as the impurity concentration is lower, in the same manner as the above depletion layer is formed. As shown in FIG. 13, even if the voltage is further increased from the state of FIG. 13, the depletion layer 8 still has room for growth on the drain side, so that it can withstand a very high voltage.

  As a result, it goes without saying that the conventional lateral JFET can secure a higher withstand voltage than the conventional vertical JFET. Specifically, the lateral JFET has a source / gate electrode interval of 1 mm and a channel length of 2 mm, whereas the junction field effect transistor of FIG. 1 of the present invention has a channel length of 10 μm, which is 200 for the same drain voltage. It was possible to pass double the current.

  The drain region 3 may have a structure spreading on the surface as shown in FIG. 1, but as shown in FIG. 14, the inner surface side interface located inside the semiconductor substrate is covered by the drift region 4 below the drain electrode. It is good also as a structure. In the case of the drain electrode having the shape shown in FIG. 14, when a high voltage is applied to the drain in the OFF state, the depletion layer 8 that bears the high voltage is formed as shown in FIG.

In addition, a structure in which the drain region 3 has a structure spreading on the surface as shown in FIG. 1 and the drift region 4 has a shape that abuts against the drain region 3 as shown in FIG. 14 is also included in the scope of the present invention. In this case, the limited region 5 and the drain 3 surrounding the drift region 4 are wide outside the drift region 4 and form a p ⁺ / n ⁺ interface. Further, in this case, the p-type impurity concentration of the p ⁺ region which is the limited region 5 is set higher than that shown in FIG. 1 or FIG. 14 to increase the thickness of the drain region 3. As a result, the depletion layer is formed on the drain region side of the interface between the p ⁺ region of the limited region and the n ⁺ region of the drain region and bears a high voltage.

(Embodiment 2)
FIG. 16 is a structural cross-sectional view of the FET according to the second embodiment. In FIG. 16, the source region 1 protrudes on the surface of the semiconductor layer and is formed in a convex shape. For example, 10 ¹⁹ cm ⁻³ is set so as to establish ohmic contact with the source electrode 11 made of Ni, for example. It contains high-concentration n-type impurities that greatly exceed. The channel region 10 includes an n-type impurity at a concentration of, for example, about 1 × 10 ¹⁵ cm ⁻³ and is formed under the source region 1. The gate region 2 contains a p-type impurity, for example, at a concentration of 10 ¹⁹ cm ⁻³ and is formed on the surface immediately below the two gate electrodes 12. The limited region 5 is formed by a certain thickness of the semiconductor thin body so as to surround the gate region 2 and sandwich the channel region 10 from both sides. This limited region 5 contains the same type of p-type impurity as the gate region at the same concentration. The drift region 4 is in contact with the channel region 10 at one end and is limited to the limited region 5 and is formed to extend to the other surface of the semiconductor thin body by a certain thickness so as to extend to the other surface of the semiconductor thin body. This part is in contact with the drain region 3. The drift region 4 contains n-type impurities, for example, about 9 × 10 ¹⁶ cm ⁻³ . A drain region 3 containing an n-type impurity having a high concentration, for example, a concentration greatly exceeding 10 ¹⁹ cm ⁻³ is formed in contact with the drift region 4 and exposed on the other surface. The drain electrode 13 is formed at the position of the other surface facing the source electrode 11 provided on one surface. The electrodes are preferably made of Ni, but may be other metal films or a multilayer film in which several kinds of metal films are laminated. In the second embodiment, the gate electrode, the source electrode, and the drain electrode all form ohmic contacts with the contact regions. The desired impurity concentration in each region is summarized as follows.
Source region 1, drain region 3: n-type impurity >> 1 × 10 ¹⁹ cm ^-3
Channel region 10: n-type impurity = 1 × 10 ¹⁵ cm ⁻³
Drift region 4: n-type impurity = 9 × 10 ¹⁶ cm ⁻³
Limited region 5, gate region 2: n-type impurity >> 1 × 10 ¹⁹ cm ^-3
The FET is turned on and off as follows. First, in the OFF state, a reverse bias voltage is applied to the gate electrode 12 so that a depletion layer protrudes from the pn junction interface between the channel region 10, the gate region 2, and the limited region 5 to the channel region 10. The OFF state is realized when the depletion layer blocks the path cross section toward the other surface in the channel region. When the drain voltage is increased in the OFF state, a depletion layer is generated at the pn junction interface between the limited region 5 and the drift region 4 and protrudes toward the low concentration drift region. Since the depletion layer bears a voltage, the breakdown voltage performance as an element is improved. In the ON state, carriers flow from the channel region 10 to the drain region 3 through the drift region 4. Since there is no resistance that hinders carrier flow in this path, power is hardly consumed. Therefore, the FET shown in FIG. 16 can provide an element with low power consumption and excellent withstand voltage performance as in the FET of the first embodiment. The FET of FIG. 16 in the second embodiment is characterized in that the structure is simple in addition to the above performance. For this reason, it becomes possible to manufacture with a high yield with few processes compared with FET of Embodiment 1. FIG.

Next, a method for manufacturing this FET will be described. First, as shown in FIG. 17, an n-type semiconductor layer 32, an n ⁻ semiconductor layer 33, and an n ⁺ semiconductor layer 34 are sequentially stacked on an n ⁺ type semiconductor substrate 31. Next, as shown in FIG. 18, in order to form the source region 1 by RIE (Reactive Ion Etching), other portions are etched away. Thereafter, as shown in FIG. 19, p-type impurity ions are implanted to form the gate region 2 and the limited region 5. Thereafter, when Ni is stacked as an electrode, the FET shown in FIG. 16 is completed. The electrodes in the second embodiment are provided so that an ohmic contact is formed including the gate electrode. However, since the impurity concentration of the gate region 2 is high, the formation of the ohmic contact is easy.

  According to this manufacturing method, the manufacturing process is simplified and the number of masks is reduced. In addition, since the chance of mask displacement is reduced, the yield can be improved.

(Example corresponding to Embodiment 2)
All of the semiconductor thin bodies and the semiconductor layers stacked thereon were formed of 4H—SiC, and the withstand voltage performance and the ON resistance were measured for FETs having the following dimensions.
Drift region thickness t ₁ = 2.2 μm
Limited region thickness t ₂ = 1 μm
Channel region width = 10 μm
(Measurement result)
Withstand voltage: 380V (when gate voltage is 22V when OFF)
ON resistance: 0.7 mΩ · cm ²
As described above, the FET of the present invention has high breakdown voltage performance and very low ON resistance. Therefore, the high breakdown voltage, low power consumption, and a simple structure can be easily manufactured and the manufacturing cost can be kept low.

  Although the embodiments and examples of the present invention have been described above, the embodiments and examples disclosed above are merely examples, and the scope of the present invention is within these embodiments and examples. It is not limited to. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 source region, 2 gate region, 3 drain region, 4 drift region, 5 limited region, 6 depletion layer formed in a pinch-off state, 7 depletion layer formed in an OFF state, 8 when a high voltage is applied in an OFF state Depletion layer to be formed, 9 channel region of lateral JFET, 10 channel region of FET of the present invention, 11 source electrode, 12 gate electrode, 13 drain electrode, 20 semiconductor thin body.

Claims (6)

A source region of a first conductivity type provided on one main surface side of the semiconductor thin body;
A channel region of a first conductivity type provided on the one main surface and continuing to the source region;
A limited region of a second conductivity type provided on the one main surface and limiting the range of the channel region;
A drain region of a first conductivity type provided on the other main surface of the semiconductor thin body;
A drift region of a first conductivity type that continues from the channel region to the drain region in the thickness direction of the semiconductor thin body;
The impurity concentration of the first conductivity type in the drift region and the channel region is lower than the impurity concentration of the first conductivity type in the source region and the drain region and the impurity concentration of the second conductivity type in the limited region,
A field effect transistor having a first conductivity type impurity concentration in the channel region lower than a first conductivity type impurity concentration in the drift region.   The field effect transistor according to claim 1, wherein the source region is formed so as to protrude above the one main surface, and the channel region is formed continuously below the source region.   The said limited area | region consists of 2 area | regions, The said channel area | region is arrange | positioned between the said 2 area | regions in contact with each of the said 2 area | region which comprises the said limited area | region. Field effect transistor. A gate electrode electrically connected to the limited region;
The field effect transistor according to claim 1, wherein the gate electrode forms an ohmic contact with the limited region. Depositing a first conductivity type first semiconductor layer having a concentration C1 lower than the concentration Cs on a first conductivity type semiconductor substrate containing a first conductivity type impurity having a concentration Cs;
Forming a first conductive type second semiconductor layer having a concentration C2 lower than the concentrations Cs and C1 on the first conductive type first semiconductor layer;
Depositing a first conductivity type third semiconductor layer having a concentration C3 higher than the concentrations C1 and C2 on the second conductivity type second semiconductor layer;
Removing the third semiconductor layer of the first conductivity type other than the source region by etching the third conductivity layer of the first conductivity type using a mask that shields the source region; and
Doping a second conductivity type impurity on the first conductivity type second semiconductor layer on both sides of the source region to form a second conductivity type limited region having a concentration C4 higher than the concentration C2. A method of manufacturing a field effect transistor.   6. The method of manufacturing a field effect transistor according to claim 5, wherein ion implantation for doping the second conductivity type impurity is performed using the mask at the time of etching the third semiconductor layer of the first conductivity type as it is.

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