JP2011123973A - Memory test device and memory test program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and reliably read out a desired file from a memory device in which fail data is stored. <P>SOLUTION: A memory test device for testing a memory chip of a semiconductor wafer in which a plurality of memory chips are formed, includes: a storage device 25 for storing fail data which is a result of testing a memory chip and additional data for specifying a semiconductor wafer of the memory chip as one file for each memory chip; a group processing part 26 for reading out each file from the storage device 25 and creating a group by organizing the files for each semiconductor wafer, based on the additional data of the files read out; and a screen control part 27 for displaying all the created groups on a screen to enable selection of the group and, when the group is selected, displaying the content of the file belonging to the selected group on the screen. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory test apparatus and a memory test program for testing a memory chip.

  Conventionally, a memory tester for testing a memory chip as a semiconductor device has been used. Many memory chips are formed on a semiconductor wafer, and fail data indicating a pass or a fail is created for each cell of the memory chip. The created fail data is stored in a fail memory, and the failure data is read from the fail memory and subjected to various types of failure analysis / analysis. As this type of memory tester, for example, there is a technique disclosed in Patent Document 1.

  FIG. 5 shows an example of a conventional memory tester. The memory tester includes a test unit 101 and an information processing apparatus 102, and the test unit 101 includes a fail memory 111 and a transmission apparatus 112. The test unit 101 performs a test on the memory chip to be tested, generates fail data, and stores it in the fail memory 111. The fail data stored in the fail memory 111 is read by the transmission device 112 and transmitted to the information processing device 102.

  The information processing device 102 is a device that processes and analyzes fail data, and includes a receiving device 121, a logical map data generation unit 122, a physical map data generation unit 123, a storage device 124, a screen control unit 125, and an input device 126. And a display device 127 are schematically configured. The reception device 121 receives the logical map data transmitted from the transmission device 112 and outputs the logical map data to the logical map data generation unit 122.

  The logical map data generation unit 122 generates logical map data. The logical map data includes fail data arranged using logical addresses, and is data in which fail data is arranged on the X coordinate and the Y coordinate for each I / O (Input / Output). The physical map data generation unit 123 converts logical map data into physical map data. The physical map data is data in which fail data is arranged using physical addresses, and the fail data is arranged with the physical addresses as X and Y coordinates. The storage device 124 is a storage device that stores logical map data and physical map data. The screen control unit 125 controls the display content of the display device 127 and displays various information on the screen based on the input content of the input device 126.

JP 2008-282538 A

  Logical map data and physical map data are created for each memory chip. A large number of memory chips are formed on a semiconductor wafer, and the number thereof is several hundred to several thousand. Therefore, a very large number of logical map data and physical map data are generated for one semiconductor wafer. And not only one semiconductor wafer is a test object, but a plurality of semiconductor wafers are a test object. In addition, the reliability of test accuracy is improved by performing the test repeatedly instead of performing the test once for one memory chip.

  Therefore, the number of created logical map data and physical map data is enormous. These data are stored in the storage device 124 as one file for each memory chip. The information processing apparatus 102 analyzes and analyzes the stored data. Therefore, the file to be analyzed / analyzed is read from the storage device 124, and the contents fail data is displayed on the display device 127. For this reason, it is necessary to selectively designate a target fail from among the enormous number of files stored in the storage device 124.

  This specification is normally made based on the file name attached to the file. Therefore, the user searches for the file name of the file to be read from a large number of files and designates the file. At this time, there is a case where not only one file is read, but a plurality of files are collectively read for analysis / analysis. In particular, there is a demand to read the fail data of each memory chip belonging to one semiconductor wafer and analyze the tendency of the semiconductor wafer to fail. In this case, all the files belonging to the desired semiconductor wafer must be selectively extracted from a huge number of files, and the time and labor for designating the files becomes extremely complicated.

  The storage device 124 is mainly an auxiliary storage device such as a hard disk, and the file name attached to the file can be easily changed. The file name may be changed before it is stored in the storage device 124. In such a case, a specific file cannot be selectively read based on the file name.

  Accordingly, an object of the present invention is to easily and reliably read out a desired file from a storage device storing fail data.

  In order to solve the above problems, a memory test apparatus according to claim 1 of the present invention is a memory test apparatus for testing the memory chip of a semiconductor wafer on which a plurality of memory chips are formed, and the test result of the memory chip. The fail data and the additional data for specifying the semiconductor wafer of the memory chip are stored for each memory chip as one file, and each file is read from the storage device, and based on the additional data of the read file A group processing unit that creates a group in which the files are collected for each semiconductor wafer, and all the created groups are displayed on the screen to enable selection of the group. When the group is selected, the selected group is selected. And a screen control unit that displays the contents of the file belonging to the screen on the screen.

  According to this memory test apparatus, a group of files for each semiconductor wafer is displayed on the screen, and all desired files are automatically displayed on the screen simply by selecting this group. The In addition, since grouping is performed based on the contents of the file, not the file name, information for grouping is not lost.

  The memory test apparatus according to claim 2 of the present invention is the memory test apparatus according to claim 1, wherein the additional data further includes test number information indicating the number of tests of the memory chip, and the group processing unit is a semiconductor A group in which the files are collected is created for each wafer and the number of tests.

  According to this memory test apparatus, since the files are grouped based on not only the semiconductor wafer but also the number of tests, the file extraction conditions can be set in more detail.

  The memory test apparatus according to claim 3 of the present invention is the memory test apparatus according to claim 1, wherein the additional data includes one or more other information for specifying the semiconductor wafer in addition to the wafer information. The group processing unit creates a group in which files that match all of the wafer information and the other information are collected.

  According to this memory test apparatus, since a plurality of pieces of information are used to identify semiconductor wafers and grouping is performed only when all pieces of information match, grouping can be performed with high accuracy. Become.

  The memory test apparatus according to claim 4 of the present invention is the memory test apparatus according to claim 3, wherein the storage device includes logical map data in which the fail data is arranged in a logical address and physical map data in which the fail data is arranged in a physical address. The other information includes lot information specifying the type of the memory chip, data size information indicating the data size of the logical map data and the physical map data, and the logical map data or the physical map data. It is data identification information indicating which is the conversion rule information for converting from the logical map data to the physical map data.

  According to this memory test apparatus, lot information, data size information, data identification information, and conversion rule information are used as other information. Based on such information, grouping can be performed with high accuracy.

  A memory test apparatus according to a fifth aspect of the present invention is the memory test apparatus according to the first aspect, further comprising a test condition information storage unit for storing conditions set for performing the test of the memory chip. The additional data is generated from a condition information storage unit.

  According to this memory test apparatus, additional data is generated using test condition information. Predetermined test conditions must be set when testing the memory chips, and it is not necessary to set conditions for grouping by using the set test conditions. Thereby, the additional data can be automatically generated.

  According to a sixth aspect of the present invention, there is provided a memory test program for causing a computer to output 1 fail data, which is a test result of the memory chip of a semiconductor wafer on which a plurality of memory chips are formed, and additional data for specifying the semiconductor wafer of the memory chip. Storage means for storing each file as one file, group processing means for reading each file from the storage means, and creating a group in which the files are grouped for each semiconductor wafer based on the additional data of the read file; As a screen control means for displaying all the created groups on the screen to enable selection of the group and displaying the contents of the files belonging to the selected group on the screen when the group is selected. It is made to function.

  Since the present invention automatically groups files based on the additional data contained in the file, even if a large number of files are stored in the storage device, the target file is automatically Since it is read out, desired data can be easily obtained. In addition, since grouping is performed based on the data in the file, grouping information is not changed, so that grouping can be performed reliably.

It is a block diagram which shows schematic structure of the memory test apparatus of embodiment. It is a block diagram of a group processing unit. It is a block diagram which shows the hard wafer structure of a memory test apparatus. It is a flowchart which shows the flow of the process of embodiment. It is a block diagram which shows schematic structure of the conventional memory test apparatus.

  Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, the memory test apparatus of the present invention includes a test unit 1 and an information processing apparatus 2 and is schematically configured. The test unit 1 inputs a predetermined test signal to the memory chip to perform a test, and the information processing apparatus 2 analyzes and analyzes the test result.

  Many memory chips (not shown) to be tested are formed on a semiconductor wafer (not shown). Assume that the number of memory chips constituting one semiconductor wafer is NM (NM is a natural number), and a total of NW (NW is a natural number) semiconductor wafers are tested. The test unit 1 repeatedly performs a test on each memory chip of the semiconductor wafer, and sets the number of tests for one memory chip to NT (NT is a natural number).

  The test unit 1 includes a fail memory 11 and a transmission device 12 and is schematically configured. The test unit 1 performs a predetermined test on the memory chip to be tested, and obtains the result as fail data that is pass or fail data. The acquired fail data is stored in the fail memory 11. The fail data is a binary signal “1” or “0”, and is binary data. A large number of cells are formed in the memory chip, and pass or fail is determined for each cell. Therefore, the fail data has an information amount with the number of bits equal to or more than the number of cells. The fail data stored in the fail memory 11 is read by the transmission device 12 and transmitted to the information processing device 2.

  The information processing device 2 includes a receiving device 21, a test information storage unit 22, a logical map data generation unit 23, a physical map data generation unit 24, a storage device 25, a group processing unit 26, a screen control unit 27, an input device 28, and a display device 29. And is schematically configured. The reception device 21 outputs the fail data transmitted from the transmission device 12 to the logical map data generation unit 23.

  The test information storage unit 22 stores various types of test information. When testing a memory chip, various conditions for performing the test are set, and the test information storage unit 22 stores the conditions. There are various conditions that can be set. Of these, six pieces of information such as wafer information, number-of-tests information, lot information, data size information, data identification information, and conversion rule information are added from the test information storage unit 22 as additional data. To be acquired. Note that information other than the six pieces of information may be added as additional data.

  The operation of the test unit 1 for testing a memory chip is normally controlled by another device. When the information processing apparatus 2 is applied to the other apparatus, the test information storage unit 22 is provided in the information processing apparatus 2. Therefore, the test information stored in itself can be used as additional data. Of course, when the other apparatus is other than the information processing apparatus 2, the test information is acquired from the test information storage unit provided in the other apparatus.

  Among the six pieces of information, the wafer information is information for specifying which semiconductor wafer was tested. The number-of-tests information is information indicating the number of tests when the memory chip is tested. The lot information is information for specifying the type of the memory chip. The data size information indicates the size of fail data at the X and Y coordinates for each I / O of the logical map data. The data identification information is information for identifying whether it is logical map data or physical map data described later. The conversion rule information is conversion rule information described later.

  The logical map data generation unit 23 generates logical map data (logical fail bitmap data) from the fail data received from the receiving device 21. The logical map data is data in which fail data is arranged at logical addresses, and is data in which fail data is arranged at the X and Y coordinates for each I / O (Input / Output) provided in the memory chip.

  At this time, the logical map data is generated as one file for each memory chip. Then, the logical map data generation unit 23 inputs additional data from the test information storage unit 22, and the logical map data and the additional data are collected as one data to constitute one file. Note that the logical map data is obtained by arranging fail data in logical addresses, and the content of the data is fail data. Further, both the fail data and the additional data are binary data, so the contents of one file are binary data.

  The file generated by the logical map data generation unit 23 is output to the physical map data generation unit 24 and the storage device 25. The physical map data generation unit 24 generates physical map data (physical fail bitmap data) based on the contents of this file. The physical map data is data in which fail data is arranged at physical addresses of X and Y coordinates. This physical map data is obtained by converting the array of fail data of the logical map data into physical addresses, and matches the physical arrangement of the memory chips. This conversion is performed based on the conversion rule information stored in the test information storage unit 22.

  The same conversion rule is applied to memory chips belonging to the same semiconductor wafer. The physical map data is data obtained by converting the address of the logical map data. For the additional data, no special change is made except that the data identification information identifies the physical map data. The contents of the physical map data are fail data, and binary data in which the physical map data and the additional data are combined into one file is generated by the physical map data generation unit 24. This file is generated for each memory chip, and the generated file is stored in the storage device 25.

  The storage device 25 stores logical map data and physical map data. If physical map data is not generated, only logical map data is stored. The storage device 25 is an auxiliary storage device such as a hard disk. In the hard disk, an area other than the system area (for example, MBR (master boot record)) is provided as a data area, and logical map data and physical map data are stored in this data area for each file.

  The data area has a hierarchical structure, and the hierarchy is specified as a directory. A directory can be created in an arbitrary hierarchy in the data area, and a file can be stored in the created directory. When the user creates a desired directory, each file is stored under the directory hierarchy.

  The group processing unit 26 will be described. As shown in FIG. 2, the group processing unit 26 includes a data search unit 31, a group creation unit 32, and a search condition output unit 33. The data search unit 31 reads the file stored in the storage device 25 and searches the contents. Close the file after the search is complete. Files to be read are all files under the specified hierarchy. If another directory exists under the directory hierarchy, the directory is also searched. Then, the data search unit 31 extracts only the additional data from the read file and outputs it to the group creation unit 32.

  The group creation unit 32 performs a grouping process for creating a group of read files based on the extracted additional data. In the grouping process, the read file is grouped for each semiconductor wafer. Further, when the number of tests is a plurality of times, the files are grouped for each semiconductor wafer and the number of tests. Then, the created group is output to the screen control unit 27 in a list format.

  The search condition output unit 33 specifies the search condition of the data search unit 31. As will be described later, the screen control unit 27 selects a group, and outputs a search condition for reading all files belonging to the selected group to the data search unit 31. The search condition is a condition for reading a predetermined file from the storage device 25. For this purpose, the group creation unit 32 stores the relationship between each created group and the files belonging to this group. The group creation unit 32 reads out the relationship from the group creation unit 32 and selects the files belonging to the selected group. It is output to the data search unit 31 as a search condition to be read.

  The screen control unit 27 creates a display screen of the display device 29. The screens created by the screen control unit 27 are mainly two screens. One is a screen (group information display screen) that displays group information in a list format, and the other is a screen (fail data display screen) that displays the fail data of the files belonging to the selected group.

  The group information display screen is a screen displaying the created groups in a list format. When the number of tests is one, information on the semiconductor wafer is displayed on the screen, and when it is a plurality of times, information on the semiconductor wafer and the number of tests is displayed on the screen. The screen control unit 27 performs not only screen creation but also GUI (graphical user interface) processing that can be operated on the display screen. A group displayed in the list by the GUI (a group displayed separately for each semiconductor wafer and the number of tests) can be selected by the input device 28. The group information display screen is a screen that displays list items to the last, and does not display data in the file.

  The fail data display screen displays fail data that is the contents of the group selected on the group information display screen. That is, binary data is displayed on the screen. Since one group may include a plurality of files, binary data of a plurality of memory chips may be displayed on the screen. The additional data may be displayed or may not be displayed.

  The input device 28 becomes an operation unit for a user to perform a desired operation such as a keyboard and a mouse. The display device 29 is a device that displays information based on the control content of the screen control unit 27. For example, a display can be applied. The above is the schematic configuration.

  FIG. 3 shows hardware blocks when the present invention is realized by a computer. As shown in FIG. 3, a CPU 42, a RAM 43, a storage device 25, a display device 29, an input device 28, and a receiving device 21 are connected to a bus 41. Is connected. The CPU 42 realizes the functions of the test information storage unit 22, the logical map data generation unit 23, the physical map data generation unit 24, the group processing unit 26, and the screen control unit 27. The CPU 42 executes a program for realizing the functions stored in the RAM 43. The program stored in the storage device 25 can be read out to the RAM 43.

  Next, the operation will be described. The operation of the present invention is divided into a data storage operation and an information processing operation. The data storage operation is an operation for storing the logical map data and the physical map data (or only the logical map data) in the storage device 25 for each file. The information processing operation is an operation for reading and analyzing and analyzing a file. First, the data storage operation will be described.

  The test unit 1 tests each memory chip on the semiconductor wafer and stores fail data in the fail memory 11. Then, the stored fail data is transmitted to the information processing device 2 by the transmission device 12. The receiving device 21 receives the fail data and outputs it to the logical map data generating unit 23. The logical map data generation unit 23 arranges fail data at logical addresses and bundles them together with additional data into one file. At this time, one file is generated for each memory chip.

  The generated file is stored in the storage device 25 and converted into physical map data by the physical map data generation unit 24 based on a predetermined conversion rule, thereby generating one file. This file is stored in the storage device 25. Normally, conversion to physical map data is performed, but conversion may not be performed. In this case, the process is omitted.

  Each time the test unit 1 generates fail data, files are sequentially stored in the storage device 25. Since one file is generated for one memory chip, the storage device 25 stores a total of NM × NW × NT files. These files are stored according to each of the logical map data and the physical map data. Since a single semiconductor wafer includes a large number (for example, several hundred to several thousand) of memory chips, NM is a very large number. In addition, since the number of semiconductor wafers to be tested and the number of tests are not small, the number of stored files is enormous.

  Thus, the data storage operation is completed. Next is an information processing operation. The flow of the information processing operation is shown in the flowchart of FIG. First, when each file is stored in a predetermined directory in the storage device 25 during the data storage operation, the directory is selected (step S1). If there is no directory selection, step S1 can be omitted.

  Then, the data search unit 31 of the group processing unit 26 reads all the files under the specified directory hierarchy of the storage device 25 one by one (step S2). Then, the contents of the read file are searched to extract only the additional data (step S3). After the extracted additional data is output to the group creation unit 32, the read file is closed (step S4), and the next file is read.

  The group creation unit 32 performs a grouping process based on the extracted additional data (step S5). The read file is grouped by semiconductor wafer and number of tests. When the number of tests is one, the files are grouped for each semiconductor wafer. At this time, the group creation unit 32 stores the relationship between the created group and the file, and outputs information on the files belonging to the group to the search condition output unit 33.

  Here, the grouping process is a process for collecting files in which all six pieces of information of the additional data are matched into one group. The group is not prepared in advance, and when the file is read, if the existing group and all six pieces of information do not match, a new group is created. The created group is a group specified by six pieces of information.

  The group does not exist when the first file is read. Therefore, the group creation unit 32 creates one group based on the additional data of the first file. When the second and subsequent files are read, if there is a match between the six pieces of information of the read file and the six pieces of information of the already created group, the read file is distributed to the matching group. On the other hand, if the six pieces of information do not match all the existing groups, a new group is created.

  The above steps S2 to S6 are performed for all files (step S6). As a result, all files are divided into groups. The grouping process is mainly performed on the basis of a semiconductor wafer. For this purpose, grouping is performed with reference to wafer information in the additional data. Thereby, the grouping process can be performed for each semiconductor wafer, and the tendency of failure can be recognized for each semiconductor wafer.

  Further, when the number of tests is a plurality of times, the grouping process is also performed according to the number of tests. This is because different test results may be obtained for each number of tests, and the tendency of fail may be different even for the same semiconductor wafer. For this reason, the semiconductor wafers and the number of tests are grouped. The grouping process based on the number of tests is performed according to the test number information of the additional data.

  Of the additional information, lot information, data size information, data identification information, and conversion rule information are auxiliary information for specifying a semiconductor wafer. The lot information is information for specifying the type of the memory chip, and it is possible to specify the semiconductor wafer. The data size information is used together with the data identification information. If it is possible to specify whether the data is logical map data or physical map data, the memory chip can be specified by the size of the data, thereby enabling the semiconductor wafer to be specified. Become. Further, since the conversion rule varies depending on each memory chip, it becomes possible to specify a semiconductor wafer.

  Therefore, each file is grouped for each semiconductor wafer based on lot information, data size information, data identification information, and conversion rule information as well as wafer information. In other words, if the semiconductor wafer is the same, all of the wafer information, lot information, data size information, data identification information, and conversion rule information should match. Therefore, the accuracy of grouping is further improved by allocating to the same group only when all these pieces of information match. Here, when all of the wafer information, lot information, data size information, data identification information, and conversion rule information match, the grouping accuracy is improved by dividing into the same group. A group of semiconductor wafers may be specified based only on information.

  The group creation unit 32 causes the screen control unit 27 to output the created group information when grouping is completed for all files. The screen control unit 27 creates a group information display screen based on the group information and displays it on the display device 29 (step S7). The group information display screen displays the items of the created group. That is, the semiconductor wafer and the number of tests are displayed in a list format. The screen control unit 27 can select a group displayed in a list format.

  The user or the like selects an arbitrary group from the groups displayed in the list format on the screen of the display device 29 (step S8). On the screen, not the contents of the file, but simply the group items are displayed in a list format, so the target group can be easily found. Then, the screen control unit 27 recognizes the selected group. Information on the selected group is output to the search condition output unit 33.

  The search condition output unit 33 acquires information on files belonging to the selected group from the group creation unit 32. For this purpose, the group creation unit 32 stores the relationship between the group when the grouping process is performed and the files belonging to this group. Based on this, the search condition output unit 33 controls the data search unit 31 to read out a file belonging to the selected group. The data search unit 31 reads all the specified files from the storage device 25 (step S9).

  The read file is output to the screen control unit 27. The screen control unit 27 displays fail data, which is data of the contents of the file, on the screen of the display device 29 in a binary format (step S10). When there are a plurality of files in the group, for example, the screen is divided into the number of files, and the fail data is displayed on the divided screen.

  As described above, target information can be displayed on the screen, and analysis / analysis can be performed based on this information. A user or the like can display fail data of a plurality of memory chips formed on a semiconductor wafer on one screen, and can analyze / analyze a failure tendency or the like for each semiconductor wafer. At this time, even if a large number of files stored in the storage device 25 are not designated and read out, it is possible to automatically select fail data by simply selecting a group item from a list displayed on the screen. It can be displayed.

  In addition, grouping is performed based on the additional data that is the contents of the file, not the file name. The file name can be easily changed, but the contents of the file are basically not changed. Therefore, the additional data is not changed, and the group can be specified reliably. In addition, since additional data is generated using test information that is always set for testing memory chips, grouping is performed automatically without setting special conditions for grouping. Processing is performed. Therefore, it becomes possible to largely omit the trouble of the user or the like.

DESCRIPTION OF SYMBOLS 1 Test unit 2 Information processing apparatus 11 Fail memory 22 Test information storage part 23 Logical map data generation part 24 Physical map data generation part 25 Storage apparatus 26 Group processing part 27 Screen control part 28 Input device 29 Display apparatus 31 Data search part 32 Group Creation part 33 Search condition output part

Claims (6)

A memory test apparatus for testing the memory chip of a semiconductor wafer on which a plurality of memory chips are formed,
A storage device that stores, for each memory chip, fail data that is a test result of the memory chip and additional data that identifies a semiconductor wafer of the memory chip as one file;
A group processing unit that reads each file from the storage device and creates a group in which the files are grouped for each semiconductor wafer based on the additional data of the read file;
A screen control unit that displays all the created groups on the screen to enable selection of the group, and displays the contents of the files belonging to the selected group on the screen when the group is selected;
A memory test apparatus comprising: The additional data further includes test number information indicating the number of tests of the memory chip,
The memory test apparatus according to claim 1, wherein the group processing unit creates a group in which the files are collected for each semiconductor wafer and the number of tests. The additional data has one or more other information for specifying the semiconductor wafer in addition to the wafer information,
The memory test apparatus according to claim 1, wherein the group processing unit creates a group in which files in which the wafer information and the other information all match are collected. The storage device stores logical map data in which the fail data is arranged in logical addresses and physical map data in which physical addresses are arranged,
Whether the other information is lot information specifying the type of the memory chip, data size information indicating the data size of the logical map data and the physical map data, the logical map data, or the physical map data. 4. The memory test apparatus according to claim 3, wherein the data test information is conversion rule information for converting the logical map data into the physical map data. A test condition information storage unit for storing conditions set for testing the memory chip;
The memory test apparatus according to claim 1, wherein the additional data is generated from the test condition information storage unit. Computer
Storage means for storing, for each memory chip, fail data that is a test result of the memory chip of the semiconductor wafer on which a plurality of memory chips are formed and additional data that identifies the semiconductor wafer of the memory chip as one file;
Group processing means for reading each file from the storage means and creating a group in which the files are grouped for each semiconductor wafer based on the additional data of the read file;
Screen control means for displaying all created groups on the screen to enable selection of the group, and displaying the contents of the files belonging to the selected group on the screen when the group is selected;
A memory test program characterized in that it is made to function.

Images