JP2011120059A - Clock abnormality detection system - Google Patents

Abstract

The present invention provides a clock abnormality detection system that prevents malfunction of a system due to an abnormal operation of a clock by detecting an abnormal operation of the clock using serial communication.
A receiver 2 of a clock abnormality detection system periodically reads a signal received from serial communication (start-stop synchronization) transmitted from a transmitter 1, and the bit value read immediately after each bit break is If it is different from the bit value read immediately before the next break, the clock abnormality detection device 23 determines that the clock is abnormal and outputs an alarm.
[Selection] Figure 1

Description

  The present invention relates to a clock abnormality detection system that accepts serial communication from an external device and detects an abnormal operation of a clock based on the communication.

  A clock is a periodic signal used to synchronize a plurality of electronic circuits when a computer or a digital circuit operates. If the clock operates abnormally, the electronic circuit may not be synchronized and may cause an unexpected malfunction. Therefore, a clock abnormality detection system for diagnosing whether the clock operation is normal is necessary.

  For example, in a conventional abnormality detection system in an optical disk recording / reproducing apparatus, a clock abnormality is detected by comparing the frequency of a wobble signal used in an optical disk with a clock frequency. A wobble signal refers to a signal resulting from a change in the intensity of reflected light from a minute groove having a predetermined amplitude and period provided on an optical disc. The frequency of the wobble signal is used as a carrier wave for reading data from the optical disk.

  In the conventional method, the value obtained by counting the period of the wobble signal detected from the optical disk by the clock signal is compared with the value obtained by counting the period when the wobble signal is normally obtained. If there is a difference between the two, it is determined that the wobble signal frequency is abnormal or the clock operation is abnormal.

  Further, for example, Patent Document 1 discloses a technique for determining a clock abnormality if a communication completion time is different from a normal communication completion time in a serial input circuit, and Patent Document 2 discloses a period of a received signal. Is counted with the clock signal, and if the count value deviates from the count value in the normal state, it is determined that the clock is abnormal. If the count number is extremely small, the received signal is regarded as being affected by noise and the clock is not abnormal. Technology is disclosed.

  Further, Patent Document 3 discloses a case where a plurality of digital data converted by an AD converter are acquired until one external clock period elapses, and even if the acquired digital data is different from one another. A technique for determining that the AD converter has failed (failure of the AD converter due to disconnection of the clock line) is disclosed.

JP 2002-27016 A JP 2000-2222829 A JP 2000-236388 A

  Since the above-described system is an optical disk recording / reproducing apparatus, a wobble signal can be used. However, in a general environment, there is a problem that a signal having a predetermined amplitude and period cannot be obtained like a wobble signal.

  The above-described system can also use serial communication instead of the wobble signal. However, since the amplitude and cycle are predetermined, the transmitter needs to transmit a test signal for diagnosis. Further, the conventional method has a problem that when communication noise is superimposed on a signal, the period of the received signal is erroneously counted, and it is erroneously determined that the clock operation is abnormal.

  In view of the above problems, the present invention is a system that detects a clock abnormality by accepting serial communication from an external device even in an environment where a signal having a predetermined amplitude and period cannot be obtained, and noise is superimposed on the communication. Even in such a case, an object of the present invention is to provide a clock abnormality detection system that determines the influence of noise and the influence of clock abnormal operation.

  The clock abnormality refers to a state where the clock operates at a speed higher or lower than a predetermined clock operating speed at normal time.

  In order to achieve the above object, a first feature of the present invention is a clock abnormality detection that detects a clock abnormality by comparing a clock generation device, a serial communication reception device, and a received serial communication cycle with a clock cycle. The gist of the present invention is a clock abnormality detection system having a device.

  Further, the clock abnormality detection device has a noise identification function for identifying the influence of communication noise and clock abnormality by analyzing the tendency of occurrence of the detected abnormality.

  According to the present invention, a clock abnormality can be detected by accepting serial communication from an external device even in an environment where a signal having a predetermined amplitude and period cannot be obtained. Even when noise is superimposed on serial communication, the influence of noise and the influence of abnormal clock operation can be identified.

1 is a diagram showing an example of the configuration of a clock abnormality detection system according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a configuration of a clock abnormality detection system according to a second embodiment of the present invention (a configuration in which a plurality of transmitters are used and an abnormal clock specifying device is added to the configuration illustrated in FIG. 1). FIG. 3 is a flowchart showing a procedure until a warning is output when a clock abnormality is detected by the receiver in the first and second embodiments of the present invention. FIG. 4 is a flowchart showing a procedure until a warning is output when a clock abnormality is detected by the receiver according to the first and second embodiments of the present invention. In addition to the procedure of FIG. 3, a process for identifying the cause of the mismatch (clock abnormality or communication noise) based on the tendency of the location where the bit value mismatch occurred. FIG. 5 is a flowchart showing a procedure until a warning is output when a clock abnormality is detected by the receiver according to the first and second embodiments of the present invention. In addition to the procedure shown in FIG. 4, a process for identifying a clock in which an abnormality has occurred is performed based on the failure occurrence rate of the transmitter / receiver that performed serial communication. FIG. 6 is a diagram showing the timing of reading the received signal in the first and second embodiments of the present invention. In addition, it shows a state in which the received signal is correctly read by synchronizing the transmitter clock and the receiver clock. FIG. 7 is a diagram showing the timing of reading the received signal in the first and second embodiments of the present invention. Since the receiver clock operates faster than the transmitter clock, the bit values read before and after the bit value separation are shown to be inconsistent. FIG. 8 is a diagram showing the timing of reading the received signal in the first and second embodiments of the present invention. Since the receiver clock operates slower than the transmitter clock, the bit values read before and after the bit value separation are shown to be inconsistent. FIG. 9 is a diagram showing the timing of reading the received signal in the first and second embodiments of the present invention. Although the transmitter clock and the receiver clock are operating at the same speed, the bit values read before and after the bit value separation are not matched due to communication noise. FIG. 10 is a diagram showing the timing of reading the received signal in the first and second embodiments of the present invention. It shows how the reading range is changed in consideration of the allowable error range of the clock operation.

  Embodiments of the present invention will be described below with reference to the drawings. However, it should be noted that the drawings are schematic.

  FIG. 1 shows the configuration of this embodiment. In the present embodiment, a transmitter 1 that transmits serial communication and a receiver 2 that receives serial communication transmitted from the transmitter 1 via the network 3 and detects clock abnormality are used. The transmitter 1 includes a clock generator 11 and a serial communication transmitter 12. The receiver 2 includes a clock generator 21, a serial communication receiver 22 for receiving serial communication sent from the serial communication device 12, and a clock abnormality detection device for detecting a clock abnormality based on serial communication reception data. 23.

  The serial communication based on start-stop synchronization will be described with reference to FIG. When transmitting / receiving data, the transmitter 1 continuously transmits stop bits when there is no information. Before the information transmission, 1 bit of the start bit is transmitted, then 7 to 8 bits of data and 1 bit of the parity bit are transmitted, and finally 1 to 2 bits of the stop bit are transmitted.

  The start bit value is defined as 0, and the stop bit is defined as 1. The transmitter 1 transmits each bit at regular intervals. At this time, the transmission cycle is measured using the clock generator 11 of the transmitter 1. Similarly, the receiver 2 uses the clock generator 21 to read the received signal at predetermined intervals and receive the signal as a bit string.

  In the following, a clock abnormality detection system in the case of performing serial communication using start-stop synchronization will be described, but it can be similarly implemented in clock synchronous serial communication. In the case of clock synchronous serial communication, a clock signal that repeats 0 and 1 at a constant cycle is sent separately from the data signal. Therefore, a clock abnormality detection system similar to the system described below is configured by using this clock signal as a reception signal.

  Next, the clock abnormality detection operation will be described with reference to FIG. A flowchart of the detection processing procedure is shown in FIG. Hereinafter, the cycle per bit of received data is referred to as a basic cycle. The received signal is constant during the basic period, and there is a break between bit values for each period. Since the received signal is created by the transmitter, the break position is determined by the clock generator 11 of the transmitter 1, and the timing for reading the received signal is determined by the clock generator 21 of the receiver 2.

  The serial communication receiver 22 receives the serial communication transmitted from the serial communication transmitter 12 of the transmitter (S300).

  When the receiver 2 detects the fall of the received signal, it recognizes the time at that time as the start time of the start bit, and each bit transmitted for each basic period based on the clock generated by its own clock generator 21. The received signals before and after the break are read and the bit values are recorded (S301).

  The serial communication receiving device 22 stops reading after reading the stop bit, and sends the read bit value to the clock abnormality detecting device 23. If the stop bit is 0, a framing error occurs. Even in this case, the read bit value is sent to the clock abnormality detection device 23. The clock abnormality detection device 23 checks the bit value immediately after the break position (S302).

  When the bit values immediately before the delimiter position after one basic cycle coincide with each other, it is determined that there is no clock abnormality, and the diagnosis is performed again after a predetermined time has elapsed. If the bit values do not match, it is determined that the clock is abnormal (S303), and an alarm is output.

  Since the bit value originally does not change from one bit break position to the next, the bit value before and after the break position is not determined to be abnormal. However, the fact that the bit value changes before and after the delimiter position means that the delimiter position obtained by the clock pulse generator 21 on the receiver side is the actual position because the clock on the transmitter side and the receiver side are shifted. It is estimated that the received signal deviates from the delimiter position. Therefore, the clock abnormality can be detected by verifying the match of the bit values.

  The timing for reading the received signal may be determined according to an allowable range of clock deviation allowed by the system using the clock. FIG. 10 shows the read timing when the read timing is determined in accordance with the system clock error allowable range.

  In FIG. 10, when the basic period is T seconds and the allowable error range of the clock is ± E percent, the shortest period within the allowable error range is S seconds and the longest period is L seconds. At this time, S = T × (1−E / 100) and L = T × (1 + E / 100).

  When performing the clock abnormality detection process, after waiting for S seconds after detecting the start bit, the reception signal is read for LS seconds. If a bit break is detected in the received signal during reading, the process waits for S seconds from the detected time, and then reads the received signal for L-S seconds to try to detect the break.

  The bit value break is defined as the place where the bit value changes for the first time after the reception signal is read. If the same bit value continues and no bit break is detected, reading of the received signal is started after S seconds from the time when reading of the received signal was last started, and L from the time when reading of the received signal was finished last. Reads up to seconds later and tries to detect breaks. Thereafter, the same processing is performed until the stop bit is read.

  The clock abnormality detection device 23 may determine the clock abnormality based on the tendency that the bit values do not match. The mismatch of the bit values can be seen not only when an abnormality occurs in the clock operation but also at a location where communication noise occurs.

  However, the location where the bit value mismatch occurs depends on the factor. When communication noise is the cause, the bit values are mismatched only at the location where the noise is generated, whereas when the clock is abnormal, the deviation of the delimiter positions is accumulated, so that bit value mismatch occurs at a plurality of locations.

  Therefore, an alarm may be output after identifying communication noise and clock abnormality based on the tendency of the bit value mismatch. FIG. 4 shows a flowchart of the processing procedure to which this processing is added.

  The serial communication receiver 22 receives the serial communication transmitted from the serial communication transmitter 12 of the transmitter (S400). After reading the start bit included at the beginning of the received signal, based on the clock generated by its own clock generator 21, the received signal before and after the break of each bit transmitted for each basic period is read and its bit value Is recorded (S401).

  The serial communication receiving device 22 stops reading after reading the stop bit, and sends the read bit value to the clock abnormality detecting device 23. The clock abnormality detection device 23 checks the bit value immediately after the delimiter position, and records a portion that does not match the bit value immediately before the delimiter position after one basic period (S402).

  If all the bit values match, it is determined that there is no clock abnormality, and the diagnosis is performed again after a predetermined time (S403).

  If a location that does not match is detected, the cause of the mismatch is identified based on the state of the communication channel (bit error rate, etc.) when the received signal is sent (S404).

  When communication noise is estimated, it is determined that there is no clock abnormality, and diagnosis is performed again after a predetermined time. Otherwise, it is determined that the clock is abnormal, and an alarm is output (S405).

  FIG. 7 shows an example of the occurrence of mismatch when the clock is abnormal and operates at a higher speed than normal, FIG. 8 shows an example of the operation at low speed, and FIG. 9 shows an example of the occurrence of mismatch due to communication noise.

  Compared to the case where communication noise causes bit mismatch, the probability of multiple occurrences of bit mismatch in the case of clock anomalies is clearly higher, so statistical analysis such as Bayesian estimation and data mining By using this method, it is possible to specify the cause of the mismatch with high accuracy.

The clock abnormality detection device 23 checks parity bits added to received data, ECC (Error Correcting Code), CRC (Cyclic Redundancy) in order to identify communication noise.
A communication error detection method such as “Check” may be used to check whether the received data includes a communication error.

  The clock abnormality detection device 23 may use only received data that does not include a bit error based on the result of error correction for clock abnormality detection.

  Further, the bit error rate may be measured according to a communication environment such as a plurality of transmitters, communication locations, communication time zones, and the like, and whether or not abnormality detection is necessary or whether alarm output is necessary may be determined according to the bit error rate. For example, in an environment with a high bit error rate (a lot of communication noise), it may be determined that the detection accuracy of clock abnormality detection is low, and the received data at that time may be selected not to be used for abnormality detection.

  The clock abnormality detection device 23 may determine that the clock is abnormal when a communication error of a predetermined number of times or more is detected in the processing for checking the communication error. That is, in the method described above, two or more places before and after each bit break are read, but each bit is read once at a predetermined timing to check whether a received signal contains a communication error, and a clock error is determined. May be.

  Similarly to the method described above, the timing for reading the received signal may be determined according to the allowable range of clock deviation allowed by the system using the clock. At this time, in order to identify the cause of the communication error, information regarding the bit location where the communication error has occurred may be used.

  There are two possible causes of communication errors: communication noise and clock anomalies. If the cause is communication noise, errors can occur equally for any bit in the received bit string.

  On the other hand, when the clock error is the cause, the synchronization between the received signal and the clock generator 21 on the receiving side is cumulatively shifted, so the probability that an error will occur at the first received start bit is the lowest, and the higher the bit behind. Become. Therefore, it is possible to specify the cause of communication error with high accuracy by using a statistical method based on the location of the bit where the error has occurred.

  In the second embodiment, it is possible to specify a bit mismatch cause and a clock abnormality occurrence source by majority vote based on received signals by serial communication from a plurality of transmitters. Signals are received from a plurality of transmitters using independent clock generators, and the deviation is verified, and an abnormal clock can be identified by majority vote. The apparatus configuration in this case is shown in FIG.

  For example, when the receiver receives signals from the transmitter 1a and the transmitter 1b and verifies the clock shift, no clock abnormality is detected from the signal of the transmitter 1a, but abnormality is detected from the signal 1b. think of. In this case, the clocks of the transmitter 1a and the receiver are the same speed, and it is determined that only the transmitter 1b has a different speed. Therefore, it can be determined that the clock of the transmitter 1b is abnormal by majority vote.

  Further, when a clock abnormality is detected from both signals of the transmitters 1a and 1b, it can be determined that the clock is abnormal in the receiver. When the receiver 2 receives serial communication from the plurality of transmitters 1a, 1b,..., The clock abnormality detection device 23 performs clock abnormality detection using each communication. Based on the result, the abnormal clock specifying device 24 specifies the clock in which an abnormality has occurred by majority vote.

  In the above system, it is assumed that the failure rate of each clock generator is the same. However, if the failure rate is different for each clock, the clock where the abnormality occurred is identified based on the failure rate of that clock. Also good.

  For example, it is assumed that the failure occurrence probability of the clock generator 11 of the transmitter 1 is very small compared to the receiver 2. In this case, when the receiver 2 detects a clock abnormality using communication from the transmitter 1, the receiver 2 can determine that the probability that the clock generator 21 of the receiver 2 has failed is high.

  Even when majority voting is performed using a plurality of transmitters, an abnormal clock may be specified by weighting evaluation based on the failure occurrence rate. FIG. 5 shows a flowchart of clock abnormality detection when the evaluation is weighted based on the failure occurrence rate.

  The procedure (S500 to S505) until the clock abnormality is detected is the same as that in the first embodiment. When an abnormality is detected, the evaluation is weighted based on the failure occurrence rate of each clock (S506), and the clock in which the abnormality has occurred is specified (S507).

  If the clock is not specified, serial communication sent from a single transmitter or a plurality of transmitters is continuously received to detect a clock abnormality. When an abnormal clock is specified, an alarm is output. In this case, the alarm may include information on a clock in which an abnormality has occurred.

  In order to calculate the failure occurrence rate used when specifying the abnormally operating clock by the abnormal clock specifying device 24, the number and frequency of alarms generated by the past clock abnormality detection may be recorded as a history. The history may be recorded individually by each receiver, or all alarms output by each receiver may be centrally managed. The failure occurrence rate of the clock generator may be a value guaranteed by the manufacturer that manufactured the device as an index.

  In control systems where safety is important, such as train control systems, car controls, and elevator controls, it is possible to safely stop the system even if an abnormality occurs, by detecting the abnormal operation of the clock used inside the system with high accuracy. Or it can be restored.

DESCRIPTION OF SYMBOLS 1 Transmitter 2 Receiver 3 Network 11 Clock generator 12 Serial communication transmitter 21 Clock generator 22 Serial communication receiver 23 Clock abnormality detection device 24 Abnormal clock identification device S300 Serial communication reception procedure S301 Received signal reading procedure S302 Bit value coincidence Verification procedure S303 Bit value mismatch verification procedure S400 Serial communication reception procedure S401 Received signal reading procedure S402 Bit value match verification procedure S403 Bit value mismatch verification procedure S404 Bit value mismatch generation factor identification procedure S405 Clock error presence verification procedure S500 Serial communication reception procedure S501 Reception signal reading procedure S502 Bit value match verification procedure S503 Bit value mismatch verification procedure S504 Bit value mismatch occurrence factor identification procedure S505 Clock error presence verification procedure Order S506 Evaluation Weighting Procedure Based on Failure Incidence Rate S507 Abnormal Clock Specific Availability Verification Procedure

Claims (6)

In a clock abnormality detection system composed of one or more transmitters that transmit serial communication, a receiver that receives serial communication, and a network,
The transmitter has a serial communication transmitter for serial communication with other receivers and a clock generator for generating a clock for generating a transmission signal by serial communication,
The receiver includes: a serial communication receiver for receiving the serial communication; a clock generator for generating a clock for determining the timing for reading the serial communication; and a received signal received by the serial communication receiver If a signal is read before and after the basic period break of each bit, and the bit value read immediately after the break of the basic period of each bit does not match the bit value read immediately before the break of the next basic period, a clock error And a clock abnormality detection device that outputs a warning upon determination. The clock abnormality detection system according to claim 1,
The clock anomaly detection device identifies the cause of the mismatch based on the tendency of the mismatch and the characteristics of the communication environment when the bit values do not match before and after the division of the basic period, and the communication noise causes When it is estimated that the clock is abnormal, the clock abnormality detection system has a function of judging that the clock is normal and not outputting an alarm. In the clock abnormality detection system according to claim 1 or 2,
The serial communication receiver has a function of determining a timing for reading a received signal based on an error range of a clock allowed by an external system using the clock generator. The clock abnormality detection system according to any one of claims 1 to 3,
What is claimed is: 1. A clock abnormality detection system comprising: an abnormal clock identifying device that identifies a clock in which an abnormality has occurred based on serial communication received from a plurality of transmitters by majority. The clock abnormality detection system according to any one of claims 1 to 4,
The abnormal clock identification device has a function of identifying a clock in which an abnormality has occurred by weighting the evaluation of each clock based on the failure occurrence rate of each clock. The clock abnormality detection system according to any one of claims 1 to 5,
It has a clock abnormality detection device that reads a bit value included in a reception signal received by the serial communication reception device, and determines that the clock is not abnormal when the communication value is abnormal, and does not output an alarm. Clock anomaly detection system.

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