JP2011096337A - Semiconductor memory device and method for testing semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an increase in current consumption during a stress test. <P>SOLUTION: A semiconductor memory device includes: a local IO line LIO and a main IO line MIO to be used for input and output of data to and from a memory cell, with one end connected to each other; a circuit block VBLPBF which applies a voltage having a VDL level to the other end of the local IO line LIO in a first test mode; and a circuit block WAMP which applies a voltage having a VDD level to the other end of the main IO line MIO in a second test mode. The semiconductor memory device includes a circuit block BLEQCT which outputs a control signal BLEQ' having different voltage levels depending on the first and second test modes, and a transfer gate which limits the value of a current flowing through the local IO line LIO and the main IO line MIO, in the first and second test mode, based on the control signal BLEQ'. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a method for testing a semiconductor memory device.

  Generally, a semiconductor memory device includes a memory cell, and a local IO line and a main IO line that are connected to each other and input / output data to / from the memory cell.

  In such a semiconductor memory device manufacturing process, in order to ensure reliability, a stress application test is performed to operate the semiconductor memory device in a wafer state by applying a stress voltage higher than the usage conditions during normal operation. Is called. In this stress application test, a stress voltage is applied to each part of the semiconductor memory device.

  However, in the wafer state, the main IO line is precharged to the VDD level that is the external power supply voltage, and therefore, in reality, no stress voltage is applied to the main IO line.

  Patent Document 1 describes a semiconductor memory device capable of applying a stress voltage to a main IO line.

  The semiconductor memory device described in Patent Document 1 includes a circuit block DMIP, a circuit block WTB1, a circuit block BLEQ, and a circuit block DMAB shown in FIG.

  The circuit block DMIP shown in FIG. 3A receives signals MIOBij, MIOTij and the like from the main IO line and outputs signals MIOBij, MIOTij and the like.

  In the circuit block WTB1 shown in FIG. 3B, signals TAIOS and TAIOSB are newly input as test signals, and signals MIDBij, MIPTij, MIDTij, MIPBij, and the like are output.

  In the circuit block BLEQ shown in FIG. 3C, signals TAIOS and TAIOSB are newly input as test signals, and a signal PREBLEQMNHP or the like is output.

  Returning to FIG. 3A, the circuit block DMAB receives the signals output from the circuit block DMIP, the circuit block WTB1, and the circuit block BLEQ, the signals MATRipB, MAPCipB, MAQEip, TPARAIO, and the like, and outputs the signals NMAQijB, TMAQijT, etc. To do.

  In such a configuration, the semiconductor memory device described in Patent Document 1 connects the local IO line and the main IO line precharged to the VDL level, which is the write voltage to the memory cell, and then uses the signal TAIOS = High. The main IO line is connected to the ground (GND), and a DC stress voltage is applied to the main IO line. Further, a DC stress voltage is applied to the local IO line by the signal TAIOS = High.

JP 2001-143497 A

  However, the inventors of the present invention have clarified that the semiconductor memory device described in Patent Document 1 has a problem that the current consumption during the stress application test increases. In other words, the semiconductor memory device described in Patent Document 1 connects the local IO line and the main IO line precharged to the VDL level, and grounds one of them to apply the stress voltage with the VDL amplitude. Therefore, a huge through current flows through the local IO line and the main IO line, resulting in an increase in current consumption.

The semiconductor memory device of the present invention
A memory cell;
One end connected to each other, a local IO line and a main IO line for inputting / outputting data to / from the memory cell;
A first voltage applying means for applying a first voltage to the other end of the local IO line in the first test mode;
In a second test mode, a semiconductor memory device comprising: a second voltage applying unit that applies a second voltage to the other end of the main IO line,
Control signal output means for outputting control signals having different voltage levels according to the first and second test modes;
Current limiting means for limiting a value of a current flowing through the local IO line and the main IO line in the first and second test modes according to the control signal.

A test method for a semiconductor memory device according to the present invention includes:
A memory cell;
One end connected to each other, a local IO line and a main IO line for inputting / outputting data to / from the memory cell;
A first voltage applying means for applying a first voltage to the other end of the local IO line in the first test mode;
In a second test mode, a test method for a semiconductor memory device comprising: a second voltage applying unit that applies a second voltage to the other end of the main IO line,
A control signal output step for outputting control signals having different voltage levels according to the first and second test modes;
And a current limiting step of limiting a value of a current flowing through the local IO line and the main IO line in the first and second test modes according to the control signal.

  According to the present invention, the semiconductor memory device has a first test mode in which a first voltage is applied to the other end of the local IO line, one end of which is connected to one end of the main IO line, and the other end of the main IO line. In response to the second test mode in which the second voltage is applied, control signals having different voltage levels are output, and the values of currents flowing through the local IO line and the main IO line in the first and second test modes are output. Limit according to the control signal.

  Therefore, it is possible to prevent an enormous through current from flowing through the local IO line and the main IO line, and to suppress an increase in current consumption in the stress application test.

1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the semiconductor memory device of 2nd Embodiment by this invention. 6 is a diagram for explaining a configuration of a semiconductor memory device described in Patent Document 1. FIG.

EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.
(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device 100 according to the first embodiment of the present invention. Note that FIG. 1 mainly shows a configuration for writing or reading data in a memory cell (not shown).

  1 includes local IO lines LIOT and LIOB, main IO lines MIOT and MIOB, a circuit block WAMP, a circuit block IOTG, a circuit block VBLPBF, a circuit block IOEQ, and a circuit block BLEQCT. Have.

  One end of each of local IO lines LIOT and LIOB is connected to one end of main IO lines MIOT and MIOB, and the other end is connected to circuit block VBLPBF. When local IO lines LIOT and LIOB are not specified, they are referred to as local IO lines LIO.

  Main IO lines MIOT and MIOB have one end connected to one end of local IO lines LIOT and LIOB via circuit block IOTG, and the other end connected to a peripheral circuit for writing or reading data to or from the memory cell. . When the main IO lines MIOT and MIOB are not specified, they are called main IO lines MIO.

  The local IO line LIO and the main IO line MIO input / output data to / from the memory cell.

  The circuit block WAMP, which is the second voltage application means, is an example of a peripheral circuit, and applies data of a desired level to the main IO line MIO and the local IO line to write data to the memory cell.

  The circuit block IOTG connects the local IO line LIO and the main IO line MIO.

  The circuit block VBLPBF as the first voltage application means outputs a voltage VBLPj for precharging a bit line (not shown) for writing or reading data to or from the memory cell during normal operation.

  Note that VBLPj becomes a stress voltage during the stress application test.

  The circuit block BLEQCT which is a control signal output means connects the circuit block VBLPBF and the local IO line LIO and limits the value of the test current flowing through the local IO line LIO and the main IO line MIO during the stress application test. A signal BLEQ ′ that is a control signal is output.

  The circuit block IOEQ includes a transfer gate that connects the circuit block VBLPBF and the local IO line LIO, and connects the circuit block VBLPBF and the local IO line LIO.

  In the present embodiment, the transfer gate also operates as a current limiting unit that limits the value of the test current according to the signal BLEQ 'during the stress application test.

  Next, the configuration of each circuit block will be described.

  The circuit block WAMP includes NAND circuits 101 and 102, AND circuits 103 and 104, inverter circuits 105 and 106, NOR circuits 107 and 108, OR circuits 109 and 110, P-type transistors 121 and 122, and N-type. Transistors 123 and 124.

  NAND circuit 101 receives signal DATAj and signal WRTT, and outputs signal 111 to AND circuit 103 and inverter circuit 105.

  NAND circuit 102 receives signal DATABj obtained by inverting signal DATAj and signal WRTT, and outputs signal 112 to AND circuit 104 and inverter circuit 106.

  The AND circuit 103 receives the signal 111 and the signal PIOT output from the NAND circuit 101 and outputs a signal 113 to the NOR circuit 107.

  The AND circuit 104 receives the signal 112 and the signal PIOT output from the NAND circuit 102 and outputs a signal 114 to the NOR circuit 108.

  The inverter circuit 105 outputs a signal 115 obtained by inverting the signal 111 output from the NAND circuit 101 to the OR circuit 109.

  The inverter circuit 106 outputs a signal 116 obtained by inverting the signal 112 output from the NAND circuit 102 to the OR circuit 110.

  The NOR circuit 107 receives the signal 113 and the signal TVBLPL output from the AND circuit 103 and outputs a signal 117 to the transistor 121.

  The NOR circuit 108 receives the signal 114 and the signal TVBLPL output from the AND circuit 104 and outputs a signal 118 to the transistor 122.

  The OR circuit 109 receives the signal 115 and the signal TVBLPH output from the inverter circuit 105 and outputs a signal 119 to the transistor 123.

  The OR circuit 110 receives the signal 116 output from the inverter circuit 106 and the signal TVBLPH, and outputs the signal 120 to the transistor 124.

  The transistor 121 has a gate connected to the output of the NOR circuit 107, a source connected to a power supply that outputs a voltage of VDD level, and a drain connected to the drain of the transistor 123.

  The transistor 122 has a gate connected to the output of the NOR circuit 108, a source connected to a power supply that outputs a voltage of VDD level, and a drain connected to the drain of the transistor 124.

  The transistor 123 has a gate connected to the output of the OR circuit 109, a source connected to GND, and a drain connected to the drain of the transistor 121.

  The transistor 124 has a gate connected to the output of the OR circuit 110, a source connected to GND, and a drain connected to the drain of the transistor 122.

  The circuit block IOTG includes a NAND circuit 201 and N-type transistors 202 and 203.

  The NAND circuit 201 receives the signal LIOSWB and the signal TWBINB and outputs the signal LIOSW.

  Transistor 202 has its gate connected to the output of NAND circuit 201, one of its source and drain connected to local IO line LIOT, and the other connected to main IO line MIOT.

  Transistor 203 has its gate connected to the output of NAND circuit 201, one of its source and drain connected to local IO line LIOB, and the other connected to main IO line MIOB.

  Note that the sources and drains of the transistors 202 and 203 are switched according to the direction in which the test current flows.

  The circuit block VBLPBF includes a P-type transistor 301 and N-type transistors 302 and 303.

  The transistor 301 has a gate connected to the input of the signal TVBLPHB, a source connected to a power supply that outputs a voltage at a VDL level, and drains connected to the drains of the transistors 302 and 303.

  The transistor 302 has a gate connected to the input of the signal TVBLPSTPB, a source connected to a power supply that outputs a voltage of VDL / 2 level, and a drain connected to the drains of the transistors 301 and 303.

  The transistor 303 has a gate connected to the input of the signal TVBLPL, a source connected to GND, and a drain connected to the drains of the transistors 301 and 302.

  The circuit block BLEQCT includes an inverter circuit 401, variable resistance elements 403 and 405 that are first and second variable resistance elements, and N-type transistors 407, 409, and 411.

  The inverter circuit 401 outputs a signal 402 obtained by inverting the signal TVBLPL.

  The variable resistance element 403 has one end connected to the inverter circuit 401 and the other end connected to the transistor 407.

  The variable resistance element 405 has one end connected to the transistor 407 and the other end connected to the transistor 409 and the transistor 411.

  The gate of the transistor 407 is connected to the input of the signal TWBIN, the variable resistance element 403 is connected to one of the source and the drain, and the variable resistance element 405 is connected to the other.

  The transistor 409 has a gate connected to an input of the signal TVBLPH, a variable resistance element 405 connected to one of a source and a drain, and a GND connected to the other.

  The gate of the transistor 411 is connected to the input of the signal TVBLPL, the variable resistance element 405 is connected to one of the source and the drain, and GND is connected to the other.

  The circuit block IOEQ includes a clocked inverter circuit 501, a P-type transistor 502, and N-type transistors 503, 504, and 505. Note that the transistors 504 and 505 form a transfer gate.

  In a normal operation, the clocked inverter circuit 501 outputs a signal BLEQ obtained by inverting the input signal BLEQB to the transistors 504 and 505, and in a stress application test, the signal TWBIN = High is input and the output of the signal BLEQ is stopped. .

  The transistor 502 has a gate connected to the input of the signal TWBINB, a source connected to the output of the circuit block BLEQCT, and a drain connected to the gates of the transistors 504 and 505.

  The transistor 503 has a gate connected to the input of the signal TWBIN, a source connected to the output of the circuit block BLEQCT, and a drain connected to the gates of the transistors 504 and 505.

  The transistor 504 has a gate connected to the input of the signal BLEQ or the signal BLEQ ', a source and a drain connected to the local IO line LIOT, and the other connected to a circuit block VBLPBF.

  The gate of the transistor 505 is connected to the input of the signal BLEQ or the signal BLEQ ', the local IO line LIOB is connected to one of the source and the drain, and the circuit block VBLPBF is connected to the other.

  Note that the sources and drains of the transistors 504 and 505 are switched depending on the direction in which the test current flows.

  Next, the operation of the semiconductor memory device 100 during the stress application test will be described.

(1) Operation when connecting the local IO line LIO and the main IO line MIO When the signal TWBINB = Low is input, the NAND circuit 201 outputs the signal LIOSW = High.

  The transistors 202 and 203 are turned on when the signal LIOSW = High is input to their gates, and the local IO line LIOT and the main IO line MIOT are connected to the local IO line LIOB and the main IO line MIOB, respectively.

(2) Operation when Connecting Local IO Line LIO and Circuit Block VBLPBF The clocked inverter circuit 501 receives the signal TWBIN = High and stops the output of the signal BLEQ.

  The transistors 502 and 503 are turned on when the signals TWBINB = Low and TWBIN = High are input to the gates, respectively.

  As a result, the signal BLEQ ′ output from the circuit block BLEQCT is input to the gates of the transistors 504 and 505, and the transistors 504 and 505 are turned on to connect the local IO line LIO and the circuit block VBLPBF.

(3) Operation when a test current is made to flow (3-1) Operation in the first test mode in which a test current is made to flow from the circuit block VBLPBF to the circuit block WAMP In the first test mode, the signal TVBLPHB = Low, TVBLPSTPB = Low and signal TVBLPL = Low are input, the transistor 301 is turned on, and the transistors 302 and 303 are turned off.

  As a result, VBLPj becomes the VDL level, and the voltage of the VDL level that is the first voltage is applied to the other end of the local IO line LIO.

  In the circuit block WAMP, the signal WRTT = Low and the signal PIOT = Low are input, the AND circuit 103 outputs the signal 113 = Low, the AND circuit 104 outputs the signal 114 = Low, and the inverter circuit 105 outputs the signal 115 = Low. And the inverter circuit 106 outputs a signal 116 = Low.

  In the first test mode, the signal TVBLPH = High is input, the OR circuit 109 outputs the signal 119 = High, and the OR circuit 110 outputs the signal 120 = High.

  Each of the transistors 123 and 124 is turned on when a signal 119 = High and a signal 120 = High are input to the gates.

  The signal TVBLPL = Low is input, the NOR circuit 107 outputs the signal 117 = High, and the NOR circuit 108 outputs the signal 118 = High.

  Each of the transistors 121 and 122 is turned OFF when the signal 117 = High and the signal 118 = High are input to the gates.

  Therefore, the main IO line MIOT and the main IO line MIOB are connected to GND, and the ground voltage is applied to the other end of the main IO line.

  Thus, by applying a VDL level voltage to the other end of the local IO line LIO and applying a ground voltage to the other end of the main IO line MIO, a test current flows from the circuit block VBLPBF to the circuit block WAMP. be able to.

(3-2) Operation in the second test mode in which a test current flows from the circuit block WAMP to the circuit block VBLPBF In the second test mode, the signal TVBLPHB = High, the signal TVBLPSTPB = Low, and the signal TVBLPL = High are input Thus, the transistors 301 and 302 are turned off and the transistor 303 is turned on.

  As a result, VBLPj becomes GND level, and the ground voltage is applied to the other end of the local IO line LIO.

  As described above, in the circuit block WAMP, the signal WRTT = Low and the signal PIOT = Low are input, the AND circuit 103 outputs the signal 113 = Low, the AND circuit 104 outputs the signal 114 = Low, and the inverter circuit 105 Outputs a signal 115 = Low, and the inverter circuit 106 outputs a signal 116 = Low.

  In the second test mode, the signal TVBLPL = High is input, the NOR circuit 107 outputs the signal 117 = Low, and the NOR circuit 108 outputs the signal 118 = Low.

  The transistors 121 and 122 are turned on when the signal 117 = Low and the signal 118 = Low are input to the gates, respectively.

  Further, the signal TVBLPH = Low is input, the OR circuit 109 outputs the signal 119 = Low, and the OR circuit 110 outputs the signal 120 = Low.

  The transistors 123 and 124 are turned OFF when the signal 119 = Low and the signal 120 = Low are input to the gates, respectively.

  Therefore, the VDD level voltage, which is the second voltage, is applied to the other ends of the main IO line MIOT and the main IO line MIOB.

  In this way, by applying the ground voltage to the other end of the local IO line LIO and applying the VDD level voltage to the other end of the main IO line MIO, a test current flows from the circuit block WAMP to the circuit block VBLPBF. be able to.

(4) Operation when Limiting Test Current Value The signal BLEQ ′ output from the circuit block BLEQCT is input to the gates of the transistors 504 and 505.

  Here, since the transistors 504 and 505 are provided between the local IO line LIO and the circuit block VBLPBF, the value of the current flowing into the local IO line LIO can be limited according to the voltage applied to the gate. As a result, the value of the test current can also be limited.

  The voltage level of the signal BLEQ ′ can be adjusted as follows.

  The transistor 407 is turned on when a signal TWBIN = High is input to its gate.

  In the first test mode, the inverter circuit 401 receives the signal TVBLPL = Low and outputs the inverted signal 402 = High. Note that the voltage level of the signal 402 = High is the VDD level.

  As a result, a VDD level voltage is applied to one end of the variable resistance element 403.

  The transistor 409 is turned on when the signal TVBLPH = High is inputted to the gate, the transistor 411 is turned off when the signal TVBLPL = Low is inputted to the gate, and the other end of the variable resistance element 405 is connected to GND.

  The circuit block BLEQCT outputs a voltage at a connection point between the variable resistance element 403 and the variable resistance element 405 as a signal BLEQ '. Here, the voltage at the connection point is determined by the ratio between the resistance value R1 of the variable resistance element 403 and the resistance value R2 of the variable resistance element 405 with respect to the voltage at the VDD level. Thus, the voltage level of the signal BLEQ ′ can be adjusted to a voltage level that limits the value of the test current to a predetermined value.

  In the second test mode, the inverter circuit 401 receives the signal TVBLPL = High and outputs an inverted signal 402 = Low. The voltage level of the signal 402 = Low is the ground voltage.

  As a result, the ground voltage is applied to one end of the variable resistance element 403.

  The transistor 409 is turned OFF when the signal TVBLPH = Low is input to the gate, the transistor 411 is turned ON when the signal TVBLPL = High is input to the gate, and a voltage of VDL level is applied to the other end of the variable resistance element 405. .

  Since the voltage at the connection point between the variable resistance element 403 and the variable resistance element 405 is determined by the ratio of the resistance value R1 and the resistance value R2 to the voltage at the VDL level, the resistance values R1, R2 are the same as in the first test mode. Is set in advance, the voltage level of the signal BLEQ ′ can be adjusted to a voltage level that limits the value of the test current to a predetermined value.

  As described above, according to the present embodiment, the semiconductor memory device 100 outputs the signal BLEQ ′ having different voltage levels according to the first or second test mode, and the test current according to the output signal BLEQ ′. Limit the value of.

Therefore, it is possible to prevent an enormous through current from flowing through the local IO line and the main IO line, and to suppress an increase in current consumption in the stress application test.
(Second Embodiment)
FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device 200 according to the second embodiment of the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  The semiconductor memory device 200 of this embodiment is different from the semiconductor memory device 100 of the first embodiment in that a circuit block VBLPTG is provided between the circuit block VBLPBF and the circuit block IOEQ, and from the circuit block IOEQ. The clocked inverter circuit 501 and the transistors 502 and 503 are deleted, the NAND circuit 601 is added, the clocked inverter circuit 701, the P-type transistor 702, and the N-type transistor 703 are added to the circuit block BLEQCT. It is different from the point that was added.

  The NAND circuit 601 receives the input signal BLEQB and the signal TWBINB, and outputs the signal BLEQ to the transistors 504 and 505.

  The clocked inverter circuit 701 receives the signal TWBIN and the signal TWBINB and outputs a signal 704 to the circuit block VBLPTG.

  The transistor 702 has a gate connected to the input of the signal TWBINB, a source connected to the input of the signal BLEQ ', and a drain connected to the circuit block VBLPTG.

  The transistor 703 has a gate connected to the input of the signal TWBIN, a source connected to the input of the signal BLEQ ', and a drain connected to the circuit block VBLPTG.

  The circuit block VBLPTG has an N-type transistor 801.

  The gate of the transistor 801 is connected to the input of the signal output from the circuit block BLEQCT, the circuit block VBLPBF is connected to one of the source and the drain, and the circuit block IOEQ is connected to the other.

  Next, the operation of the semiconductor memory device 200 will be described.

  The NAND circuit 601 receives the signal BLEQB and the signal TWBINB and outputs a signal 602. Here, when the signal 602 = High, the transistors 504 and 505 are turned on.

  The clocked inverter circuit 701 outputs the signal 704 = High in which the ground voltage (Low) is inverted during normal operation, and receives the signal TWBIN = High during the stress application test, and stops the output of the signal 704.

The transistor 702 is turned on when the signal TWBINB = Low is input to the gate,
The transistor 703 is turned on when a signal TWBINB = High is input to its gate.

  As a result, the signal BLEQ ′ is input to the gate of the transistor 801.

  The transistor 801 connects the circuit block VBLPBF and the circuit block IOEQ according to the voltage level of the signal BLEQ ′ input to the gate, and limits the value of the test current.

  As described above, the value of the test current can also be limited by providing the circuit block VBLPTG between the circuit block VBLPBF and the circuit block IOEQ.

100, 200 Semiconductor memory device 101, 102, 201, 601 NAND circuit 103, 104 AND circuit 105, 106, 401 Inverter circuit 107, 108 NOR circuit 109, 110 OR circuit 121, 122, 301, 502, 702 P-type transistor 123 , 124, 202, 203, 302, 303, 407, 409, 411, 503, 504, 505, 703, 801 N-type transistors 403, 405 Variable resistance elements 501, 701 Clocked inverter circuits WAMP, IOTG, VBLPBF, IOEQ, BLEQCT, VBLPTG Circuit block LIO, LIOT, LIOB Local IO line MIO, MIOT, MIOB Main IO line

Claims (6)

A memory cell;
One end connected to each other, a local IO line and a main IO line for inputting / outputting data to / from the memory cell;
A first voltage applying means for applying a first voltage to the other end of the local IO line in the first test mode;
In a second test mode, a semiconductor memory device comprising: a second voltage applying unit that applies a second voltage to the other end of the main IO line,
Control signal output means for outputting control signals having different voltage levels according to the first and second test modes;
A semiconductor memory device having current limiting means for limiting a value of a current flowing through the local IO line and the main IO line in the first and second test modes according to the control signal;   The semiconductor memory device according to claim 1, wherein the current limiting unit is provided between the local IO line and the first voltage applying unit. The current limiting means includes
The control signal output means is connected to the gate,
3. The transistor having a source and a drain connected to one of the local IO lines and the other connected to the first voltage application unit according to the first and second test modes. Semiconductor memory device. The control signal output means includes
First and second variable resistance elements having one end connected to each other and having a predetermined resistance value according to the first and second test modes;
Third voltage applying means for applying a third voltage to one of the other ends of the first and second variable resistance elements and applying a ground voltage to the other in accordance with the first and second test modes. And comprising
4. The semiconductor memory device according to claim 1, wherein the control signal is output from a connection point between the first and second variable resistance elements. 5. A memory cell;
One end connected to each other, a local IO line and a main IO line for inputting / outputting data to / from the memory cell;
A first voltage applying means for applying a first voltage to the other end of the local IO line in the first test mode;
In a second test mode, a test method for a semiconductor memory device comprising: a second voltage applying unit that applies a second voltage to the other end of the main IO line,
A control signal output step for outputting control signals having different voltage levels according to the first and second test modes;
And a current limiting step of limiting a value of a current flowing through the local IO line and the main IO line in accordance with the control signal in the first and second test modes. The semiconductor memory device
First and second variable resistance elements having one end connected to each other and having a predetermined resistance value according to the first and second test modes;
Third voltage applying means for applying a third voltage to one of the other ends of the first and second variable resistance elements and applying a ground voltage to the other in accordance with the first and second test modes. And further comprising
In the control signal output step,
The test method according to claim 5, wherein the control signal is output from a connection point between the first and second variable resistance elements.

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