JP2011086969A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device allowing the structure thereof to be simplified. <P>SOLUTION: When etching a second interlayer film 16, a type of an etching gas or etchant is selected so that the etching rate of a first interlayer film 14 becomes smaller than the etching rate of the second interlayer film 16. The first interlayer film 14 is formed with silicon nitride (SiN) or the like having a dense molecular density. Accordingly, the first insulating layer 14 functions as an etching stopper and a diffusion inhibitor film. Since it is not necessary to form an etching stopper film and a diffusion inhibitor film separately, the structure and the manufacturing process of this semiconductor device can be simplified. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a contact hole and a wiring groove communicating therewith, and a method for manufacturing such a semiconductor device.

  For example, Patent Document 1 discloses this type of semiconductor device using a dual damascene process, and FIG. 6 shows this conventional semiconductor device 1. The semiconductor device 1 includes a semiconductor substrate 2, and a first interlayer film 3a, an etching stopper film 3b, and a second interlayer film 3c are stacked on the semiconductor substrate 2. In the first interlayer film 3a and the etching stopper film 3b, a contact hole 5a reaching the conductive portion 4 formed on the semiconductor substrate 2 is formed, and the second interlayer film 3c including the upper portion of the contact hole 5a is formed. The wiring trench 5b is formed. A metal wiring 6 is buried in the contact hole 5a and the wiring groove 5b. The etching stopper film 3b also plays a role of preventing diffusion of copper (Cu) or the like constituting the metal wiring 6.

When manufacturing the semiconductor device 1, first, as shown in FIG. 7A, the conductive portion 4 is formed by doping polycrystalline silicon or the like on the upper portion of the semiconductor substrate 2. The first interlayer film 3a and the etching stopper film 3b are stacked, and the window 7 is formed in the etching stopper film 3b. Subsequently, as shown in FIG. 7B, a second interlayer film 3c is laminated on the etching stopper film 3b. Then, as shown in FIG. 7C, the first interlayer film 3a and the second interlayer film 3c are masked and etched with the patterned resist 8 to form contact holes 5a and wiring grooves 5b. Subsequently, after removing the resist 8, as shown in FIG. 7D, a metal wiring 6 made of copper (Cu), aluminum (Al) or the like is formed so as to fill the contact hole 5a and the wiring groove 5b. Unnecessary metal wiring 6 is removed by CMP (chemical mechanical polishing).
Japanese Patent Publication No. 5-46983

  In the conventional semiconductor device 1, since the etching stopper film 3b is formed, the depth of the wiring groove 5b can be made uniform. However, since the structure is complicated, the manufacturing process is complicated. It was.

  Therefore, a main object of the present invention is to provide a semiconductor device capable of simplifying the structure.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device that can simplify the manufacturing process.

  1st invention etches the 1st interlayer film, the contact hole formed in the 1st interlayer film, the 2nd interlayer film formed in the surface of the 1st interlayer film, and the 2nd interlayer film A semiconductor device comprising a wiring groove formed by this and communicating with a contact hole, wherein the first interlayer film has an etching rate smaller than that of the second interlayer film in etching.

In the second invention, a first interlayer film is laminated on a semiconductor substrate, a second interlayer film is laminated on the surface of the first interlayer film, and the second interlayer film is used as an etching stopper. In this method, the interlayer film is etched to form a wiring groove, and the first interlayer film is etched to form a contact hole communicating with the wiring groove.

  In a third aspect of the invention, a first interlayer film is stacked on a semiconductor substrate, a contact hole is formed by etching the first interlayer film, and a second interlayer film is stacked on the surface of the first interlayer film. The method of manufacturing a semiconductor device, wherein the second interlayer film is etched using the first interlayer film as an etching stopper to form a wiring groove communicating with the contact hole.

  In the first invention, since the first interlayer film has an etching rate lower than that of the second interlayer film, the first interlayer film functions as an etching stopper when etching the second interlayer film. . Therefore, it is not necessary to form an etching stopper film between the first interlayer film and the second interlayer film. If the first interlayer film is composed of a nitride film having a dense molecular density, the first interlayer film can be used as a diffusion blocking film.

  In the second and third inventions, since the second interlayer film is etched using the first interlayer film as an etching stopper, the step of forming the etching stopper film can be omitted.

  According to the present invention, the structure can be simplified and the manufacturing process can be simplified.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

It is an illustration figure which shows one Example of this invention. It is an illustration figure which shows the manufacturing method of FIG. 1 Example. It is an illustration figure which shows the manufacturing method of FIG. 1 Example. It is an illustration figure which shows the other manufacturing method of FIG. 1 Example. It is an illustration figure which shows the other manufacturing method of FIG. 1 Example. It is an illustration figure which shows the conventional semiconductor device. It is an illustration figure which shows the manufacturing method of the conventional semiconductor device.

  A semiconductor device 10 of this embodiment shown in FIG. 1 includes a semiconductor substrate 12 made of silicon (Si) or the like. A first interlayer film 14 made of silicon nitride (SiN) or the like and a second interlayer film 16 made of silicon oxide (SiO 2) or the like are stacked on the semiconductor substrate 12. A contact hole 20 reaching the conductive portion 18 formed in the upper portion is formed, and a wiring trench 22 is formed in the second interlayer film 16 including the upper portion of the contact hole 20. A metal wiring 24 made of copper (Cu), aluminum (Al), or the like is embedded in the contact hole 20 and the wiring groove 22.

  The semiconductor device 10 is manufactured by the following process using a so-called dual damascene method. That is, first, as shown in FIG. 2A, the conductive portion 18 is formed by doping polycrystalline silicon or the like on the semiconductor substrate 12, and the silicon nitride having a dense molecular density is formed on the semiconductor substrate 12. A first interlayer film 14 made of (SiN) or the like is laminated by sputtering or the like. Then, as shown in FIG. 2B, the first interlayer film 14 is etched by masking it with a patterned resist 26 a to form a contact hole 20 reaching the conductive portion 18. Subsequently, after removing the resist 26a, as shown in FIG. 2C, a second interlayer film 16 made of silicon oxide (SiO2) or the like is laminated by CVD or the like so as to fill the contact hole 20.

  Then, as shown in FIG. 3D, the second interlayer film 16 is etched by masking it with a patterned resist 26b to form a wiring groove 22 communicating with the contact hole 20. In this etching step, the type of etching gas or etchant is selected so that the etching rate of the first interlayer film 14 is smaller than the etching rate of the second interlayer film 16. Therefore, the first interlayer film 14 functions as an etching stopper.

  Then, as shown in FIG. 3E, a metal wiring 24 made of copper (Cu), aluminum (Al), or the like is laminated by sputtering or the like so as to fill the contact hole 20 and the wiring groove 22, and FIG. ), Unnecessary metal wiring 24 is removed by CMP (chemical mechanical polishing) or the like.

  According to this embodiment, since the first interlayer film 14 functions as an etching stopper, it is not necessary to separately form a conventional etching stopper film. Therefore, the structure can be simplified and the manufacturing process can be simplified.

  In addition, since the first interlayer film 14 is formed of silicon nitride (SiN) or the like having a high molecular density, the first interlayer film 14 is prevented from diffusing copper (Cu) or the like constituting the metal wiring 24. It can also be used as a membrane.

  The semiconductor device 10 may be manufactured by other manufacturing methods shown in FIGS. That is, first, as shown in FIG. 4A, polycrystalline silicon or the like is doped on the top of the semiconductor substrate 12 to form a conductive portion 18, and silicon nitride (with a dense molecular density) is formed on the semiconductor substrate 12. A first interlayer film 14 made of SiN) or the like is laminated by sputtering or the like, and a second interlayer film 16 made of silicon oxide (SiO2) or the like is laminated by CVD or the like. Then, as shown in FIG. 4B, the second interlayer film 16 is masked with a patterned resist 26c and etched to form wiring trenches 22. In this etching step, the type of etching gas or etchant is selected so that the etching rate of the first interlayer film 14 is smaller than the etching rate of the second interlayer film 16. Therefore, the first interlayer film 14 functions as an etching stopper. Subsequently, after removing the resist 26c, as shown in FIG. 4C, the first interlayer film 14 is etched by masking with the patterned resist 26d, and the contact from the bottom of the wiring trench 22 to the conductive portion 18 is performed. Hole 20 is formed.

  Then, as shown in FIG. 5D, a metal wiring 24 made of copper (Cu), aluminum (Al), or the like is laminated by sputtering or the like so as to fill the contact hole 20 and the wiring groove 22, and the structure shown in FIG. ), Unnecessary metal wiring 24 is removed by CMP (chemical mechanical polishing) or the like.

  Also in this embodiment, since the first interlayer film 14 functions as an etching stopper and a diffusion blocking film, the structure and the manufacturing process can be simplified.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Semiconductor substrate 14 ... 1st interlayer film 16 ... 2nd interlayer film 18 ... Conductive part 20 ... Contact hole 22 ... Wiring groove 24 ... Metal wiring

Claims (4)

A first interlayer film,
A contact hole formed in the first interlayer film;
A semiconductor device comprising: a second interlayer film formed on a surface of the first interlayer film; and a wiring groove formed by etching the second interlayer film and communicating with the contact hole,
The semiconductor device, wherein the first interlayer film has an etching rate smaller than an etching rate of the second interlayer film in the etching.   The semiconductor device according to claim 1, wherein the first interlayer film is a nitride film. Laminating a first interlayer film on a semiconductor substrate;
Laminating a second interlayer film on the surface of the first interlayer film;
Etching the second interlayer film using the first interlayer film as an etching stopper to form a wiring groove;
A method of manufacturing a semiconductor device, comprising: etching the first interlayer film to form a contact hole communicating with the wiring groove. Laminating a first interlayer film on a semiconductor substrate;
Etching the first interlayer film to form a contact hole;
Laminating a second interlayer film on the surface of the first interlayer film;
A method of manufacturing a semiconductor device, wherein the second interlayer film is etched using the first interlayer film as an etching stopper to form a wiring groove communicating with the contact hole.

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