JP2011071339A - Light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting element capable of suppressing an increase of a forward voltage while maintaining a light-emitting area. <P>SOLUTION: The light-emitting element 1 includes: a semiconductor laminate structure comprising a nitride compound semiconductor including a first-conductivity type semiconductor layer, a light-emitting layer 25, and a second-conductivity type semiconductor layer differing from a first conductivity type; a p-contact electrode 30 coming into ohmic contact with the second-conductivity type semiconductor layer; a second spot-like electrode coming into ohmic contact with the p-contact electrode 30; and a plurality of first spot-like electrodes that come into ohmic contact with the first-conductivity type semiconductor layer which are exposed by partially removing the second-conductivity type semiconductor layer and the light-emitting layer 25, and larger than the second electrodes in number. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a light emitting element in which two types of electrodes are provided on the same surface side.

  Conventionally, a p-contact electrode formed on a semiconductor layer, a passivation film that covers the surface of the p-contact electrode, a passivation film that has an opening in part, and a bonding electrode that has a solder layer on the upper surface, On the p-contact electrode surface, a buffer electrode having a diameter larger than that of the opening and flatter than the surface of the p-contact electrode is formed at the bottom of the opening of the passivation film, and a semiconductor to which the junction electrode is connected to the buffer electrode A light emitting element is known (see, for example, Patent Document 1).

  In the semiconductor light emitting device described in Patent Document 1, a buffer electrode is formed on the surface of the p-contact electrode, and an opening smaller than the buffer electrode is formed on the passivation film on the buffer electrode, so that the surface of the buffer electrode is flat. Therefore, adhesion between the buffer electrode and the passivation film can be ensured, and when the opening is etched, it is possible to suppress the progress of lateral etching from the interface between the buffer electrode and the passivation film. it can.

JP 2008-288548 A

  However, in the semiconductor light emitting device described in Patent Document 1, the number of n electrodes is equal to or less than the number of p buffer electrodes, and the forward voltage is reduced when the size of the n electrodes is reduced for the purpose of expanding the light emitting area. May rise.

  Accordingly, an object of the present invention is to provide a light emitting element capable of suppressing an increase in forward voltage while maintaining a light emitting area.

  In order to achieve the above object, according to the present invention, a first conductive type first semiconductor layer, a light emitting layer, and a second conductive type second semiconductor layer different from the first conductive type are stacked, and the first conductive type is stacked. A semiconductor stacked structure composed of a nitride compound semiconductor from which a part of the semiconductor layer and the light emitting layer is removed and the first semiconductor layer is exposed; a p-contact electrode in ohmic contact with the second semiconductor layer; and the p-contact Provided is a light-emitting element comprising: a point-like second electrode that is in ohmic contact with an electrode; and a plurality of point-like first electrodes that are in ohmic contact with an exposed portion of the first semiconductor layer and are larger than the number of the second electrodes. Is done.

  Further, in the light emitting device, the first semiconductor layer is an n-type semiconductor layer, the second semiconductor layer is a p-type semiconductor layer, and the n-type semiconductor layer is formed from a sheet resistance of the p-contact electrode. It is preferable to have a high sheet resistance.

  Further, in the light emitting device, the first electrode is an n electrode, the second electrode is a p buffer electrode, and a portion where a distance in plan view between the n electrode and the p buffer electrode is shortest is There may be a plurality of them.

  In the light emitting device, the plurality of n electrodes may form at least one pair provided in a line-symmetrical position with respect to an axis passing through the p-buffer electrode in a plan view.

  The light emitting element includes at least one group in which a plurality of the p buffer electrodes are linearly arranged on the p contact electrode, and the plurality of n electrodes are positioned symmetrically with respect to the symmetry axis. May be provided.

  Further, in the light emitting element, a plurality of the p buffer electrodes may be provided on the p contact electrode, and the plurality of n electrodes may be provided at a point-symmetrical position with the p buffer electrode as a center of symmetry. Good.

  According to the light emitting device of the present invention, an increase in forward voltage can be suppressed while maintaining a light emitting area.

FIG. 1A is a longitudinal sectional view of a light emitting device according to a first embodiment of the present invention. FIG. 1B is a plan view of the light-emitting element according to the first embodiment of the present invention. FIG. 2A is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2B is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2C is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 3 is a plan view of a light emitting device according to the second embodiment of the present invention. FIG. 4 is a plan view of a light emitting device according to the third embodiment of the present invention. FIG. 5 is a plan view of a light emitting device according to a fourth embodiment of the present invention. FIG. 6 is a plan view of a light emitting device according to a fifth embodiment and a modification of the present invention.

[First Embodiment]
FIG. 1A shows an outline of a longitudinal section of a light emitting element according to the first embodiment of the present invention, and FIG. 1B shows an outline of an upper surface of the light emitting element according to the first embodiment of the present invention. In addition, FIG. 1A has shown the outline | summary of the longitudinal cross-section in the AA of FIG. 1B.

(Configuration of Light-Emitting Element 1)
As shown in FIG. 1A, the light-emitting element 1 includes a sapphire substrate 10 having a C plane (0001), a buffer layer 20 provided on the sapphire substrate 10, and an n-type semiconductor provided on the buffer layer 20. A side contact layer 22, an n-side cladding layer 24 provided on the n-side contact layer 22, a light emitting layer 25 provided on the n-side cladding layer 24, a p-side cladding layer 26 provided on the light emitting layer 25, A semiconductor multilayer structure including a p-side contact layer 28 made of a p-type semiconductor provided on the p-side cladding layer 26 is provided. The n-type contact layer 22 and the n-side cladding layer 24 constitute an n-type semiconductor layer 23, and the p-side cladding layer 26 and the p-side contact layer 28 constitute a p-type semiconductor layer 27.

  The light emitting element 1 includes n electrodes 40a to 40d as first electrodes provided on the n-side contact layer 22 exposed by etching from the p-side contact layer 28 to at least the surface of the n-side contact layer 22. (See FIG. 1B), a p-contact electrode 30 provided on the p-side contact layer 28, p-buffer electrodes 42a and 42b as second electrodes provided in a partial region on the p-contact electrode 30, and an n-side Insulation as a passivation film having an opening 52 exposing the region where the n electrodes 40a to 40d are arranged on the contact layer 22 and an opening 52 exposing the region where the p buffer electrodes 42a and 42b are arranged on the p contact electrode 30 A layer 50, a reflective layer 60 disposed inside the insulating layer 50, and a part of the upper surface of the insulating layer 50, and an n current Comprises a bonding electrode 70 provided on the opening 52 on 40 a to 40 d, p buffer electrode 42a covers a portion of the upper surface of the insulating layer 50, and a bonding electrode 72 provided in the opening 52 on 42b. The n-side bonding electrode 70 and the p-side bonding electrode 72 can be formed having a barrier layer and a solder layer from the side of each electrode.

Here, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are each made of a group III nitride compound semiconductor. It is a layer. The group III nitride compound semiconductor is, for example, a quaternary group III nitride of Al _x Ga _y In _1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A compound compound semiconductor can be used, and a binary group III nitride compound semiconductor such as AlN, GaN, or InN, Al _x Ga _1-x N, Al _x In _1-x N, or Ga _x In _A ternary group III nitride compound semiconductor of _1-xN (where 0 <x <1) can also be used.

  In the present embodiment, the buffer layer 20 is made of AlN. The n-side contact layer 22 and the n-side cladding layer 24 are each formed from n-GaN doped with a predetermined amount of n-type dopant (for example, Si). The light emitting layer 25 has a multiple quantum well structure formed of InGaN / GaN / AlGaN. Further, the p-side cladding layer 26 and the p-side contact layer 28 are each formed from p-GaN doped with a predetermined amount of p-type dopant (for example, Mg).

In addition, the p-contact electrode 30 according to the present embodiment is formed from an oxide semiconductor, for example, from ITO (Indium Tin Oxide). Here, in the present embodiment, the n-side contact layer 22 is formed with a sheet resistance higher than that of the p-contact electrode 30. The insulating layer 50 is mainly formed from, for example, silicon dioxide (SiO ₂ ). The reflection layer 60 is provided inside the insulating layer 50 and is formed of a metal material that reflects light emitted from the light emitting layer 25. The reflective layer 60 is made of Al, for example. The thickness of the entire insulating layer 50 is, for example, 0.1 μm or more and 1 μm or less, and the thickness of the reflective layer 60 provided inside the insulating layer 50 is, for example, 50 nm or more and 500 nm or less.

  As shown in FIG. 1A, the n electrodes 40 a to 40 d are positioned on the n-side contact layer 22 away from a mesa portion composed of a plurality of compound semiconductor layers from the n-side cladding layer 24 to the p-side contact layer 28. Is provided. In addition, the n electrodes 40 a to 40 d are in contact with the insulating layer 50 at outer surfaces that are not in contact with the barrier layer 70 on the upper surface in contact with the barrier layer 70. In the present embodiment, the plurality of n electrodes 40a to 40d are formed in a dot shape in plan view and are separated from each other. Here, the “spot shape” includes, for example, a circular shape, a polygonal shape, and the like. For example, when the n-electrode n-electrodes 40a to 40d are formed in a circular shape, the diameter is preferably 5 μm or more and 50 μm or less for the purpose of increasing the area of the light-emitting layer 25 (that is, the light-emitting area) in plan view. .

  On the other hand, the p buffer electrodes 42 a and 42 b are formed on a p contact electrode 30 provided on a mesa portion composed of a plurality of compound semiconductor layers from the n side cladding layer 24 to the p side contact layer 28. In addition, the p buffer electrodes 42 a and 42 b are in contact with the insulating layer 50 on the upper surface in contact with the barrier layer 70, and the outer edge portion not in contact with the barrier layer 70. The plurality of p buffer electrodes 42a and 42b are formed in a dot shape in plan view. For example, when the p buffer electrodes 42a and 42b are formed in a circular shape, the diameter is preferably 5 μm or more and 30 μm or less. The insulating layer 50 covers the p contact electrode 30 and the mesa portion except for the formation regions of the p buffer electrodes 42a and 42b, and covers the n side contact layer 22 except for the formation regions of the n electrodes 40a to 40d. . As shown in FIG. 1B, since the n-side junction electrode 70 and the p-side junction electrode 72 are exposed on the surface, the n-electrodes 40a to 40d and the p-buffer electrodes 42a and 42b are directly seen in a plan view. Can not be confirmed.

(Details of arrangement of n electrode and p buffer electrode)
In the present embodiment, more n electrodes in contact with the n-side contact layer 22 having a sheet resistance higher than that of the p contact electrode 30 are formed than the p buffer electrode. For example, when the number of n electrodes is x and the number of p buffer electrodes is y for the purpose of increasing the light emitting area of the light emitting element 1 in a plan view and suppressing the increase of the forward voltage, 1 <(x / y) <4 can be satisfied. The plurality of n electrodes are provided so that there are a plurality of portions having the shortest distance in plan view between the n electrode and the p buffer electrode so that current diffusion to the light emitting layer 25 is uniform. The plurality of n electrodes are provided at predetermined positions with respect to the axis passing through the p buffer electrode in plan view so that current diffusion to the light emitting layer 25 is uniform.

  Specifically, as shown in FIG. 1B, the light emitting element 1 is formed in a substantially square shape in plan view, and a plurality of p buffer electrodes 42a and 42b (two p buffer electrodes in the present embodiment) are formed in the square. Provided on the line. This middle line is defined as the axis 100. Of a plurality of n electrodes (four n electrodes in this embodiment), a pair of two n electrodes (in FIG. 1B, a pair consisting of an upper left n electrode 40a and a lower left n electrode 40c, and an upper right n electrode 40b) And the lower right n electrode 40d) are provided at positions where the shaft 100 is sandwiched and the distance from the shaft 100 is the same. In FIG. 1B, the upper left n-electrode 40a and the lower left n-electrode 40c are at positions opposite to each other with the shaft 100 in between, and the distance from the shaft 100 is the same. In other words, the upper left n-electrode 40a and the lower left n-electrode 40c are provided in line-symmetric positions with the axis 100 as the axis of symmetry.

  In the present embodiment, the upper left n-electrode 40a, the lower left n-electrode 40c, and the left p-buffer electrode 42a are provided linearly in plan view. That is, the p-buffer electrode is provided at a position corresponding to the intersection of the line connecting the n-electrodes provided at line-symmetric positions with respect to the axis 100 and the axis 100. As long as the p buffer electrode 42a is provided on the shaft 100, the p buffer electrode 42a and the n electrodes 40a and 40c may not be provided strictly linearly in plan view. The positional relationship among the right p buffer electrode 42b, the upper right n electrode 40b, and the lower right n electrode 40d is the same.

  The n-electrodes 40a to 40d are formed including at least one metal selected from the group consisting of Ni, Cr, Ti, Al, Pd, Pt, Au, V, Ir, and Rh, for example. Further, the p buffer electrodes 42 a and 42 b are formed to have a metal layer mainly composed of Ni at a contact portion with the p contact electrode 30. Further, the p buffer electrodes 42 a and 42 b can be formed by having a metal layer mainly composed of Al at a contact portion with the bonding electrode 70.

  Further, when the n electrodes 40a to 40d and the p buffer electrodes 42a and 42b are formed from the same material, it is preferable that each electrode is formed from a metal material containing Ni or Cr and Au. In particular, when the n-side contact layer 22 is formed of n-type GaN, the n electrodes 40 a to 40 d can be formed including the Ni layer and the Au layer from the n-side contact layer 22 side. Further, the n electrodes 40a to 40d can be formed including the Cr layer and the Au layer from the n-side contact layer 22 side. When the p contact electrode 30 is formed of an oxide semiconductor, the p buffer electrodes 42a and 42b can be formed including an Ni layer and an Au layer from the p contact electrode 30 side. Further, the p buffer electrodes 42a and 42b can be formed including the Cr layer and the Au layer from the p contact electrode 30 side.

  The n-side bonding electrode 70 and the p-side bonding electrode 72 are in contact with the surface of the insulating layer 50 opposite to the p-contact electrode 30 (that is, the upper surface in FIG. 1A), and a predetermined surface of the insulating layer 50 is predetermined. Covering the area. The p-side bonding electrode 72 is formed in a substantially rectangular shape in plan view, and the n-side bonding electrode 70 is formed in a U-shape that semi-encloses the p-side bonding electrode 72 in plan view.

  The n-side bonding electrode 70 and the p-side bonding electrode 72 have a metal layer mainly made of Ti as a barrier layer at a contact portion with the insulating layer 50. Moreover, each joining electrode 70 and 72 can have a solder layer formed of a eutectic material, for example, AuSn, on the barrier layer. The solder layer can be formed by, for example, a vacuum evaporation method (for example, an electron beam evaporation method or a resistance heating evaporation method), a sputtering method, a plating method, a screen printing method, or the like. The solder layer can also be formed from eutectic solder made of a eutectic material other than AuSn or lead-free solder such as SnAgCu.

  Specifically, the barrier layer is formed on the first barrier layer in contact with the insulating layer 50, the n electrodes 40a to 40d or the p buffer electrodes 42a and 42b, and the material constituting the solder layer. And a second barrier layer that suppresses diffusion of the first barrier layer. The first barrier layer is formed of a material that forms ohmic contact with the material that forms the n-electrodes 40a to 40d and the material that forms the p-buffer electrodes 42a and 42b and has good adhesion. It is formed. The second barrier layer is formed of a material that can prevent the material constituting the solder layer from diffusing toward the n-electrodes 40a to 40d and the p-buffer electrodes 42a and 42b. It is formed.

  The barrier layer can also include a plurality of pair layers, with the first barrier layer and the second barrier layer as one pair layer. When the barrier layer includes a plurality of pair layers, diffusion of the material constituting the solder layer can be further suppressed. The film thickness of the first barrier layer of the barrier layer is, for example, about 150 nm, and the film thickness of the second barrier layer is, for example, about 100 nm or 150 nm. Furthermore, the solder layer is formed to have a thickness of 2 μm or more and 20 μm or less, for example.

  The light emitting element 1 configured as described above is a flip chip type light emitting diode (LED) that emits light having a wavelength in a blue region. For example, the light emitting element 1 emits light having a peak wavelength of 450 nm when the forward voltage is 2.9 V and the forward current is 20 mA. The light emitting element 1 is formed in a substantially square shape in plan view. For example, the vertical dimension and the horizontal dimension of the light emitting element 1 are approximately 350 μm, respectively. Since the p-buffer electrode and the n-electrode are provided on the same surface side, the light-emitting element 1 is applied to a face-up type LED and a vertical light-emitting type LED in addition to the flip-chip type LED as described above. You can also. The vertical light emitting LED is formed, for example, by forming a semiconductor multilayer structure on a growth substrate, attaching a heterogeneous substrate to the surface of the semiconductor multilayer structure on the opposite side of the growth substrate, and then removing the growth substrate.

  The layers from the buffer layer 20 to the p-side contact layer 28 provided on the sapphire substrate 10 are, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (Molecular Beam). Epitaxy (MBE), Halide Vapor Phase Epitaxy (HVPE), etc. Here, the buffer layer 20 is formed of AlN, but the buffer layer 20 can also be formed of GaN. Further, the quantum well structure of the light emitting layer 30 may be a single quantum well structure or a strained quantum well structure instead of a multiple quantum well structure.

The insulating layer 50 is formed from a metal oxide such as titanium oxide (TiO ₂ ), alumina (Al ₂ O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), or a resin material having electrical insulation properties such as polyimide. You can also And the reflective layer 60 can also be formed from Ag, and can also be formed from the alloy which contains Al or Ag as a main component. The reflective layer 60 may be a distributed Bragg reflector (DBR) formed from a plurality of layers of two materials having different refractive indexes.

  Furthermore, the light emitting element 1 may be an LED that emits light having a peak wavelength in the ultraviolet region, the near ultraviolet region, or the green region, and the peak wavelength region of the light emitted from the LED is not limited thereto. In other modified examples, the planar dimension of the light emitting element 1 is not limited to this. For example, the planar dimension of the light emitting element 1 can be designed such that the vertical dimension and the horizontal dimension are each 1 mm, and the vertical dimension and the horizontal dimension can be different from each other.

(Manufacturing process of light-emitting element 1)
2A to 2C show an example of a manufacturing process of the light-emitting element according to the first embodiment. Specifically, FIG. 2A (a) is a longitudinal sectional view before etching for exposing the surface of the n-side contact layer is performed. FIG. 2B is a longitudinal sectional view after the etching for exposing the surface of the n-side contact layer is performed. 2C is a longitudinal sectional view showing a state where a mask is formed on the p-contact electrode. Furthermore, (d) of FIG. 2A is a longitudinal cross-sectional view after etching the p-contact electrode.

  First, a sapphire substrate 10 is prepared, and a semiconductor stacked structure including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer is formed on the sapphire substrate 10. Specifically, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are formed on the sapphire substrate 10. Epitaxial growth is sequentially performed to form an epitaxial growth substrate (semiconductor laminated structure forming step).

  Subsequently, a mask 200 made of a photoresist is formed on the p-side contact layer 28 of the epitaxial growth substrate by using a photolithography technique (FIG. 2A (a)). Next, after etching a part of the region excluding the portion where the mask 200 is formed from the p-side contact layer 28 to the surface of the n-side contact layer 22, the mask 200 is removed. Thereby, a mesa portion composed of a plurality of compound semiconductor layers from the n-side cladding layer 24 to the p-side contact layer 28 is formed, and a part of the surface of the n-side contact layer 22 is exposed (FIG. 2A (b)). , Removal step). In the removal step, etching is performed to a part of the n-side contact layer 22 for the purpose of completely removing the portion from the n-side cladding layer 24 to the p-side contact layer 28 where the mask 200 is not formed.

  Thereafter, the p contact electrode 30 is formed on the entire surface of the n-side contact layer 22 and the p-side contact layer 28. That is, the p contact electrode 30 is formed so as to cover the exposed surface of the n-side contact layer 22, the side surface of the mesa portion, and the surface of the p-side contact layer 28 (that is, the upper surface of the mesa portion). In this embodiment, the p-contact electrode 30 is ITO, and can be formed by using, for example, a vacuum deposition method. Then, the p contact electrode 30 is formed so that the sheet resistance of the p contact electrode 30 is lower than the sheet resistance of the n-side contact layer 28. The p-contact electrode 30 can also be formed by a sputtering method, a CVD method, a vapor deposition method, a sol-gel method, or the like. Then, a photoresist mask 202 is formed in the region where the p-contact electrode 30 is to be left (FIG. 2A (c)). Subsequently, the p contact electrode 30 not covered with the mask 202 is etched. Thereby, the p-contact electrode 30 is formed in a predetermined region of the p-side contact layer 28 (FIG. 2A (d), p-contact electrode forming step).

  FIG. 2B (a) is a longitudinal sectional view after forming the n-electrode and the p-buffer electrode. FIG. 2B (b) is a longitudinal sectional view after forming the first insulating layer. Further, FIG. 2B (c) is a longitudinal sectional view after the reflective layer and the second insulating layer are formed.

  First, the n electrodes 40 a to 40 d are formed in a predetermined part of the surface of the n-side contact layer 22 by using a vacuum deposition method and a photolithography technique. Further, the p buffer electrodes 42a and 42b are formed in a predetermined partial region on the surface of the p contact electrode 30 provided on the p side contact layer 28 by using a vacuum deposition method and a photolithography technique (see FIG. 2B (a), electrode formation step). The material constituting the n-electrodes 40a to 40d and the material constituting the p-buffer electrodes 42a and 42b may be different from each other or the same. When both materials are the same, n electrode 40a-40d and p buffer electrode 42a, 42b can be formed simultaneously. In addition, after forming the n electrodes 40a to 40d and the p buffer electrode 42a and the p buffer electrode 42b, between the n side contact layer 22 and the n electrodes 40a to 40d, and the p contact electrode 30 and the p buffer electrode 42a, In order to ensure ohmic contact and adhesion with 42b, a heat treatment can be performed for a predetermined time at a predetermined temperature and in a predetermined atmosphere.

  Subsequently, an insulating layer 50 is formed to cover the n electrodes 40a to 40d and the p buffer electrodes 42a and 42b. Specifically, the first insulating layer 50a covering the n-side contact layer 22, the n electrodes 40a to 40d, the mesa portion, the p contact electrode 30, and the p buffer electrodes 42a and 42b is formed by plasma CVD (insulation). First insulating layer forming step in the layer forming step). Then, a reflective layer 60 is formed on the first insulating layer 50a in a predetermined region excluding the n-electrodes 40a to 40d and the p-buffer electrodes 42a and 42b using a vacuum deposition method and a photolithography technique. (FIG. 2B (b), reflective layer forming step in insulating layer forming step). Next, the second insulating layer 50b is formed using the plasma CVD method on the upper side of the reflective layer 60 formed in the step of FIG. 2B (b) and on the upper side of the portion where the reflective layer 60 is not formed. (FIG. 2B (c), second insulating layer forming step in the insulating layer forming step). As a result, the reflective layer 60 is covered with the second insulating layer 50b. The first insulating layer 50a and the second insulating layer 50b constitute the insulating layer 50 according to this embodiment.

  FIG. 2C (a) is a longitudinal sectional view after an opening is formed in a part of the insulating layer. Further, FIG. 2C (b) is a longitudinal sectional view after the barrier layer and the solder layer are formed.

  Subsequently, the upper portions of the n electrodes 40a to 40d and the upper portions of the p buffer electrodes 42a and 42b in the insulating layer 50 are removed by using a photolithography technique and an etching technique. Thereby, an opening 52 as a through hole is formed on the p buffer electrodes 42a and 42b, and an opening 52 as a through hole is formed on the n electrodes 40a to 40d (FIG. 2C (a), opening). Forming step).

  Next, a barrier layer is formed inside each opening 52 by using a vacuum deposition method and a photolithography technique (barrier layer forming step). The barrier layer formed in the opening 52 on the n electrodes 40a to 40d is electrically connected to the n electrodes 40a to 40d. The barrier layer formed in the opening 52 on the p buffer electrodes 42a and 42b is electrically connected to the p buffer electrodes 42a and 42b. Subsequently, a solder layer is formed on the barrier layer (solder layer forming step). Thereby, the joining electrode 70 which consists of a barrier layer and a solder layer is formed, and the light emitting element 1 shown to FIG. 2C (b) is manufactured.

  Each of the n electrodes 40a to 40d and the p buffer electrodes 42a and 42b can also be formed by a sputtering method. The insulating layer 50 can also be formed by chemical vapor deposition (CVD). The light emitting element 1 formed through the above steps is mounted by flip chip bonding on a predetermined position of a substrate made of ceramic or the like in which a wiring pattern of a conductive material is formed in advance. And the light emitting element 1 mounted on the board | substrate can be packaged as a light-emitting device by sealing integrally with sealing materials, such as an epoxy resin or glass.

(Effects of the first embodiment)
In the light emitting device 1 according to the present embodiment, in the light emitting device in which the n electrode and the p buffer electrode are provided on the same surface side, the number of n electrodes provided in the n side contact layer 22 having a sheet resistance higher than that of the p contact electrode 30 is p. Since the number of buffer electrodes is larger than the number of buffer electrodes, the size of the n electrode is set to, for example, a diameter of 50 μm or less for the purpose of increasing the light emitting area of the light emitting element 1 in plan view and further reducing light absorption at the electrodes. Also, an increase in the forward voltage of the light emitting element 1 can be suppressed. In addition, the light emitting element 1 can disperse the current supplied to the light emitting element 1 more uniformly in the light emitting layer 25 as compared with the case where a single n electrode is provided by providing a plurality of n electrodes. Furthermore, the electrostatic withstand voltage of the light emitting element 1 can be improved by providing a plurality of n electrodes.

  Further, since the light emitting element 1 according to the present embodiment does not require the sheet resistance of the n-side contact layer 22 to be smaller than the sheet resistance of the p-contact electrode 30, the sheet resistance of the n-side contact layer 22 is reduced. For this purpose, it is not necessary to increase the thickness of the n-side contact layer 22 and increase the carrier concentration. Therefore, due to the increase in the thickness of the n-side contact layer 22, the substrate on which the semiconductor multilayer structure is formed does not warp in the manufacturing process of the light-emitting element, and the carrier concentration increases. Thus, the surface of the semiconductor layer during epitaxial growth can be prevented from being roughened.

[Second Embodiment]
FIG. 3 shows an outline of the upper surface of the light emitting device according to the second embodiment of the present invention.

  The light emitting element 2 according to the second embodiment has substantially the same configuration and function except that the number and arrangement of electrodes are different from those of the light emitting element 1 according to the first embodiment. Therefore, a detailed description is omitted except for differences.

  The light emitting element 2 according to the second embodiment is formed in a substantially square shape in plan view, and the p buffer electrodes 42a and 42b are provided on the middle line of the square. The middle line is defined on the axis 100. The plurality of n-electrodes are provided at positions where the axis 100 is sandwiched and at the same distance from the axis 100. In the present embodiment, six n electrodes 40a to 40f and two p buffer electrodes 42a and 42b are formed, and the three n electrodes 40a to 40c are arranged on one side of the shaft 100 (the upper side in FIG. 3). Three n-electrodes 40d to 40f are arranged on the other side of the shaft 100 (the lower side in FIG. 3). For example, the upper left n-electrode 40a and the lower left n-electrode 40d are opposite to each other with the shaft 100 in between, and are provided at the same distance from the shaft 100. That is, the upper left n-electrode 40a and the lower left n-electrode 40d are provided in a line-symmetrical position with the axis 100 as the axis of symmetry and form a pair. In addition, the upper center n-electrode 40b and the lower center n-electrode 40e make a pair, and the upper-right n-electrode 40c and the lower-right n-electrode 40d also make a pair.

  In this embodiment, the p buffer electrodes 42 a and 42 b are provided at positions deviating from the intersection of the axis 100 and the line connecting the paired n electrodes. Specifically, the p buffer electrode 42a on the left side is defined by the intersection of the axis 100 and the line connecting the upper left n electrode 40a and the lower left n electrode 40d and the upper left n electrode 40a and the upper n electrode 40b. It is provided at a position shifted toward the center of the light emitting element 2 by a half distance. The p buffer electrode 42b on the right side is half the distance between the upper right n electrode 40c and the upper n electrode 40b from the intersection of the axis 100 and the line connecting the upper right n electrode 40c and the lower right n electrode 40f. It is provided at a position shifted toward the center of the light emitting element 2 by a distance.

[Third Embodiment]
FIG. 4 shows an outline of the upper surface of the light emitting device according to the third embodiment of the present invention.

  The light emitting element 3 according to the third embodiment has substantially the same configuration and function except that the number and arrangement of electrodes are different from those of the light emitting element 1 according to the first embodiment. Therefore, a detailed description is omitted except for differences.

  The light emitting element 3 according to the third embodiment is formed in a substantially square shape in plan view, and one p buffer electrode 42 is provided at the center of the square. A straight line passing through the p buffer electrode 42 and parallel to one side of the square (for example, the middle line of the square) is defined as the axis 100. The plurality of n-electrodes are provided at positions where the axis 100 is sandwiched and at the same distance from the axis 100. In the present embodiment, four n electrodes 40a to 40d are provided. For example, the upper left n electrode 40a and the lower left n electrode 40c are at positions opposite to each other with the axis 100 in between, and the distance from the axis 100 is One pair is provided at the same position. In other words, the upper left n-electrode 40a and the lower left n-electrode 40c are provided in line-symmetric positions with the axis 100 as the axis of symmetry. The relationship between the upper right n-electrode 40b and the lower right n-electrode 40d is the same. Furthermore, in the present embodiment, the upper left n electrode 40a, the lower right n electrode 40d, the upper right n electrode 40b, and the lower left n electrode 40c are provided at point-symmetrical positions with the p buffer electrode 42 as the center of symmetry.

[Fourth Embodiment]
FIG. 5 shows an outline of the upper surface of a light emitting device according to the fourth embodiment of the present invention.

  The light emitting element 4 according to the fourth embodiment has substantially the same configuration and function except that the number and arrangement of electrodes are different from those of the light emitting element 1 according to the first embodiment. Therefore, a detailed description is omitted except for differences.

  The light emitting element 4 according to the fourth embodiment is formed in a substantially square shape in plan view, and a plurality of p buffer electrodes are provided on each of the first axis 102 and the second axis 104 that divide one side of the square into three equal parts. It is done. Specifically, two p buffer electrodes 42a and 42b are provided on the first shaft 102 extending left and right to form one group, and two p buffer electrodes 42c and 42d are provided on the second shaft 104 extending left and right. Form a group. The plurality of n-electrodes are provided at positions where the first axis 102 or the second axis 104 is sandwiched and at the same distance from the first axis 102 or the second axis 104. Specifically, three n electrodes are arranged side by side on the left and right above the first shaft 102, between the first shaft 102 and the second shaft 104, and below the second shaft 104. For example, the upper left n-electrode 40a and the middle left n-electrode 40d are located at positions opposite to each other with the first axis 102 in between, and the distance from the first axis 102 is the same. That is, the upper left n-electrode 40a and the middle left n-electrode 40d are provided in a line-symmetrical position with the first axis 102 as the axis of symmetry to form a pair. In the present embodiment, the n electrodes forming a pair in the case where the n electrodes form “one pair” refer to n electrodes provided at the shortest distance from a certain axis.

  Similarly, the upper middle n-electrode 40b, the middle middle n-electrode 40e, the upper right n-electrode 40c, and the middle right n-electrode 40f are provided in line-symmetric positions with the first axis 102 as the symmetry axis. It is done. Then, the upper middle n electrode 40b and the middle middle n electrode 40e form a pair, and the upper right n electrode 40c and the middle right n electrode 40f form a pair. Similarly, the middle left n-electrode 40d, the lower left n-electrode 40g, the middle middle n-electrode 40e, the lower middle n-electrode 40h, the middle right n-electrode 40f and the lower right n-electrode 40i are respectively The second axis 104 is provided at a line-symmetrical position with respect to the axis of symmetry, and each forms a pair.

  Further, in the present embodiment, the p buffer on the first axis 102 is located at a position deviated from the intersection of the first axis 102 and a line connecting n electrodes provided at line-symmetric positions with the first axis 102 as the axis of symmetry. Electrodes 42a and 42b are provided. The same applies to the p buffer electrodes 42c and 42d on the second shaft 104.

[Fifth Embodiment]
FIG. 6A shows an outline of the upper surface of the light emitting device according to the fifth embodiment of the present invention, and FIG. 6B shows a modification of the light emitting device according to the fifth embodiment of the present invention. An outline of the top surface of is shown.

  The light emitting elements 5 and 6 according to the fifth embodiment have substantially the same configuration and function except that the light emitting element 1 according to the first embodiment has a different element shape in plan view. Therefore, a detailed description is omitted except for differences.

  Referring to FIG. 6A, the light emitting element 5 according to the fifth embodiment is formed in a substantially rectangular shape in plan view. The p buffer electrode 42 is provided at a position corresponding to the intersection of the two diagonal lines of the rectangle. Here, a line parallel to the short side of the rectangle and passing through the p buffer electrode 42 is defined as the axis 100. Two n-electrodes 40a and 40b are provided at positions symmetrical with respect to the axis 100 as a symmetry axis. In the fifth embodiment, the n electrodes 40a and 40b and the p buffer electrode 42 are provided linearly.

  6B, the light emitting element 6 according to the modification of the fifth embodiment is formed in a substantially rectangular shape in plan view. And four p buffer electrodes 42a-42d are linearly provided on the middle line of this rectangular short side. A total of eight n-electrodes 40 a to 40 h are provided at symmetrical positions with respect to the axis 106, with this middle line as the symmetrical axis 106. In the modification of the fifth embodiment, the two n electrodes and the p buffer electrode forming a pair are provided linearly.

  While the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

1, 2, 3, 4, 5, 6 Light-emitting element 10 Sapphire substrate 20 Buffer layer 22 n-side contact layer 23 n-type semiconductor layer 24 n-side cladding layer 25 light-emitting layer 26 p-side cladding layer 27 p-type semiconductor layer 28 p-side Contact layer 30 p contact electrode 40a, 40b, 40c, 40d, 40en electrode 40f, 40g, 40h, 40in electrode 42a, 42b, 42c, 42d p buffer electrode 50 insulation layer 50a first insulation layer 50b second insulation Layer 52 Opening 60 Reflective layer 70 Joining electrode 70a, 70b, 70c Joining electrode 71 Joining electrode 72, 72a, 72b Joining electrode 100, 102, 104, 106 Axis 200, 202 Mask

Claims (6)

A first conductive type first semiconductor layer, a light emitting layer, and a second conductive type second semiconductor layer different from the first conductive type are stacked, and the second semiconductor layer and a part of the light emitting layer are formed. A semiconductor multilayer structure made of a nitride compound semiconductor that has been removed to expose the first semiconductor layer;
A p-contact electrode in ohmic contact with the second semiconductor layer;
A point-like second electrode in ohmic contact with the p-contact electrode;
A light emitting device comprising: a plurality of point-like first electrodes that are in ohmic contact with an exposed portion of the first semiconductor layer and are larger in number than the second electrodes. The first semiconductor layer is an n-type semiconductor layer;
The second semiconductor layer is a p-type semiconductor layer;
The light emitting device according to claim 1, wherein the n-type semiconductor layer has a sheet resistance higher than a sheet resistance of the p-contact electrode. The first electrode is an n-electrode, the second electrode is a p-buffer electrode,
The light emitting device according to claim 2, wherein there are a plurality of portions having a shortest distance in plan view between the n electrode and the p buffer electrode.   4. The light emitting device according to claim 3, wherein the plurality of n electrodes form at least one pair provided at a line-symmetrical position with an axis passing through the p-buffer electrode as a symmetry axis in plan view. A plurality of the p buffer electrodes form at least one group arranged linearly on the p contact electrode;
The light emitting device according to claim 4, wherein the plurality of n electrodes are provided at positions symmetrical with respect to the symmetry axis. One p buffer electrode is provided on the p contact electrode,
The light emitting element according to claim 3, wherein the plurality of n electrodes are provided at point-symmetrical positions with the p buffer electrode as a center of symmetry.

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