JP2011061438A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor which scalably changes imaging points. <P>SOLUTION: Image data obtained from a plurality of imaging apparatuses 20-1 to 20-n are temporarily held in a plurality of FIFOs 112-1 to 112-n constructed on an FPGA. A register part 114 receives synchronizing signals from the imaging apparatuses 20-1 to 20-n. On receipt of the synchronizing signal from the imaging apparatus that has started imaging last, the register part 114 outputs an output start signal to a control part 115. The control part 115 outputs the image data in a predetermined order from the FIFOs 112-1 to 112-n when the output start signal is received. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus that is used in, for example, a security system using a plurality of imaging devices, acquires image data from the plurality of imaging devices, and performs image processing on the image data.

  In recent years, security systems using image data acquired by an imaging device such as a camera have been used in plants, stations, airports, stores, and the like. This type of security system comprehensively monitors a monitoring area with a plurality of imaging devices. At this time, the security system automatically reduces the burden on the monitoring personnel in the central monitoring room by automatically processing image data from a plurality of imaging devices.

  By the way, in the conventional security system, each image data picked up by a plurality of image pickup devices is received by the image processing device. The image processing apparatus includes a plurality of image acquisition units and image processing units using a decoder or the like. Each piece of image data captured by a plurality of imaging devices is received by a plurality of image acquisition units. Each image data is automatically subjected to image processing by an image processing unit. At this time, the upper limit of the number of physical wires that can be connected is determined for LSI (Large Scale Integration) such as CPU (Central Processing Unit) and FPGA (Field Programmable Gate Array) used in the image processing unit. Therefore, the number of image data that can be transmitted to the image processing unit is limited.

  In order to solve this problem, a memory that temporarily stores data output from the image acquisition unit to the image processing unit is installed in the security system, and the data stored in the memory is controlled by the CPU of the image processing unit. A method of sequentially outputting images to an image processing unit has been proposed (for example, see Patent Document 1). However, in this method, when a plurality of imaging devices are connected, the access time to the memory is longer than the number of imaging devices. For this reason, there is a possibility that the output of image data from all the imaging devices to the image processing unit is not completed within the time expected by the image processing unit.

  Note that, in the facilities such as the plant, the station, the airport, and the store described above, the monitoring area is vast, and the security level in the monitoring area changes with time. In addition, there are cases where the number of image pickup devices is increased step by step due to the annual budget. Thus, in the security system, there is a demand for changing the number of imaging points to be scalable.

Japanese Patent Laid-Open No. 11-65722

  As described above, in the conventional security system, the operation may be limited depending on the number of connected imaging devices. For this reason, it has been difficult to change the number of imaging points in a scalable manner in order to improve the security level.

  This invention is made | formed by the said situation, The objective is to provide the image processing apparatus which can change the number of imaging points scalable.

  To achieve the above object, an image processing apparatus according to the present invention is an image processing apparatus that processes a plurality of image data captured by a plurality of image capturing apparatuses, each of which temporarily stores one of the plurality of image data. A plurality of holding units that output the image data in response to an output instruction, and a plurality of synchronization signals generated when the plurality of imaging devices start imaging, out of the plurality of synchronization signals A register unit that generates an output start signal when receiving the last synchronization signal, and a control unit that gives the output instruction in a preset output order to the plurality of holding units in response to the output start signal; Is provided on an FPGA (Field Programmable Gate Array), and an image processing unit that performs image processing on the image data output from the plurality of holding units according to the output instruction. .

  In the image processing apparatus having the above configuration, image data from a plurality of imaging apparatuses is temporarily held by a plurality of FIFOs constructed on an FPGA. Then, based on the arrival timing of the synchronization signal from the imaging device, the image data is output from the FIFO in a predetermined order. As a result, the image processing apparatus can virtually consider a plurality of imaging devices as a single imaging device.

  According to the present invention, it is possible to provide an image processing apparatus that can increase the number of imaging points in a scalable manner.

It is a block diagram which shows the function structure of the security system which concerns on the 1st Embodiment of this invention. It is a figure which shows the process in the image acquisition part of FIG. FIG. 2 is a block diagram illustrating a security system when a plurality of crystal oscillators are connected to the image acquisition unit of FIG. 1. FIG. 2 is a block diagram showing a security system when a configuration ROM is connected to each of the image acquisition unit and the image processing unit in FIG. 1. FIG. 2 is a block diagram showing a security system when a configuration ROM and a damping resistor are connected to the image acquisition unit of FIG. 1 and a configuration ROM is connected to the image processing unit. It is a block diagram which shows the function structure of the security system which concerns on the 2nd Embodiment of this invention. It is a figure which shows the process in the image acquisition part of FIG. FIG. 7 is a block diagram illustrating a security system in a case where the image acquisition unit in FIG. 6 does not have a FIFO and has an external memory.

  Embodiments of an image processing apparatus according to the present invention will be described below in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a functional configuration of a security system according to the first embodiment of the present invention. The security system in FIG. 1 includes an image processing device 10 and imaging devices 20-1 to 20-n.

  The imaging devices 20-1 to 20-n are cameras or the like, and acquire moving images as image data every predetermined time (for example, every 1/30 seconds, every 1/60 seconds, etc.). Then, the imaging devices 20-1 to 20-n sequentially output the acquired image data to the image processing device 10. The imaging devices 20-1 to 20-n generate a synchronization signal when imaging is started. The imaging devices 20-1 to 20-n output this synchronization signal to the image processing device 10. Note that the amount of output data from the imaging device 20 is wide from 1920 × 1440 pixels to 320 × 240 pixels per frame. Various image output information exists including the presence or absence of color information. Furthermore, in recent years, it is also possible to output fine information by complementing missing data between pixels such as super resolution. For this reason, the image data output from the imaging device has a characteristic that the number of output data expands and contracts depending on the state of the imaging target. Here, the number of output data refers to the number of pixels, the frame rate, and the like.

  An image processing apparatus 10 in FIG. 1 includes an image acquisition unit 11, a crystal oscillator 12, an image processing unit 13, and connectors 14-1 to 14-n (n is a natural number). The crystal oscillator 12 is connected to the image acquisition unit 11 by a PLL (Phase Locked Loop) provided in the image acquisition unit 11.

  The image acquisition unit 11 includes an FPGA (Field Programmable Gate Array). The image acquisition unit 11 includes input interface (IF) units 111-1 to 111-n, first-in first-out (FIFO) 112-1 to 112-n, and output IF by incorporating a logic circuit on the FPGA. The function of the unit 113, the register unit 114, and the control unit 115 is provided.

  The input IF units 111-1 to 111-n output the image data input via the connectors 14-1 to 14-n to the FIFOs 112-1 to 112-n. Further, the input IF units 111-1 to 111-n output the synchronization signal input via the connectors 14-1 to 14-n to the register unit 114.

  The FIFOs 112-1 to 112-n temporarily hold the image data from the input IF units 111-1 to 111-n. Then, the FIFOs 112-1 to 112-n output the held image data to the image processing unit 13 via the output IF unit 113 in the order of input in accordance with an output instruction from the control unit 115. The transmission bit rate of the image data output at this time is based on the clock signal generated by the crystal oscillator 12.

  The register unit 114 receives the synchronization signal from the input IF units 111-1 to 111-n. When receiving the synchronization signal, the register unit 114 sets a bit so that it can be understood from which of the imaging devices 20-1 to 20-n the received synchronization signal is output. Then, the register unit 114 outputs an output start signal to the control unit 115 when receiving a synchronization signal from the imaging device that has started imaging.

  The control unit 115 gives an output instruction to the FIFOs 112-1 to 112-n according to the output start signal from the register unit 114. At this time, the order in which the control unit 115 gives the output instruction is set in advance.

  The control unit 115 also designates the output capacity of the image data for each of the FIFOs 112-1 to 112-n and gives an output instruction. The output capacity is determined by the number of the imaging devices 20-1 to 20-n connected to the FIFOs 112-1 to 112-n and the number of output data.

  The image processing unit 13 is an LSI such as a CPU or FPGA. The image processing unit 13 detects the image data from the image acquisition unit 11 at a preset frequency. Then, the image processing unit 13 performs image processing on the detected image data. In the present embodiment, the preset frequency is a frequency corresponding to the clock frequency of the crystal oscillator 12. Note that the image processing unit 13 may receive the transmission bit rate from the image acquisition unit 11 and detect video data according to the transmission bit rate.

  Next, the operation in the above configuration will be described.

  FIG. 2 is a schematic diagram showing processing in the image acquisition unit 11 of the image processing apparatus 10 according to the first embodiment of the present invention. FIG. 2 illustrates an example in which image data is transferred by the raster scan method. Note that the data transfer method of the present embodiment is not limited to the raster scan method.

  In FIG. 2, an example in which the imaging devices 20-1 to 20-n are connected to the image processing device 10 and the imaging device 20-2 starts imaging processing last will be described.

  When imaging with the imaging device 20-1 is started, image data 1 is acquired and a synchronization signal 1 is generated. The image data 1 and the synchronization signal 1 are output to the image acquisition unit 11. The FIFO 112-1 holds the image data 1. The register unit 114 receives the synchronization signal 1 and sets a bit indicating that the synchronization signal 1 from the imaging device 20-1 has been received.

  When imaging with the imaging device 20-n is started, image data N is acquired and a synchronization signal N is generated. The image data N and the synchronization signal N are output to the image acquisition unit 11. The FIFO 112-n holds image data N. The register unit 114 receives the synchronization signal N and sets a bit indicating that the synchronization signal N from the imaging device 20-n has been received.

  Then, when imaging with the last imaging device 20-2 is started, image data 2 is acquired and a synchronization signal 2 is generated. The image data 2 and the synchronization signal 2 are output to the image acquisition unit 11. The FIFO 112-2 holds the image data 2. Further, the register unit 114 receives the synchronization signal 2 and sets a bit indicating that the synchronization signal 2 from the last imaging device 20-2 has been received. When receiving the last synchronization signal 2, the register unit 114 generates an output start signal and outputs the output start signal to the control unit 115.

  When receiving the output start signal, the control unit 115 issues an output instruction to the FIFO 112-1 to output the image data 11 on the first scanning line of the image data 1. Subsequently, the control unit 115 sequentially instructs the FIFOs 112-2, 112-3, 112-4... To output the video data on the first scanning line of the image data 2, 3, 4. put out. Then, the control unit 115 gives an output instruction to the FIFO 112-n so as to output the image data N1 on the first scanning line of the image data N, and when the image data N1 is output from the FIFO 112-n, An output instruction is given to the FIFO 112-1 to output the video data 12 on the second scanning line of the image data 1. In this embodiment, an example has been described in which an output instruction is first given to the FIFO 112-1, and then the output instructions are given in the order of FIFOs 112-2, 112-3,..., 112-n. The order of giving the output instruction and the order of giving the output instruction are not limited to this.

  As described above, the image acquisition unit 11 outputs the image data 1 to N to the image processing unit 13 in units of scanning lines. Thereby, the image processing unit 13 receives the video data captured by the imaging devices 20-1 to 20-n in order from the first stage of the scanning line. At this time, the image processing unit 13 receives a video in which videos captured by the imaging devices 20-1 to 20-n are horizontally arranged as shown in FIG.

  As described above, in the first embodiment, the image acquisition unit 11 temporarily holds the image data from the imaging devices 20-1 to 20-n using the FIFOs 112-1 to 112-n. Then, the image acquisition unit 11 sequentially outputs image data from the FIFOs 112-1 to 112-n in a predetermined order using the arrival timing of the synchronization signal. Thereby, in the image processing apparatus 10, it becomes possible to regard a plurality of imaging devices virtually as one imaging device.

  In the first embodiment, the image acquisition unit 11 is constructed with an FPGA. Thereby, even after the image processing apparatus 10 is created, it is possible to easily cope with various situations by reconfiguring the FPGA. That is, it is possible to reset the order of the FIFO that gives the output instruction first and the FIFO that gives the output instruction. In addition, the output capacity of image data output from the FIFO can be reset according to the number of output data of the connected imaging device. Further, according to the number of connected imaging devices, the image acquisition unit 11 can be newly provided with functions such as an input IF unit, an output IF unit, and a FIFO.

  In the first embodiment, output of image data from the FIFO is started when a synchronization signal is received from the imaging device that started imaging last. As a result, even when the number of frames and the generation of the synchronization signal of the plurality of connected imaging devices are different, these imaging devices can be virtually regarded as one imaging device.

  In the first embodiment, the image acquisition unit 11 has a number of FIFOs corresponding to the number of connected imaging devices. As a result, the access time to the FIFO is minimized.

  In the first embodiment, the number of physical wires to the image processing unit 13 is single. Therefore, it is possible to mount an arithmetic processing LSI (CPU, FPGA, ASIC, DSP) having a small image processing unit package size. Thereby, the manufacturing cost of the image processing apparatus 10 can be suppressed.

  Therefore, the image processing apparatus according to the present invention has expandability. That is, the user of the security system can increase the number of imaging points in a scalable manner.

  Note that the image processing apparatus 10 of the present embodiment is not limited to the configuration shown in FIG. For example, you may have the structure shown in FIGS.

  FIG. 3 is a block diagram showing a security system when a plurality of crystal oscillators 12-1 to 12-3 are connected to the image acquisition unit 11. The user of the security system selects a crystal oscillator having an appropriate clock frequency from among the crystal oscillators 12-1 to 12-3 according to the number of connected imaging apparatuses 20, the number of output data, and the output data format. At this time, the clock frequencies of the crystal oscillators 12-1 to 12-3 are different from each other. For example, the clock frequency of the crystal oscillator 12-1 is 27 MHz, the clock frequency of the crystal oscillator 12-2 is 54 MHz, and the crystal oscillator 12 -3 clock frequency is 108 MHz. The user reconfigures the FPGA of the image acquisition unit 11 according to the selected clock frequency of the crystal oscillator. The image acquisition unit 11 notifies the image processing unit 13 of the bit rate changed by the reconfiguration.

  As a result, the image processing apparatus 10 can scale the data transmission timing of the image data output from the image acquisition unit 11 to the image processing unit 13 according to the number of connected imaging devices 20, the number of output data, and the output data format. It becomes possible to fluctuate. Along with this, it is possible to reduce the power consumption and suppress the generation of unnecessary electromagnetic noise.

  FIG. 4 is a block diagram showing a security system when a configuration ROM (Read Only Memory) 15 is connected to the image acquisition unit 11 and a configuration ROM 16 is connected to the image processing unit 13. In the configuration ROM 15, a data conversion format for reconfiguring the logic circuit of the image acquisition unit 11 is recorded in advance. For example, in the configuration ROM 15, when the number of imaging devices 20 to be connected is changed from n to (n + 1), the image acquisition unit 11 assigns its own logic circuit to the input IF unit 111-(n + 1) and the FIFO 112-( A format for automatically reconfiguring to have n + 1) is recorded.

  In addition, a data conversion format for reconfiguring the logic circuit of the image processing unit 13 is recorded in the configuration ROM 16 in advance. For example, the configuration ROM 16 records a format for switching the detection timing of image data. The detection timing of the image data in the image processing unit 13 is, for example, a state in which data is detected both when the rectangular wave rises and falls from a state where the data is detected only when the rectangular wave rises in the data. Switch to.

  According to the image processing apparatus 10 according to FIG. 4, it is possible to automatically reconfigure the FPGA even when the number of connected imaging apparatuses is changed.

  FIG. 5 is a block diagram showing a security system when a configuration ROM (Read Only Memory) 15 and a damping resistor 17 are connected to the image acquisition unit 11 and a configuration ROM 16 is connected to the image processing unit 13. By connecting the damping resistor 17 to the image acquisition unit 11, it is possible to cope with the pattern wiring resistance generated when the transmission bit rate and the clock frequency are changed.

[Second Embodiment]
FIG. 6 is a block diagram showing a functional configuration of the security system according to the second embodiment of the present invention. The security system in FIG. 6 includes an image processing device 30 and imaging devices 20-1 to 20-n.

  The imaging devices 20-1 to 20-n sequentially output the acquired image data to the image processing device 30. In addition, the imaging devices 20-1 to 20-n output the synchronization signal generated when imaging is started to the image processing device 30.

  The image processing apparatus 30 in FIG. 6 includes image acquisition units 31-1 to 31-n (n is a natural number), a crystal oscillator 32, an image processing unit 33, and connectors 34-1 to 34-n. The crystal oscillator 32 is connected to the image acquisition units 31-1 to 31-n by PLL (Phase Locked Loop) provided in the image acquisition units 31-1 to 31-n, respectively.

  The image acquisition units 31-1 to 31-n are made of FPGA. The image acquisition units 31-1 to 31-n include input IF units 311-1 to 311-n, FIFOs 312-1 to 312-n, and output IF units 313-1 to 313 by incorporating a logic circuit on the FPGA. -N, functions of register units 314-1 to 314-n and control units 315-1 to 315-n. Here, since the image acquisition units 31-1 to 31-n have the same configuration, the image acquisition unit 31-1 will be described below as a representative.

  The input IF unit 311-1 outputs the image data input via the connector 34-1 to the FIFO 312-1. The input IF unit 311-1 outputs the synchronization signal from the imaging devices 20-1 to 20-n input via the connectors 34-1 to 34-n to the register unit 314-1. These synchronization signals have identifiers that can identify which one of the imaging devices 20-1 to 20-n is generated.

  The FIFO 312-1 temporarily holds the image data from the input IF unit 311-1. Then, the FIFO 312-1 outputs the image data to the image processing unit 33 via the output IF unit 313-1 in the order in which the image data is held in response to an output instruction from the control unit 315-1. The transmission bit rate of the image data output at this time depends on the clock signal generated by the crystal oscillator 32.

  The register unit 314-1 receives the synchronization signal from the input IF unit 311-1. When the register unit 314-1 receives the synchronization signal, the register unit 314-1 sets a bit so that it can be understood which of the imaging devices 20-1 to 20-n has generated the received synchronization signal. The register unit 314-1 outputs an output start signal to the control unit 315-1 when receiving a synchronization signal from the imaging device that has started imaging last.

  When receiving the output start signal from the register unit 314-1, the control unit 315-1 gives an output instruction to the FIFO 312-1 based on the output start signal. At this time, the order of image data output from the FIFOs 312-1 to 312-n is set in advance. The control units 315-1 to 315-n give output instructions to the FIFOs 312-1 to 312-n in the order according to the output order of the image data.

  The control unit 315-1 also designates the output capacity of the image data output from the FIFO 312-1 and gives an output instruction. The output capacity is determined by the number of output data of the imaging device 20-1 connected to the FIFO 312-1.

  The image processing unit 33 is an LSI such as a CPU or FPGA. The image processing unit 33 detects the video data from the image acquisition units 31-1 to 31-n at a preset frequency. Then, the image processing unit 33 performs image processing on the acquired image data. In the present embodiment, the preset frequency is a frequency corresponding to the clock frequency of the crystal oscillator 32.

  Next, the operation in the above configuration will be described.

  FIG. 7 is a schematic diagram illustrating processing in the image acquisition units 31-1 to 31-n of the image processing device 30 according to the second embodiment of the present invention. FIG. 7 illustrates an example in which image data is transferred by the raster scan method. Note that the data transfer method of the present embodiment is not limited to the raster scan method.

  In FIG. 7, the case where the imaging devices 20-1 to 20-n are connected to the image processing device 30 and the imaging device 20-2 starts the imaging process last is described as an example.

  When imaging with the imaging device 20-1 is started, image data 1 is acquired and a synchronization signal 1 is generated. The image data 1 is output to the image acquisition unit 31-1, and the synchronization signal 1 is output to the image acquisition units 31-1 to 31-n. The FIFO 312-1 holds the image data 1. The register units 314-1 to 314-n receive the synchronization signal 1 and set a bit indicating that the synchronization signal 1 from the imaging device 20-1 has been received.

  When imaging with the imaging device 20-n is started, image data N is acquired and a synchronization signal N is generated. The image data N is output to the image acquisition unit 31-n, and the synchronization signal N is output to the image acquisition units 31-1 to 31-n. The FIFO 312-n holds the image data N. Also, the register units 314-1 to 314-n receive the synchronization signal N and set a bit indicating that the synchronization signal N from the imaging device 20-n has been received.

  Then, when imaging with the last imaging device 20-2 is started, image data 2 is acquired and a synchronization signal 2 is generated. The image data 2 is output to the image acquisition unit 31-2, and the synchronization signal 2 is output to the image acquisition units 31-1 to 31-n. The FIFO 312-2 holds the image data 2. The register units 314-1 to 314-n receive the synchronization signal 2 and set a bit indicating that the synchronization signal 2 from the last imaging device 20-2 has been received. Upon receipt of the last synchronization signal 2, the register units 314-1 to 314-n generate output start signals and output them to the control units 315-1 to 315-n arranged in the respective image acquisition units.

  When receiving the output start signal, the control unit 315-1 issues an output instruction to the FIFO 312-1 so that the image data 11 on the first scanning line of the image data 1 is output. Subsequently, the control unit 315-2 issues an output instruction to the FIFO 312-2 so that the image data 12 on the first scanning line of the image data 2 is output. Subsequently, the control units 315-3, 315-4,... 315-n output the FIFO 312-3, 312-4,... 312- so that the video data on the first scanning line of the image data 3, 4,. Output instructions are sequentially given to n.

  Then, when the image data N1 is output from the FIFO 312-n, the control unit 315-1 instructs the FIFO 312-1 to output the image data 12 on the first scanning line of the image data 1. give. In the present embodiment, first, the control unit 315-1 gives an output instruction to the FIFO 312-1, and then the control units 315-2, 315-3,... 315-n receive the FIFOs 312-2, 312-3, .., 312 -n, an example in which output instructions are given has been described. However, the order in which FIFOs are first given and output instructions are not limited to this.

  The control units 315-1 to 315-n output the video data on the scanning lines in order from the first stage by outputting the video data from the FIFOs 312-1 to 312-n as described above.

  Accordingly, the image processing unit 33 sequentially receives the video data captured by the imaging devices 20-1 to 20-n from the first stage of the scanning line. At this time, the image processing unit 33 receives a video in which video images captured by the imaging devices 20-1 to 20-n are horizontally arranged as illustrated in FIG.

  As described above, in the second embodiment, the image acquisition units 31-1 to 31-n are each configured with an FPGA. For this reason, it is not necessary to prepare a large FPGA, and the manufacturing cost of the image processing apparatus 30 can be further suppressed.

  Note that the image processing apparatus 30 of the present embodiment is not limited to the configuration shown in FIG. For example, the configuration shown in FIG. 8 may be used.

  FIG. 8 is a block diagram showing a security system when the image acquisition units 31-1 to 31-n do not have the FIFOs 312-1 to 312-n but have the external memories 316-1 to 316-n. By substituting the FIFO with the external memories 316-1 to 316-n, it becomes unnecessary to construct the FIFO on the FPGA, so that the manufacturing cost can be further reduced.

[Other Embodiments]
The present invention is not limited to the above embodiments. For example, in each of the above-described embodiments, an example in which image data is sequentially output from the FIFO when a synchronization signal is received from an imaging device that has started imaging has been described. However, the present invention is not limited to the above-described embodiment. is not. For example, a timer may be connected to the image acquisition unit, and image data may be sequentially output from the FIFO when a certain time has elapsed. At this time, the imaging device that has not generated the synchronization signal is treated as being absent, and the image data output from the image acquisition unit to the image processing unit does not include an image from the imaging device.

  Furthermore, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

DESCRIPTION OF SYMBOLS 10 ... Image processing apparatus 11 ... Image acquisition part 111-1 to 111-n ... Input IF part 112-1 to 112-n ... FIFO
113 ... Output IF unit 114 ... Register unit 115 ... Control units 12, 12-1, 12-2, 12-3 ... Crystal oscillator 13 ... Image processing units 14-1 to 14-n ... Connectors 15, 16 ... Configuration ROM
17 ... Damping resistors 20-1 to 20-n ... Imaging device 30 ... Image processing devices 31-1 to 31-n ... Image acquisition units 311-1 to 311-n ... Input IF units 312-1 to 312-n ... FIFO
313-1 to 313-n. Output IF units 314-1 to 314-n. Register units 315-1 to 315-n. Control units 316-1 to 316-n. External memory 32. Crystal oscillator 33. Image processing unit. 34-1 to 34-n connector

Claims (9)

In an image processing device that processes a plurality of image data captured by a plurality of imaging devices,
A plurality of holding units each temporarily holding one of the plurality of image data and outputting the image data in response to an output instruction;
A plurality of synchronization signals generated when the plurality of imaging devices start imaging, and a register unit that generates an output start signal when receiving the last synchronization signal among the plurality of synchronization signals;
An image acquisition means comprising, on an FPGA (Field Programmable Gate Array), a control unit that gives the output instructions in a preset output order to the plurality of holding units in response to the output start signal;
An image processing apparatus comprising: an image processing unit that performs image processing on image data output from the plurality of holding units according to the output instruction. In an image processing device that processes a plurality of image data captured by a plurality of imaging devices,
A plurality of image acquisition units that sequentially output the acquired image data so that each of the plurality of image data is acquired and the plurality of image data is output in a preset output order;
An image processing unit that performs image processing on image data from the plurality of image acquisition units,
The image acquisition unit
A holding unit that temporarily holds one of the plurality of image data and outputs the image data to the image processing unit in response to an output instruction;
When configured on an FPGA (Field Programmable Gate Array) and receiving a plurality of synchronization signals generated when the plurality of imaging devices start imaging, and receiving the last synchronization signal among the plurality of synchronization signals, A register unit for generating an output start signal;
An image is provided on the FPGA, and includes a control unit that gives the output instruction to the holding unit so that the image data is output according to the output order in accordance with the output start signal. Processing equipment. 3. The control unit according to claim 1, wherein the control unit gives an output instruction to the holding unit so that image data having a capacity corresponding to a characteristic of the connected imaging device is output. The image processing apparatus described. A timer that starts counting when receiving the first synchronization signal among the plurality of synchronization signals;
3. The control unit according to claim 1, wherein, even if the output start signal is not generated, the control unit gives the output instruction when the count value of the timer reaches a preset count value. 4. An image processing apparatus according to claim 1. A plurality of crystal oscillators each having a unique clock frequency;
The image acquisition means outputs the image data to the image processing unit at a bit rate based on a clock frequency of a first crystal oscillator selected from the plurality of crystal oscillators. The image processing apparatus described. When the image processing unit is made of FPGA,
A first configuration ROM prerecorded with a first conversion format for resetting the configuration of the image acquisition means;
A second configuration ROM in which a second conversion format for resetting the configuration of the image processing unit is preset, and
The image acquisition means, when the setting of at least one of the plurality of imaging devices is changed, reset the configuration based on the first conversion format,
2. The image processing according to claim 1, wherein when the configuration of the image acquisition unit is reset, the image processing unit resets the configuration based on the second conversion format. 3. apparatus. When the image processing unit is made of FPGA,
A plurality of crystal oscillators each having a unique clock frequency;
A first configuration ROM prerecorded with a first conversion format for resetting the configuration of the image acquisition means;
A second configuration ROM in which a second conversion format for resetting the configuration of the image processing unit is preset, and
The image acquisition means, when any one of the plurality of crystal oscillators is selected, reset the configuration based on the first conversion format,
The image processing apparatus according to claim 1, wherein when the configuration of the image acquisition unit is reset, the image processing unit resets the configuration based on the second conversion format. Further comprising a damping resistor,
The image processing apparatus according to claim 5, wherein the image acquisition unit corresponds to a pattern wiring resistance accompanying a change in a bit rate and a clock frequency by the damping resistance. The image processing apparatus according to claim 2, wherein the holding unit is configured on an FPGA.

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