JP2011041114A - Image reading apparatus, and image processing method - Google Patents

Abstract

A technique for suppressing an increase in circuit scale and cost due to rearrangement of image data input in parallel is provided as much as possible.
An image reading apparatus including a line image sensor having a plurality of channels, a storage unit storing image data for at least one line, and a predetermined image for image data output in parallel from each of the plurality of channels. An image processing unit that performs processing in parallel and outputs, and an image processing unit that is provided in the subsequent stage so that each of the image data output in parallel from the image processing unit is in the order of arrangement of a plurality of channels in the line image sensor A rearrangement processing unit for writing image data to the storage unit.
[Selection] Figure 1

Description

  The present invention relates to an image reading apparatus and an image processing method for processing image data read by an image sensor.

  2. Description of the Related Art Scanners equipped with line image sensors such as CIS and CCD, and image reading devices such as copiers and multifunction machines equipped with such scanners are known. In addition, a line image sensor (particularly, CIS) that includes a plurality of sensor units (also referred to as blocks and channels) arranged in the main scanning direction and outputs image data read by each sensor unit in parallel is mounted. An image reading apparatus is known (for example, Patent Document 1).

  Image data output in parallel from each sensor unit is an image processing unit (for example, image processing) that is mounted inside the image reading apparatus and performs predetermined image processing (for example, shading correction, gamma correction, filtering, and enlargement / reduction). ASIC (Application Specific Integrated Circuit), controller, etc.). Note that conversion from analog data to digital data is performed by a circuit such as an AFE (Analog Front End) provided at the front stage of the image processing unit, for example.

JP 2007-74400 A

  By the way, if the image processing unit is configured so that the image data output in parallel from the line image sensor is processed in parallel as it is, the structure becomes complicated, and the circuit scale and manufacturing cost tend to increase. Therefore, in general, the image data output in parallel from each sensor unit is first rearranged in the data order in the main scanning direction in the line image sensor, and then various image processing is performed on the image data in that order. The image processing unit is configured such that

  As a method for rearranging the image data, for example, an internal memory for storing image data for at least one line is provided in the image processing unit, and the parallel input image data is converted into the data order in the main scanning direction of the line image sensor. As described above, there is a method of once storing in the memory. Further, for example, an area for storing image data for at least one line is secured in an external memory outside the image processing unit, and the image data input in parallel is arranged in the data order in the main scanning direction of the line image sensor. There is a method of once storing in the memory. Note that subsequent image processing is performed by sequentially reading the image data stored in the memory.

  However, in the former method, since it is necessary to provide an internal memory for data rearrangement in the image processing unit, the circuit scale and manufacturing cost increase. Further, in the latter method described above, since it is necessary to access an external memory for data rearrangement, traffic between the image processing unit and the external memory increases. In order not to reduce the processing speed even if the traffic increases, it is necessary to widen the bus width and the like, which increases the circuit scale and manufacturing cost.

  Accordingly, an object of the present invention is to provide a technique for suppressing an increase in circuit scale and cost due to rearrangement of parallel input image data as much as possible.

  One aspect of the present invention for solving the above-described problems is an image reading apparatus including a line image sensor having a plurality of channels, each of which includes a storage unit that stores image data for at least one line, and each of the channels. An image processing unit that receives image data that is output in parallel, performs predetermined image processing on the target pixel for each of the received image data in parallel, and outputs the image data. A rearrangement processing unit that receives each of the image data output in parallel from the processing unit and writes the image data in the storage unit so as to be in the order of the channels in the line image sensor. It is characterized by.

  In the above-described image reading apparatus, provided at the subsequent stage of the rearrangement processing unit, reads the image data in the channel arrangement order from the storage unit in that order, performs predetermined image processing on the pixel of interest, and outputs it. The image processing unit may be included.

  In any one of the above image reading apparatuses, the image processing unit, the rearrangement processing unit, and the other image processing unit are provided on one ASIC, and the storage unit is provided outside the ASIC. It may be characterized by being provided in.

  Another aspect of the present invention for solving the above problem is an image processing method in an image reading apparatus including a line image sensor having a plurality of channels, wherein the image reading apparatus receives image data for at least one line. An image processing step comprising: a storage unit for storing; receiving image data output in parallel from each of the channels; and performing predetermined image processing on the target pixel in parallel for each of the received image data; and After the image processing step, each of the image data output in parallel by the image processing step is received, and the image data is written in the storage unit so as to be in the order of the channels in the line image sensor. A replacement processing step.

1 is a block diagram showing a configuration related to image data rearrangement in an image reading apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of an image processing circuit A. FIG. 3 is a block diagram illustrating a configuration example of an image reading apparatus that rearranges image data using an internal memory. FIG. 3 is a diagram illustrating a configuration example of an image reading apparatus that rearranges image data using an external memory.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration related to rearrangement of image data in an image reading apparatus 1 according to an embodiment of the present invention. This figure shows an outline of the hardware configuration related to the image data rearrangement process in order to easily understand the features related to the image data rearrangement.

  The image reading device 1 is a device such as a so-called scanner, copier, or multifunction device. The image reading apparatus 1 includes a line image sensor 10, an image processing ASIC 20, a RAM 100, and a ROM 110.

  The line image sensor 10 includes a plurality of sensor blocks (sensor units) arranged in the main scanning direction. In this figure, the line image sensor 10 has three blocks (blocks 0 to 2). Image data (analog data) for each line generated by the line image sensor 10 by applying light to the document is divided in units of sensor blocks, and output from each block to the image processing ASIC 20 in parallel.

  A conversion circuit (for example, AFE) that converts analog data into digital data is provided between the line image sensor 10 and the image processing ASIC 20 (not shown). In this embodiment, it is assumed that the conversion circuit converts analog data input in parallel from the line image sensor 10 into digital data in parallel and outputs the digital data to the image processing ASIC 20 in parallel. Of course, the conversion circuit may be incorporated in the image processing ASIC.

  The RAM 100 is a large-capacity storage device used for temporarily storing a program executed by the CPU 70, image data to be processed by the rearrangement processing circuit 50 described later, and image processing target image data. is there. The RAM 100 is a volatile memory such as SDRAM or DDR-SDRAM, for example.

  The ROM 110 is a storage device that stores various programs and data to be executed by the CPU 70 of the image processing ASIC 20. The ROM 110 is, for example, a nonvolatile flash ROM.

  The image processing ASIC 20 is an image processing unit that rearranges image data input in parallel from the line image sensor 10 and performs various image processing. The image processing ASIC 20 includes an input interface (I / F) 30, an image processing circuit A 40, a rearrangement processing circuit 50, an image processing circuit B 60, a CPU 70, an output interface (I / F) 80, and a RAM interface (I / F) 90. Have.

  The input I / F 30 is an interface circuit that receives image data output in parallel from each sensor block of the line image sensor 10 and outputs the image data in parallel to the subsequent image processing circuit A40.

  The image processing circuit A40 receives the image data of each sensor block output in parallel from the input I / F 30, performs predetermined image processing in parallel, and converts the image data after the image processing in parallel to a rearrangement processing circuit 50 in the subsequent stage. The circuit that outputs to

  The image processing circuit A40 of the present embodiment performs predetermined image processing on the pixel of interest in the order of input with respect to the image data of each sensor block. The image processing of the target pixel using the neighboring pixels of the target pixel is not performed. As image processing, for example, shading correction, gamma correction, and the like are performed.

  The image processing circuit A40 can be configured as shown in FIG. 2, for example. That is, the image processing circuit A 40 includes a shading correction unit 41 and a gamma correction unit 42. The shading correction unit 41 receives image data of each sensor block output in parallel from the input I / F 30, performs shading correction on the target pixel in the order of input, and applies the processed target pixel in parallel to the gamma correction unit Output to 42. The gamma correction unit 42 receives the image data of each sensor block output in parallel from the shading correction unit 41, performs gamma correction on the target pixel in the input order, and arranges the processed target pixel in parallel in the subsequent stage. The data is output to the replacement processing circuit 50.

  The configuration of the image processing circuit A40 is not limited to the above. For example, each of the shading correction unit 41 and the gamma correction unit 42 has a circuit configuration for processing image data for one sensor block. Then, the internal clock of the image processing circuit A40 may be set to be equal to or higher than the input rate × the number of blocks, and the image processing circuit A40 may be operated to sequentially process the image data of each block. In this way, it is not necessary to provide the same number of circuits as the number of blocks as shown in FIG. 2, and the increase in circuit scale can be suppressed.

  Returning to FIG. 1, the rearrangement processing circuit 50 receives the image data of each sensor block output in parallel from the image processing circuit A 40, and the image data of each block is converted into a data order in the main scanning direction in the line image sensor 10. This is a circuit for writing to the RAM 100 via the RAM I / F 90 so that the line becomes (in order from the first pixel to the last pixel of the line).

  Note that in the subsequent stage (image processing circuit B60, CPU 70, etc.) from the rearrangement processing circuit 50, image data is processed in order from the first pixel in units of one line. Therefore, it is necessary to prepare an area for storing at least one line of image data written by the rearrangement processing circuit 50 in the RAM 100. In addition, when writing image data from the rearrangement processing circuit 50 and reading image data by a subsequent circuit are performed in parallel, an area for storing at least two lines of image data is prepared in the RAM 100. There is a need.

  The RAM I / F 90 is an interface for controlling access (read, write, etc.) to the RAM 100 in response to requests from other circuits (the rearrangement processing circuit 50, the image processing circuit B60, the CPU 70, the output I / F 80, etc.). Circuit.

  The image processing circuit B60 reads the image data in units of lines written in the RAM 100 by the rearrangement processing circuit 50 in order from the first pixel of the line, performs predetermined image processing in the read order, and performs image processing after image processing. This is a circuit for writing data to the RAM 100 again. It is assumed that the area where image data is read is different from the area where image data after image processing is written.

  The image processing circuit B60 according to the present embodiment performs predetermined image processing on the pixel of interest in the input order for the image data of each line. Image processing of the pixel of interest may be performed using a pixel near the pixel of interest, or image processing of the pixel of interest may be performed without using a pixel near the pixel of interest. As the image processing, for example, filtering, enlargement / reduction, and the like are performed.

  The CPU 70 implements various processes by reading a predetermined program from the ROM 110 into the RAM 100 and executing it. The CPU 70 controls the entire image processing ASIC 20 in an integrated manner, or performs predetermined image processing on the image data stored in the RAM 100.

  The output I / F 80 is an interface circuit for reading image data subjected to various image processes from the RAM 100 and outputting the read image data to a subsequent circuit outside the image processing ASIC 20 in the read order. Examples of the output destination include a storage device such as a hard disk, a network interface connected to a host PC, and the like, an ASIC that controls printing by a print engine, and the like.

  The above is the configuration related to the rearrangement of the image data of the image reading apparatus 1 according to the present embodiment. Of course, the configuration of the image reading apparatus 1 is not limited to the above. For example, a plurality of image processing circuits that process image data of each sensor block in parallel may be provided in the previous stage of the rearrangement processing circuit 50. Further, for example, a plurality of image processing circuits that process image data in units of lines may be provided at the subsequent stage of the rearrangement processing circuit 50.

  Note that the configuration of the image reading apparatus 1 described above is not limited to the above because the main configuration has been described in describing the features of the present invention. Further, the configuration of the image reading apparatus 1 does not exclude other configurations included in a general image reading apparatus.

  As described above, in the present embodiment, predetermined image processing is first performed in parallel on the image data of each sensor block input to the image processing ASIC 20, and then image data rearrangement processing using an external memory is performed. Is done. With this processing order, there is no need to provide an internal memory in the image processing ASIC 20 for rearranging image data input in parallel. In addition, since the predetermined image processing is performed without using the external memory before the rearrangement processing, access to the external memory is reduced.

  In order to clarify the characteristics of this embodiment, an image reading apparatus that does not have the characteristics of this embodiment will be described as an example.

  FIG. 3 is a block diagram illustrating a configuration example of an image reading apparatus 1 ′ that rearranges image data using an internal memory. As shown in the figure, the image processing ASIC 20 ′ of the image reading apparatus 1 ′ has a rearrangement processing circuit 50 ′ at the subsequent stage of the input I / F 30. Further, an image processing circuit A40 'is provided at the subsequent stage of the rearrangement processing circuit 50'.

  The rearrangement processing circuit 50 'includes a RAM 51' for storing image data for at least one line. The rearrangement processing circuit 50 ′ stores the image data of each sensor unit input in parallel in the RAM 51 ′ so that the data order in the main scanning direction of the line image sensor is obtained.

  The image processing circuit A40 ′ reads the image data in units of lines written in the RAM 51 ′ by the rearrangement processing circuit 50 ′ sequentially from the first pixel of the line, performs predetermined image processing in the read order, and performs image processing. This is a circuit for writing subsequent image data to the RAM 100.

  In the image processing ASIC 20 ′, the input image data of each sensor block is first subjected to rearrangement processing using an internal memory, and then predetermined image processing is performed. Because of this processing order, the image processing ASIC 20 'needs to have an internal memory. That is, the circuit scale and the manufacturing cost increase as compared with the above-described embodiment of the present invention. In general, since it is desirable to perform reading and writing in parallel, an internal memory for storing at least two lines of image data is required.

  FIG. 4 is a block diagram showing a configuration example of an image reading apparatus 1 ″ that rearranges image data using an external memory. As shown in FIG. 4, the image processing ASIC 20 ″ of the image reading apparatus 1 ″ A rearrangement processing circuit 50 ″ is provided at the subsequent stage of the input I / F 30. Further, an image processing circuit A40 "is provided at the subsequent stage of the rearrangement processing circuit 50".

  The rearrangement processing circuit 50 ″ receives the image data of each sensor block output in parallel from the input I / F 30, and stores the image data of each block in the data order in the main scanning direction of the line image sensor. This is a circuit for writing to the RAM 100 via / F90.

  The image processing circuit A 40 ″ reads the line-by-line image data written to the RAM 100 by the rearrangement processing circuit 50 ″ in order from the first pixel of the line, performs predetermined image processing in the read order, and after image processing The image data is written to the RAM 100.

  In the image processing ASIC 20 ″, the input image data of each sensor block is first subjected to rearrangement processing using an external memory, and then predetermined image processing is performed. Due to such processing order. The image processing ASIC 20 ″ needs to perform a rearrangement process using an external memory before a predetermined image process. That is, as compared with the above-described embodiment of the present invention, the number of accesses to the external memory and the traffic increase. In the example of FIG. 4, the access (read and write) to the external memory is one round trip more than that in FIG.

  The embodiment of the present invention has been described above. According to the present embodiment, it is possible to provide a technique for suppressing an increase in circuit scale and cost due to rearrangement of image data input in parallel as much as possible.

  The above-described embodiments of the present invention are intended to illustrate the gist and scope of the present invention and are not intended to be limiting. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

1: image reading device, 10: line image sensor, 20: image processing ASIC, 30: input I / F, 40: image processing circuit A, 41: shading correction unit, 42: gamma correction unit, 50: rearrangement processing circuit 60: Image processing circuit B, 70: CPU, 80: Output I / F, 90: RAM I / F, 100: RAM, 110: ROM, 1 ′: Image reading device, 20 ′: Image processing ASIC, 40 ′: Image processing circuit A, 50 ': Rearrangement processing circuit, 51': RAM, 1 ": Image reading device, 20": Image processing ASIC, 40 ": Image processing circuit A, 50": Rearrangement processing circuit

Claims (4)

An image reading apparatus including a line image sensor having a plurality of channels,
A storage unit for storing image data for at least one line;
An image processing unit that receives image data output in parallel from each of the channels, performs predetermined image processing on the target pixel for each of the received image data in parallel, and outputs,
The storage unit is provided at a subsequent stage of the image processing unit, receives each of the image data output in parallel from the image processing unit, and stores the image data in the order of the channels in the line image sensor. A reordering processing unit that writes to
An image reading apparatus comprising: The image reading apparatus according to claim 1,
Another image processing unit, which is provided at a subsequent stage of the rearrangement processing unit, reads out image data in the order of arrangement of the channels from the storage unit in that order, performs predetermined image processing on the target pixel, and outputs it
An image reading apparatus comprising: The image reading apparatus according to claim 1, wherein:
The image processing unit, the rearrangement processing unit, and the other image processing unit are provided on one ASIC,
The storage unit is provided outside the ASIC.
An image reading apparatus. An image processing method in an image reading apparatus including a line image sensor having a plurality of channels,
The image reading device includes:
A storage unit for storing image data for at least one line;
An image processing step of receiving image data output in parallel from each of the channels, and performing predetermined image processing on the target pixel in parallel for each of the received image data;
After the image processing step, each of the image data output in parallel by the image processing step is received, and the image data is written in the storage unit so as to be the order of the channels in the line image sensor. A sorting process step;
The image processing method characterized by performing.

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