JP2011030327A - Power supply circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact and low-cost power supply circuit without changing circuit performance, even when a capacitor for output with a low breakdown voltage is used. <P>SOLUTION: A capacitor C2 for output is connected between the voltage output terminal VOUT of a charge pump booster 10 and the output side of a DC power supply VCC. Thus the charge pump booster can output a boost voltage relative to the voltage level of the DC power supply VCC. As a result, it is possible to use a capacitor for output having a breakdown voltage corresponding to a differential voltage obtained by subtracting the voltage component of the DC power supply VCC from an output voltage boosted at the charge pump booster 10. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a power supply circuit device, and more particularly to a power supply circuit device that can use an output capacitor having a low withstand voltage.

In recent years, mobile devices such as mobile phones, portable information terminals, and portable music players have been rapidly reduced in size and power consumption.
For example, a familiar mobile phone is preferred by users because it is very thin or lightweight. At the same time, products with high functionality are increasing, but products that can be driven for a long time with low power consumption are preferred.
Needless to say, thinning and low power consumption are also required for components built into these devices. In recent mobile phones, piezoelectric speakers that are relatively thin and have low power consumption are often used for speaker devices.

By the way, since such mobile devices are driven using a battery as a power source, it is necessary to obtain an output voltage higher than the power source voltage. Normally, these devices have a built-in power supply circuit device constituted by a booster circuit.
As the power supply circuit device, there are a DC-DC converter and a charge pump type boosting device that boosts a DC power source as shown in FIG. 9 by a charge pump circuit. FIG. 9 is a circuit configuration diagram showing a configuration of a general charge pump booster.

The charge pump type booster 100 shown in FIG. 9 is connected between the DC power supply VCC via the voltage input terminal VIN and the load 200 via the voltage output terminal VOUT. At the same time, the charge pump booster 100 is connected to the ground via the reference voltage terminal VSS.
The charge pump booster 100 includes a charge pump circuit 100a for performing a boost operation by turning on / off a switch, a clock generator 100b for generating a clock signal CLK for controlling the on / off operation of the switch, A charging / discharging capacitor C1 which is a power storage element for performing charge boosting by charging / discharging a charge corresponding to the DC power supply VCC, and an output capacitor C2 for holding and stabilizing and outputting the boosted output voltage. Composed.

  In the charge pump type booster 100, first, a charge phase for charging the charge / discharge capacitor C1 is performed by the charge pump circuit 100a. Thereafter, a transfer phase is performed in which the charge charged in the charge / discharge capacitor C1 is transferred to the output capacitor C2 with the ground level as a reference voltage. The charge pump type boosting device 100 repeats the boosting operation including the charge phase and the transfer phase while turning on / off the switch of the charge pump circuit 100a by the clock signal CLK output from the clock generation unit 100b. Boost the output voltage of the DC power supply VCC.

  As shown in the figure, the output capacitor C2 has a positive (+) terminal connected to the voltage output terminal VOUT of the charge pump booster 10 and a negative (−) terminal connected to the reference voltage terminal VSS having the ground as a reference voltage. It is connected. Therefore, the charge charged in the charge / discharge capacitor C1 is transferred to the output capacitor C2 using the ground level as a reference voltage. Therefore, it is necessary to use a capacitor having a withstand voltage capable of withstanding the boosted power supply voltage as the output capacitor C2 connected to the charge pump booster 100 described above.

  For example, the charge pump circuit, the solid-state imaging device, and the liquid crystal display device described in Patent Document 1 control the amount of charge of a charging / discharging capacitor therein, so that the voltage applied to the elements constituting the circuit is It is possible to prevent the breakdown voltage from being exceeded.

JP 2008-283794 A

However, the above charge pump circuit, solid-state imaging device, and liquid crystal display device control the charge amount itself of the charge / discharge capacitor. For this reason, as the charge amount decreases, the output voltage after boosting naturally also decreases. That is, the above circuit and device have not been proposed in consideration of the withstand voltage of the output capacitor connected to the external component.
Therefore, if the product becomes highly functional and power consumption increases, a capacitor having a higher withstand voltage must be used. However, the output capacitor increases in size and size as the breakdown voltage increases. For this reason, the use of a capacitor with a high withstand voltage hinders the miniaturization of the shape of a small electronic device manufactured using these booster circuits, and also hinders the production of a product at a low price. Become.
In view of the above problems, an object of the present invention is to provide a power supply circuit that is small and low-cost without changing circuit performance even when an output capacitor having a low withstand voltage is used.

In order to achieve the above object, a power supply circuit device according to the present invention is configured as follows.
A first power supply circuit device according to the present invention includes a reference voltage terminal for inputting a reference voltage, a voltage input terminal for inputting a power supply voltage, and boosting, stepping down or stepping up or down the power supply voltage input from the voltage input terminal. And a voltage output terminal that outputs an output voltage output by the step-up / step-down means, the power supply circuit device comprising a voltage output terminal and a voltage output terminal between the voltage input terminal and the voltage output terminal Is connected to the output power storage device, and the output power storage device supplies the power corresponding to the output voltage boosted, stepped down, or stepped up / down with reference to the reference voltage. It is characterized by being held with reference to voltage.

According to the above power supply circuit device, the step-up / step-down means outputs an output voltage obtained by stepping up, stepping down or stepping up / down the power supply voltage input from the voltage input terminal with reference to the reference voltage. However, the output storage element holds the output voltage boosted, stepped down, or stepped up / down by the step-up / step-down means with reference to the reference voltage, with reference to the power supply voltage. In short, even if the output storage element does not have a withstand voltage corresponding to the output voltage, it is possible to hold the output voltage that has been stepped up, stepped down or stepped up / down with reference to the reference voltage by the step-up / step-down means. .
In a second power supply circuit device according to the present invention, the step-up / step-down means is a charge pump type booster circuit.
According to the power supply circuit device described above, it is possible to reduce the withstand voltage of the output storage element by using a known charge pump type booster circuit as the step-up / step-down means.

A power supply circuit device for a portable device according to the present invention includes a voltage input terminal connected to a positive electrode terminal of a storage battery for inputting a power supply voltage, and an output obtained by boosting, stepping down or stepping up the power supply voltage input from the voltage input terminal. A power supply circuit device for a portable device, comprising: a step-up / step-down means for outputting a voltage; and a voltage output terminal for outputting an output voltage output by the step-up / step-down means. Output power storage element that holds the output voltage, and the output power storage element corresponds to the output voltage boosted, stepped down, or stepped up / down with reference to the voltage of the negative terminal of the storage battery The charge to be held is held with reference to the power supply voltage.
According to the above-described power supply circuit device for mobile devices, the power supply circuit device optimal for mobile devices and the same operation as the first power supply circuit device are achieved.

According to the power supply circuit device of the present invention, for example, in the case of a booster circuit, it corresponds to a differential voltage obtained by subtracting the power supply voltage from the output voltage without reducing the boosted output voltage, that is, without changing the circuit performance. One having a withstand voltage can be used. For this reason, the production cost of the product in which the power supply circuit device is incorporated can be reduced, and the product size can be further reduced.
Even if output capacitors having different withstand voltages are used, the power supply voltage can be stepped up / down by performing a general step-up / step-down operation using, for example, a known charge pump type booster circuit. Therefore, there is no major circuit change, which is very convenient for reducing the production cost and reducing the product size.

FIG. 2 is a circuit configuration diagram showing a connection configuration of a charge pump booster, a DC power source, and a load when a charge pump booster is used as an example of a power supply circuit device according to the present invention. It is a circuit block diagram which shows the structure of the charge pump system booster circuit which concerns on this embodiment. 4 is a time chart showing a clock generation signal and output signal waveforms of each terminal voltage in the charge pump booster according to the present embodiment. It is an equivalent circuit diagram of the charge pump circuit in the charge phase of the charge pump type booster according to the present embodiment. It is an equivalent circuit diagram of the charge pump circuit in the transfer phase of the charge pump type booster according to the present embodiment. 3 is a graph showing DC bias characteristics of a ceramic capacitor. It is a circuit block diagram which shows the structure of the circuit by which the control circuit was connected as a load to the charge pump system booster. It is a block diagram which shows the structure of the power supply circuit using a pressure | voltage rise type DC-DC converter. It is a circuit block diagram which shows the structure of a general charge pump system booster.

DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings. In each drawing referred to in the following description, components equivalent to those in the other drawings are denoted by the same reference numerals.
(Connection configuration of charge pump booster, DC power supply and load)
First, a connection configuration of a charge pump booster, a DC power source, and a load when a charge pump booster is used as an example of a power supply circuit device according to the present invention will be described with reference to FIG. FIG. 1 is a circuit configuration diagram showing a connection configuration of a charge pump booster, a DC power source, and a load when a charge pump booster is used as an example of a power supply circuit device according to the present invention.
In the charge pump booster 10 shown in FIG. 1, a DC power supply VCC is connected to a voltage input terminal VIN, and a load 20 is connected to a voltage output terminal VOUT. The DC power supply VCC, the charge pump booster 10 and the load 20 are connected to a reference voltage terminal VSS having a ground as a reference voltage.

The DC power supply VCC is a power supply for driving the load 20. For example, when the charge pump type booster 10 is incorporated in a portable small device, it is convenient to use a small storage battery that can continuously drive the load 20 for several tens of hours in consideration of its convenience. It is.
Here, as shown, the reference voltage terminal VSS is connected to the ground. In the case of a small storage battery, the negative terminal thereof becomes the reference voltage terminal VSS.
The load 20 is, for example, a music piezoelectric speaker or a liquid crystal display device, and is driven by an output voltage obtained by boosting the power supply voltage VCC by the charge pump booster 10.

(Configuration of charge pump type booster circuit)
Next, the configuration of the charge pump booster circuit according to this embodiment will be described with reference to FIG. FIG. 2 is a circuit configuration diagram showing the configuration of the charge pump booster circuit according to the present embodiment.
The charge pump booster 10 shown in FIG. 2 includes a charge pump circuit 10a, a clock signal generation circuit 10b, a charge / discharge capacitor C1, and an output capacitor C2.
The charge pump circuit 10a includes switches SW1 to SW4. The switches SW1 to SW3 are PMOS transistors, and the switch SW4 is an NMOS transistor, and functions as a switch for opening and closing the circuit.

  The switches SW1 to SW4 are controlled to be turned on / off by the clock signals CLK1 to CLK4 generated by the clock signal generation circuit 10b. The switch SW1 is connected between the positive terminal of the charge / discharge capacitor C1 and the voltage input terminal VIN, and switches the connection state therebetween. The switch SW2 is connected between the negative terminal of the charge / discharge capacitor C1 and the voltage input terminal VIN, and switches the connection state therebetween. The switch SW3 is connected between the positive terminal of the charge / discharge capacitor C1 and the voltage output terminal VOUT, and switches the connection state therebetween. The switch SW4 is connected between the negative electrode terminal of the charge / discharge capacitor C1 and the negative electrode side (reference voltage terminal VSS) of the load, and switches the connection state therebetween.

The clock signal generation circuit 10b generates clock signals CLK1 to CLK4 for controlling on / off operations of the switches SW1 to SW4 of the charge pump circuit 10a in each phase of the boosting operation.
The charging / discharging capacitor C1 is connected between the charging / discharging capacitor connection terminal CP and the charging / discharging capacitor connection terminal CN, and charges / discharges the charge corresponding to the DC power supply VCC by the on / off operation of the switches SW1 to SW4. It is an electrical storage element for doing.

The output capacitor C2 is connected between the voltage output terminal VOUT and the voltage input terminal VIN, and is a storage element for holding the charge transferred from the charge / discharge capacitor C1. The output capacitor C2 is a storage element that holds the boosted output voltage and stabilizes and outputs the output voltage.
In the charge pump circuit 10a, the switches SW1 to SW4 are turned on / off by the clock signals CLK1 to CLK4, whereby the charge / discharge capacitor C1 is charged with the charge corresponding to the DC power supply VCC, and the output capacitor C2 is charged / discharged. By holding the charge transferred from the capacitor C1, the boost operation of the DC power supply VCC is performed.

(Operating principle of charge pump booster)
Next, with reference to FIG. 3, the operation principle of the boosting operation in the charge pump booster according to the present embodiment will be described. FIG. 3 is a time chart showing the clock generation signal and the output signal waveform of each terminal voltage in the charge pump booster according to the present embodiment. FIG. 4 shows the charge in the charge phase of the charge pump booster according to the present embodiment. FIG. 5 is an equivalent circuit diagram of the pump circuit, and FIG. 5 is an equivalent circuit diagram of the charge pump circuit in the transfer phase of the charge pump booster according to the present embodiment.

The horizontal axis of the time chart shown in FIG. 3 indicates the passage of time, and the vertical axis indicates the signal level.
First, the charge phase PH1 in the time chart shown in FIG. 3 is a period during which the charge / discharge capacitor C1 is charged with a charge corresponding to the DC power supply VCC. In the charge phase PH1, since the clock signal CLK1 is at the L (LOW) level and the clock signal CLK4 is at the H (HIGH) level, both the switches SW1 and SW4 are turned on. Further, since the clock signals CLK2 and CLK3 are at the H level, the switches SW2 and SW3 are turned off.

In the charge phase PH1, the internal circuit of the charge pump booster 10 is as shown in an equivalent circuit 21 shown in FIG. The on-resistances Ron1 and Ron4 are resistances generated when the switches SW1 and SW4 are turned on.
At this time, the charge / discharge capacitor C1 has a time constant determined by the on-resistances Ron1 and Ron4 and the charge / discharge capacitor C1, and the charge corresponding to the DC power supply VCC with the ground level as a reference voltage is indicated by an arrow A shown in the figure. It is charged in the direction of. In addition, since a potential difference is caused by the on-resistance Ron4 connected between the charge / discharge capacitor connection terminal CN and the ground, strictly speaking, the reference voltage does not become the ground level. However, since the on-resistance Ron4 is a value that can be ignored, the ground level can be considered as the reference voltage.

  Further, the charge consumed by the load 20 is lost from the charge held in the output capacitor C2. As the charge moves, the voltage at the charge / discharge capacitor connection terminal CP increases as shown in the time chart, while the voltage at the charge / discharge capacitor connection terminal CN decreases. A voltage drop corresponding to the charge lost from the output capacitor C2 occurs in the potential of the voltage output terminal VOUT.

Next, the transfer phase PH2 in the time chart shown in FIG. 3 is a period during which the charge charged in the charge / discharge capacitor C1 is transferred to the output capacitor C2. In this transfer phase PH2, since the clock signal CLK1 changes from L level to H level and the clock signal CLK4 changes from H level to L level, the switches SW1 and SW4 are switched from the on state to the off state. Further, since the clock signals CLK2 and CLK3 are switched from the H level to the L level, the switches SW2 and SW3 are switched from the off state to the on state.
In the transfer phase PH2, the internal circuit of the charge pump circuit 10a becomes like an equivalent circuit 22 shown in FIG. Note that the on-resistances Ron2 and Ron3 are resistances generated when the switches SW2 and SW3 are turned on, similarly to the on-resistances Ron1 and Ron4 described above.

  At this time, the output capacitor C2 has a positive terminal connected to the charge / discharge capacitor C1 and a negative terminal connected to the positive terminal of the DC power supply VCC. Therefore, when charge is transferred from the charging / discharging capacitor C1 to the output capacitor C2, it is determined by the on-resistances Ron2, Ron3, the charging / discharging capacitor C1, and the output capacitor C2 with reference to the voltage of the DC power supply VCC. Charges are transferred from the charge / discharge capacitor C1 to the output capacitor C2 in the direction of the arrow B shown in the figure. Note that, since a potential difference is caused by the on-resistance Ron2 connected between the charge / discharge capacitor connection terminal CN and the DC power supply VCC, strictly speaking, the reference voltage does not become the voltage of the DC power supply VCC. However, since the on-resistance Ron2 is a value that can be ignored, the voltage of the DC power supply VCC can be considered as the reference voltage.

  Further, the output capacitor C2 has the charge consumed by the load 20 transferred from the charge / discharge capacitor C1. As the charge moves, the voltage at the charging / discharging capacitor connection terminal CP decreases as shown in the time chart, while the voltage at the charging / discharging capacitor connection terminal CN increases. The potential at the voltage output terminal VOUT is increased by a voltage corresponding to the charge lost from the output capacitor C2.

The charge pump booster 10 alternately boosts the voltage of the DC power supply VCC by repeating the charge phase PH1 and the transfer phase PH2, and uses the boosted voltage as an output voltage as a voltage output terminal VOUT. Output from.
Further, when the charge phase PH1 is switched to the transfer phase PH2, floating phases FPH1 to FPH3 are provided.

First, in the floating phase FPH1, the clock signal CLK1 is switched from the L level to the H level, and the switch SW1 is turned off, and only one positive terminal of the charging / discharging capacitor C1, that is, the charging / discharging capacitor connection terminal CP side is disconnected. This is a period during which a floating state is reached.
In the subsequent floating phase FPH2, the clock signal CLK4 is switched from the H level to the L level and the switch SW2 is turned off, so that both terminals of the charging / discharging capacitor C1, that is, both charging / discharging capacitor connection terminals CP and CN are floating. This is the period during which the state is reached.

  In the subsequent floating phase FPH3, the clock signal CLK2 is switched from the H level to the L level and the switch SW2 is turned on, so that only the positive one terminal of the charging / discharging capacitor C1, that is, the charging / discharging capacitor connection terminal CP side only. This is a period during which the floating state is resumed. Finally, the clock signal CLK3 is switched from the H level to the L level, and the switch SW3 is turned on, so that both terminals of the charging / discharging capacitor C1, that is, the charging / discharging capacitor connection terminals CP and CN are not in the floating state. Transition to PH2.

  The floating phases FPH1 to FPH3 are dead time periods during which no charge transfer from the DC power supply VCC to the charge / discharge capacitor C1 and no charge transfer from the charge / discharge capacitor C1 to the output capacitor C2 occur. By providing the floating phases FPH1 to FPH3 when shifting from the charge phase PH1 to the transfer charge PH2, it is possible to prevent a current from flowing between the DC power supply VCC and the reference voltage terminal VSS.

  For the same reason as described above, the floating phases FPH4 to FPH6 are also provided when shifting from the transfer phase PH2 to the charge phase PH1. Similarly to the floating phases FPH1 to FPH3, the floating phases FPH4 to FPH6 have the same polarity order of the charge / discharge capacitors C1 to be in a floating state.

First, in the floating phase FPH4, the clock signal CLK3 is switched from the L level to the H level and the switch SW3 is turned off, so that only one positive terminal of the charging / discharging capacitor C1, that is, the charging / discharging capacitor connection terminal CP side is floating. This is the period during which the state is reached.
In the subsequent floating phase FPH5, the clock signal CLK2 is switched from the L level to the H level and the switch SW2 is turned off, so that both ends of the charge / discharge capacitor C1, that is, both sides of the charge / discharge capacitor connection terminals CP and CN are floating. This is the period during which the state is reached.

In the subsequent floating phase FPH6, the clock signal CLK4 is switched from the L level to the H level and the switch SW4 is turned on, and only the positive one terminal of the charging / discharging capacitor C1, that is, the charging / discharging capacitor connection terminal CP side only. It will be in a floating state again.
Finally, the clock signal CLK1 is switched from the L level to the H level, both terminals of the charging / discharging capacitor C1, that is, the charging / discharging capacitor connection terminals CP and CN, are not in the floating state, and the phase shifts to the charging phase PH1.

  As described above, when the transition from the charge phase PH1 to the transfer phase PH2 is performed, the floating phases FPH1 to FPH3 are provided, and when the transfer phase PH2 is shifted to the charge phase PH1, the floating phases FPH4 to FPH6 are provided. It is possible to reliably prevent a current from flowing between VCC and the reference voltage terminal VSS.

  As described above, the output capacitor C2 only needs to have a withstand voltage corresponding to the potential difference between the voltage output terminal OUT and the node VDD, and the output capacitor C2 is connected to the voltage output terminal OUT as in the conventional connection method. A device having a lower withstand voltage than when connected between the reference voltage terminals VSS can be used. As described above, even if an output capacitor having a lower withstand voltage than that of the related art is used, the output voltage of the charge pump circuit 10a can be smoothed or stabilized without degrading the boosting performance.

(DC bias characteristics of ceramic capacitors used for output capacitors)
Here, with reference to FIG. 6, the DC bias characteristic of the ceramic capacitor used for the output capacitor will be described. FIG. 6 is a graph showing the DC bias characteristics of the ceramic capacitor.
When the charge pump booster 10 according to the present embodiment is commercialized, a ceramic capacitor is used as the normal output capacitor. Among ceramic capacitors, in particular, a high-permittivity ceramic capacitor has a DC bias characteristic in which the capacitance changes depending on the bias when a DC bias is applied. This DC bias characteristic is a phenomenon peculiar to a high dielectric constant type ceramic capacitor, and cannot be ignored when the charge pump type booster 10 is mounted on a mobile device or the like.

  The graph shown in FIG. 6 is a booster device having a specification in which the charge pump booster device 10 boosts the input voltage and outputs it, and the voltage of the DC power supply VCC is the average value of the rated output voltage of a general battery. This shows the DC bias characteristics of the ceramic capacitor when the output capacitor C2 has a capacitance of about 1.0 to 2.2 μF. The horizontal axis of the graph shown in FIG. 6 indicates the power supply voltage VCC [V], and the vertical axis indicates the ratio [%] of the electrostatic capacity due to the DC bias characteristic to the rated electrostatic capacity of the ceramic capacitor.

  The voltage output terminal VOUT of the charge pump type booster 10 is boosted to 7.2 V by boosting the output voltage 3.6 V of the DC power supply VCC twice. However, as shown in the graph of FIG. 6, the ratio 40 of the capacitance due to the DC bias characteristic to the rated capacitance of the ceramic capacitor remains almost 100% until the DC power supply VCC is about 1.0V. However, as the DC power supply VCC increases from around the DC power supply VCC exceeding 1.0 V, the capacitance gradually decreases due to the DC bias characteristics. In particular, when the DC power supply VCC is around 3.6 V, the capacitance decreases to 50% of the rating.

  Therefore, in the case where the output capacitor C2 is connected between the voltage output terminal VOUT and the reference voltage terminal VSS, considering the above bias dependence, at least 14 times the boosted output voltage of 7.2V is 14 times. It is necessary to use a ceramic capacitor having a withstand voltage of .4V. Capacitors having this withstand voltage in the current market have a withstand voltage of 16 V even with the lowest withstand voltage, and the standard size is 1608 size.

On the other hand, when the output capacitor C2 is connected between the voltage output terminal VOUT and the positive terminal of the DC power supply VCC, it has a withstand voltage of 6.3V and the standard size is 1005 size even in consideration of bias dependency. Things can be used.
Although it depends on the manufacturer and specifications of the ceramic capacitor, the size of the above-mentioned 1608 size ceramic capacitor is about 0.8 mm in width, 1.6 mm in depth, and about 0.8 mm in height. On the other hand, the dimensions of a 1005 size ceramic capacitor are about width 0.5 mm, depth 1.0 mm, and height 0.5 mm.

  Therefore, the volume of the 1608 size ceramic capacitor is ¼ or less of the volume of the 1005 size ceramic capacitor. That is, even if compared by area ratio, it becomes smaller and the height becomes smaller, so it becomes very small even if compared by volume ratio. Therefore, the size of the power supply circuit device can be greatly reduced, and at the same time, the production cost of the power supply circuit device can be reduced.

  Capacitors used in products in the future will be required to be small and low cost when built into mobile devices. In recent years, the use of a standard size below 1005 size has been demanded in the market, and thus the charge pump booster 10 according to the present embodiment is very convenient. Further, if the size of the ceramic capacitor itself becomes smaller in the future, the use of the power supply circuit device according to the present embodiment reduces the size and cost of the charge pump booster as the size of the ceramic capacitor itself becomes smaller. Can be dramatically improved.

(First modification)
The above-described embodiments are merely examples, and various modifications can be made without departing from the scope of the technical idea shown in the claims.
Therefore, as a first modification of the power supply circuit device of the present embodiment, a configuration of a charge pump booster device in which a control circuit is connected as a load will be described with reference to FIG. FIG. 7 is a circuit configuration diagram showing a configuration of a circuit in which a control circuit is connected as a load to the charge pump type booster.

In practice, as shown in FIG. 7, the load 20 is connected between the voltage output terminal VOUT and the reference voltage terminal VSS of the charge pump booster 10, and the control circuits 30-1 to 30-1 are connected between the node VDD and the reference voltage terminal VSS. 30-n are connected. When the control circuits 30-1 to 30-n (n is an integer of 2 or more) are manufactured, for example, as an IC (integrated circuit) 45, the charge pump type booster 10 is replaced with a clock generation circuit 10b, a liquid crystal display device, or the like. This is a circuit for comprehensively controlling each device in the IC45.
A bypass capacitor C0 is connected in parallel with the control circuits 30-1 to 30-n. This bypass capacitor C0 is a power storage element that plays a role of suppressing fluctuations in the voltage supplied from the DC power supply VCC. The charge pump booster 10 boosts the voltage supplied to the bypass capacitor C0.

  On the other hand, since the load 20 is a music piezoelectric speaker or the like as described above, although depending on the driving method, the peak of the current amount Ia is about 100 mA, and the amplitude of the signal level is very large. On the other hand, since the control circuits 30-1 to 30-n are intended to control the circuit as described above, the current amount Ib is about 2 to 5 mA and there is almost no fluctuation in the current amount. That is, when the amount of current Ia flowing through the load 20 is compared with the amount of current Ib flowing through the control circuits 30-1 to 30-n, the amount of current Ib flowing through the control circuits 30-1 to 30-n flows to the load 20. Usually, it is much less than the current amount Ia.

  Accordingly, the total amount of current supplied from the DC power supply VCC is dominated by the amount of current Ia, and is a value obtained by multiplying the amount of current Ia by the boosting factor of the charge pump booster 10. For example, when the boosting factor of the charge pump booster 10 is 2, the total current amount is 2 × Ia. The wiring resistance Ri of the circuit is generally as small as several hundred mΩ. For example, when Ia = 100 mA and Ri = 0.2Ω, the voltage supplied to the bypass capacitor C0 is about (VCC−0.04) V. That is, since the DC power supply VCC and the node VDD are almost the same voltage, the bypass capacitor C0 and the wiring resistance Ri can be ignored.

In short, if the bypass capacitor C0 and the wiring resistance Ri are ignored, only the capacity of the DC power supply VCC and the capacity of the output capacitor C2 are provided between the reference voltage terminal VSS and the voltage output terminal VOUT. Therefore, when the total capacity viewed from the voltage output terminal VOUT side is Co, the capacity of the DC power supply VCC is Ci, and the capacity Cj of the capacitor of the output capacitor C2, the total capacity viewed from the voltage output terminal VOUT side is expressed by the equation (1). And can be expressed as in equation (2).
Co = Ci × Cj / (Ci + Cj)
= Cj / (1 + Cj / Ci) (1)
Since Ci >> Cj,
Co = Cj (2)
Can be considered.

  That is, the charge pump booster 10 according to the present embodiment has the voltage output terminal VOUT and the reference voltage terminal regardless of the connection of the control circuits 30-1 to 30-n and the like as loads as described above. It can be said that this is equivalent to the case where only the output capacitor C2 is connected to VSS. As illustrated, the voltage applied to the output capacitor C2 is a potential difference between the voltage output terminal OUT and the node VDD.

(Second modification)
In the present embodiment, the power supply circuit device has been described as a charge pump booster that boosts the voltage using a charge pump circuit. However, the power supply circuit device is not limited to the charge pump booster.
Therefore, as a second modification of the power supply circuit device of the present embodiment, the configuration of a step-up DC-DC converter will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration of a power supply circuit using a step-up DC-DC converter.
The step-up DC-DC converter 50 shown in FIG. 8 includes a PWM (Pulse Width Modulation) circuit 50a, a gate drive circuit 50b, a DC-DC converter circuit 50c, and an output capacitor C2.

The PWM circuit 50a is a circuit that generates the amplitude of an input voltage into pulse signals having a constant amplitude and different pulse widths.
The gate drive circuit 50b is a circuit that controls the DC-DC converter circuit 50c based on the pulse signal generated by the PWM circuit 50a.
The DC-DC converter circuit 50c includes a coil L, a diode D, and a switch SW. The DC-DC converter circuit 50a performs a step-up operation by turning on / off the switch SW based on the signal SIG output from the gate drive circuit 50b.

  That is, the boost DC-DC converter 50 is a booster circuit that controls the voltage according to the pulse width of the pulse signal, and is different from the configuration of the booster circuit of the charge pump booster 10. However, like the charge pump booster 10, the output capacitor C2 is connected between the output voltage terminal VOUT and the reference voltage terminal VSS. For this reason, the step-up DC-DC converter 50 can lower the withstand voltage of the output capacitor C2 without changing the step-up performance by performing the step-up operation with reference to the output voltage of the DC power supply VCC.

In addition, the power supply circuit device is not limited to the booster circuit, and when a voltage lower than the power supply voltage is output, the power supply circuit device is configured by a step-down circuit. A circuit device may be configured. Also, the type of power supply circuit may be either a switching regulator or a linear regulator.
Further, for example, even in an element constituting a circuit, for example, a transistor functioning as a switch for opening and closing the circuit, the description has been made using only the MOS transistor for convenience, but the present invention can also be realized using a CMOS transistor.

(Summary)
In the charge pump booster according to this embodiment, the output capacitor is connected between the voltage output terminal VOUT of the charge pump booster and the voltage input terminal VIN on the output side of the DC power supply VCC. As a result, the charge pump booster can perform a boosting operation based on the voltage level of the reference voltage terminal VSS in the charge phase and based on the voltage level of the DC power supply VCC in the transfer phase. For this reason, it is possible to use an output capacitor having a withstand voltage corresponding to the difference voltage obtained by subtracting only the voltage of the DC power supply VCC from the output voltage boosted by the charge pump booster. For this reason, it is possible to easily reduce the production cost of a product in which the power supply circuit device is incorporated or to further reduce the product size.

  In particular, it is used as a power supply circuit device for driving small electronic devices such as mobile phones, portable information terminals and portable music players, and small components and devices such as piezoelectric speakers constituting them.

DESCRIPTION OF SYMBOLS 10 Charge pump system booster 10a Charge pump circuit 10b Clock signal generation circuit C1 Charging / discharging capacitor C2 Output capacitor SW1-SW4 switch

Claims (3)

A reference voltage terminal for inputting a reference voltage; a voltage input terminal for inputting a power supply voltage; a step-up / step-down means for outputting an output voltage obtained by stepping up, stepping down or stepping up or down the power supply voltage input from the voltage input terminal; A voltage output terminal for outputting an output voltage output by the step-up / step-down means, and a power supply circuit device comprising:
An output storage element connected between the voltage input terminal and the voltage output terminal and holding the output voltage;
The output power storage element is:
A power supply circuit device that holds charges corresponding to the output voltage boosted, stepped down, or stepped up / down with reference to the reference voltage, with reference to the power supply voltage.   2. The power supply circuit device according to claim 1, wherein the step-up / step-down means is a charge pump type booster circuit. A voltage input terminal connected to a positive electrode terminal of the storage battery for inputting a power supply voltage; a step-up / step-down means for outputting an output voltage obtained by stepping up, stepping down or stepping up the power supply voltage input from the voltage input terminal; and the step-up / step-down means A voltage output terminal for outputting an output voltage output by the power supply circuit device for a portable device comprising:
An output storage element connected between the voltage input terminal and the voltage output terminal and holding the output voltage;
The output power storage element is:
A power supply circuit device for a portable device, which holds a charge corresponding to the output voltage boosted, stepped down, or stepped up / down with reference to a voltage of a negative electrode terminal of the storage battery with reference to the power supply voltage.

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