JP2011018849A - Semiconductor inspection device and semiconductor inspection method - Google Patents

Abstract

A semiconductor inspection apparatus and a semiconductor inspection method capable of suppressing dust generation when a sample to be inspected is detached from a sample stage.
A sample table on which a semiconductor wafer is placed, a plurality of electrodes provided on the sample table, and an insulating member that electrically insulates the plurality of electrodes from the semiconductor wafer. 4 and an outer and inner electrode power source 11 and 13 for applying a voltage between at least one pair of electrodes 8 and 9 of the plurality of electrodes. The impedance control unit 21a outputs the operation signal 121 based on the measurement result. The push pin 22 and the push pin driving unit 23 move the semiconductor wafer 5 up and down with respect to the sample stage 6 based on the operation signal 121.
[Selection] Figure 1

Description

  The present invention relates to a technique of a semiconductor inspection apparatus and a semiconductor inspection method for inspecting a semiconductor wafer, a liquid crystal substrate, and the like by adsorbing them to a sample table with electrostatic force.

  In general, in the manufacturing and inspection processes of semiconductor devices, liquid crystals, etc., a holding mechanism using an electrostatic force (so-called electrostatic chuck) is used because a high surface flatness can be realized because no mechanical holder is used. Is used.

  As described above, as a technique for holding a processing object using electrostatic force, for example, Patent Document 1 discloses a pair of electrodes disposed to face the inside of a processing container for processing a substrate to be processed, In a plasma processing apparatus provided with an RF power feeding means for generating plasma between the pair of electrodes, a sample stage for holding a substrate to be processed is provided by providing an insulating film on the surface of one of the pair of electrodes. A technique is disclosed in which a substrate to be processed and the sample table are held by adsorption by electrostatic force generated between the substrate to be processed and the sample table by applying a DC voltage to the sample table by grounding the plasma.

JP 2002-203837 A

  In a semiconductor inspection apparatus using an electrostatic chuck that holds a sample to be inspected such as a semiconductor wafer using electrostatic force as in the prior art described above, when the sample to be inspected is detached from the sample stage, Even if the voltage application is stopped, the adsorption force due to electrostatic force may remain.

  In such a state, if the sample to be inspected is removed by a mechanism such as a push pin that pushes up the sample stage from the sample stage side, the sample cannot be removed from the sample stage due to the residual adsorption force, and the sample to be inspected does not leave the sample stage. Or the sample to be inspected may be warped due to local detachment, and further, friction may be generated between the push pin or the sample stage and the sample to be inspected, and the friction part may become a dust generation source.

  In particular, in recent years, circuit patterns formed on semiconductor devices and objects to be detected in inspection are also miniaturized, and there is a concern that the quality of the sample to be inspected and the yield may be reduced due to foreign matters generated by dust generation.

  The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor inspection apparatus and a semiconductor inspection method capable of suppressing dust generation when a sample to be inspected is detached from a sample stage.

  In order to achieve the above object, the present invention provides a sample table on which a sample to be inspected is mounted, a plurality of electrodes provided on the sample table, and the plurality of electrodes and the sample to be inspected are electrically insulated. Insulating means, a voltage applying means for applying a voltage between at least one pair of the plurality of electrodes, a plurality of electrodes provided between at least one pair of the plurality of electrodes, or a plurality of electrodes provided on the plurality of electrodes. Measuring means for measuring impedance between at least one pair of areas; sample lifting means for moving the sample to be inspected with respect to the sample stage based on an operation signal; and sample lifting means based on the measurement result And an elevating control means for sending an operation signal to.

  According to the present invention, it is possible to suppress dust generation when the sample is detached from the sample stage.

1 is a diagram schematically showing an overall configuration of a semiconductor inspection apparatus according to a first embodiment of the present invention. It is a figure which extracts and shows the electrostatic chuck which concerns on the 1st Embodiment of this invention with the periphery structure, and is a plane sectional view in the BB line of the electrostatic chuck shown in FIG. It is a figure which extracts and shows the electrostatic chuck which concerns on the 1st Embodiment of this invention with the periphery structure, and is side surface sectional drawing in the AA of the electrostatic chuck shown in FIG. It is a flowchart which shows the processing content of the to-be-inspected sample removal process of the whole control part containing a raising / lowering control part. It is a figure which shows an example of the relationship between the elapsed time when removing the semiconductor wafer mounted on the sample stand with a push pin, and the measured value of the impedance between the electrode area | regions, and is a figure which shows the case where it isolate | separates normally. It is a figure which shows an example of the relationship between the elapsed time when the semiconductor wafer mounted on the sample stand is detached by the push pin and the measured value of the impedance between the electrode regions, and is a figure showing a case of partial separation . It is a figure which shows an example of the relationship between the elapsed time when the semiconductor wafer mounted on the sample stand is made to detach | leave with a push pin, and the measured value of the impedance between the area | regions of an electrode, and is a figure which shows the case where it does not detach | leave. It is a figure which shows the relationship of FIGS. 5-7 collectively. It is a figure which shows the detail of the electrostatic chuck which concerns on the 2nd Embodiment of this invention, and is a plane sectional view in the DD line of the electrostatic chuck shown in FIG. It is a figure which shows the detail of the electrostatic chuck which concerns on the 2nd Embodiment of this invention, and is side surface sectional drawing in the CC line of the electrostatic chuck shown in FIG. It is a figure which shows the detail of the electrostatic chuck which concerns on the 3rd Embodiment of this invention, and is a plane sectional view in the FF line of the electrostatic chuck shown in FIG. It is a figure which shows the detail of the electrostatic chuck which concerns on the 3rd Embodiment of this invention, and is sectional drawing on the side surface in the EE line of the electrostatic chuck shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram schematically showing an overall configuration of a semiconductor inspection apparatus according to a first embodiment of the present invention.

  In FIG. 1, the semiconductor inspection apparatus of the present embodiment is embedded in a sample stage 6 on which a semiconductor wafer 5 is placed as an example of a sample to be inspected, and an insulating member 4 (for example, alumina, etc.) constituting the sample stage 6. An outer electrode 8 having a plurality of (for example, two) regions 181 and 182 (see FIG. 2 later) insulated from each other, and an outer electrode power source 11 for adjusting the potential of the outer electrode 8 with respect to the reference potential 26; A plurality of relays 10a and 10b for switching the connection state between the outer electrode 8 and the outer electrode power source 11 and a plurality of (for example, two) regions 191 and 192 embedded in the insulating member 4 constituting the sample stage 6 and insulated from each other. The connection state of the inner electrode 9 having (see FIG. 2 later), the inner electrode power source 13 for adjusting the potential of the inner electrode 9 with respect to the reference potential 26, and the inner electrode 9 and the outer electrode power source 11 is switched. A plurality of relays 12a, 12b, an electron gun 1 for irradiating the surface of the semiconductor wafer 5 placed on the sample stage 6 with the electron beam 3a, and secondary electrons 3b generated from the semiconductor wafer 5 by the irradiation of the electron beam 3a are detected. A plurality of (for example, three) push pins that constitute a sample lifting / lowering means for moving the semiconductor wafer 5 up and down with respect to the sample table 6. 22 and the push pin driving unit 23, an impedance measuring unit 19 for measuring the impedance between the respective regions of the electrodes 8 and 9, and a plurality of relays 17a for switching the connection state between the impedance measuring unit 19 and the respective regions of the electrodes 8 and 9. , 17b, 17c, 17d, the charge removal processing unit 25 for removing the bias of the charge distribution between the regions of the electrodes 8, 9, and the connection state between the charge removal processing unit 25 and the regions of the electrodes 8, 9 A plurality of relays 18a, 18b, 18c, 18d to be replaced, a ground needle 24 for setting the potential of the semiconductor wafer 5 placed on the sample stage 6 to the reference potential 26, and driving the ground needle 24 to connect the semiconductor wafer 5 A ground needle drive unit 20 that adjusts the contact state, a retarding power source 15 that is provided between the ground potential 27 and the reference potential 26 and adjusts the potential of the reference potential 26 with respect to the ground potential 27, the retarding power source 15 and the reference potential 26, the relay 14 for switching the connection state between the retarding power supply 15 and the reference potential 26, the resistor 16 for connecting the ground potential 27 and the reference potential 26, and the overall control for controlling the operation of the entire semiconductor inspection apparatus. Part 21.

  2 and 3 are cross-sectional views showing details of the sample stage 6 of FIG. 1, FIG. 2 is a plan cross-sectional view taken along line BB of the sample stage 6 shown in FIG. 3, and FIG. 3 is shown in FIG. It is side surface sectional drawing in the AA line of the sample stand 6 which was prepared.

  2 and 3, the sample stage 6 includes the insulating member 4, the outer electrode 8, the inner electrode 9, the push pin 22, and the push pin driving unit 23 as described above.

  As shown in FIG. 2, the inner electrode 9 has a disk shape, and is disposed in the center portion of the disk-shaped sample stage 6. The outer electrode 8 has an annular shape and is disposed so as to surround the inner electrode 9. The outer electrode 8 and the inner electrode 9 are insulated by the insulating member 4. As shown in FIG. 3, the outer electrode 8 and the inner electrode 9 are configured to be embedded in the insulating member 4 of the sample table 6 and insulated from the semiconductor wafer 5 placed on the sample table 6.

  The inner electrode 9 has two semicircular regions 191 and 192 provided to be insulated from each other. The outer electrode 8 has two regions 181 and 182 that are concentrically provided around the inner electrode 9. The regions 181 and 182 are also insulated from each other.

  In the central portion of the sample stage 6, three push pins 22 are provided, which are arranged through the sample stage 6 and the inner electrode 9 in the vertical direction. The three push pins 22 are arranged at positions that are vertices of a triangle (for example, a regular triangle) having the center of gravity of the semiconductor wafer 5 placed on the sample stage 6 as the center of gravity. One end on the upper side of each push pin 22 can protrude above the sample stage 6 and is provided so as to be in contact with the semiconductor wafer 5. Further, the lower end of each push pin 22 has a push pin drive unit 23 that drives each push pin 22 in the vertical direction based on an operation signal 121 (see FIG. 1) from the elevation control unit 21a of the overall control unit 21. It is connected to the. The push pin 22 is driven by the driving unit 23 to support the semiconductor wafer 5 from the sample stage 6 side, thereby moving the semiconductor wafer 5 up and down with respect to the sample stage 6. The semiconductor wafer 5 is placed on the sample stage 6 by placing the semiconductor wafer 5 on the push pin 22 projected on the sample stage 6 by a sample placing mechanism (not shown) and lowering the push pin 22. . Further, the semiconductor wafer 5 placed on the sample stage 6 is pushed up from the sample stage 6 side by lifting the push pin 22 and is detached from the sample stage 6. Thus, the push pin 22 and the push pin driving unit 23 constitute a sample lifting / lowering unit that lifts and lowers the semiconductor wafer 5 with respect to the sample stage 6.

  Returning to FIG.

  The power supply 11 for the outer electrode adjusts the potential of the outer electrode 8 with respect to the reference potential 26. In the present embodiment, the region 181 of the outer electrode 8 is connected via the relay 10a and the region 182 via the relay 10b. The region 181 of the outer electrode 8 is connected to the outer electrode power source 11 when the relay 10a is in the closed position, and is disconnected from the outer electrode power source 11 when it is in the open position. The potential of the region 181 with respect to the reference potential 26 is adjusted by applying the voltage by the outer electrode power source 11 with the relay 10a in the closed position. The same applies to the region 182. That is, the region 182 is connected to the outer electrode power source 11 when the relay 10b is in the closed position, and is disconnected from the outer electrode power source 11 when it is in the open position. Further, the potential of the region 182 with respect to the reference potential 26 is adjusted by applying the voltage by the outer electrode power source 11 with the relay 10b in the closed position.

  The inner electrode power source 13 adjusts the potential of the inner electrode 9 with respect to the reference potential 26. In this Embodiment, it connects with the area | region 191 of the inner side electrode 9 via the relay 12a, and the area | region 192 via the relay 12b. The region 191 of the inner electrode 9 is connected to the inner electrode power source 13 when the relay 12a is in the closed position, and is disconnected from the inner electrode power source 13 when it is in the open position. The potential of the region 191 with respect to the reference potential 26 is adjusted by applying the voltage by the inner electrode power source 13 with the relay 12a in the closed position. The same applies to the region 192. That is, the region 192 is connected to the inner electrode power source 13 when the relay 12b is in the closed position, and is disconnected from the inner electrode power source 13 when the relay 12b is in the open position. Further, the potential of the region 192 relative to the reference potential 26 is adjusted by applying the voltage by the inner electrode power source 13 with the relay 12b in the closed position.

  The relays 10a and 10b and the relays 12a and 12b are closed, a positive voltage with respect to the reference potential 26 is applied to the regions 181 and 182 (that is, the outer electrode 8), and the regions 191 and 192 (that is, the inner electrode 9) are applied. When a potential difference is generated between the outer electrode 8 and the inner electrode 9 by applying a negative voltage with respect to the reference potential 26, dielectric polarization occurs in the semiconductor wafer 5 placed on the sample stage 6, and the outer electrode 8 and the inner electrode An electrostatic force is generated between the electrode 9 and the semiconductor wafer 5. The semiconductor wafer 5 is attracted and fixed to the sample stage 6 by this electrostatic force. Thus, the insulating member 4 and the electrodes 8 and 9 of the sample stage 6 constitute a bipolar electrostatic chuck that attracts the semiconductor wafer 5 to the sample stage 6 by electrostatic force. A negative voltage with respect to the reference potential 26 may be applied to the regions 181 and 182 (that is, the outer electrode 8), and a positive voltage with respect to the reference potential 26 may be applied to the regions 191 and 192 (that is, the inner electrode 9).

  The impedance measuring unit 19 measures impedance between a plurality of regions of the outer electrode 8 and impedance between a plurality of regions of the inner electrode 9. In the present embodiment, the impedance measuring unit 19 measures the impedance between the two regions 181 and 182 of the outer electrode 8 and the impedance between the two regions 191 and 192 of the inner electrode 9. Are connected to the regions 181 and 182 of the outer electrode 8 and the regions 191 and 192 of the inner electrode 9 through relays 17a, 17b, 17c and 17d. The region 181 of the outer electrode 8 is connected to the impedance measurement unit 19 when the relay 17a is in the closed position, and is disconnected from the impedance measurement unit 19 when it is in the open position. The same applies to the region 182 of the outer electrode 8 and the regions 191 and 192 of the inner electrode 9. That is, the region 182 of the outer electrode 8 and the regions 191 and 192 of the inner electrode 9 are connected to the impedance measuring unit 19 when the relays 17b, 17c and 17d are in the closed position, respectively, and impedance measurement is performed when they are in the open position. The connection with the unit 19 is interrupted. The impedance measuring unit 19 measures the impedance between the two regions 181 and 182 of the outer electrode 8 with the relays 17 a and 17 b switched to the closed position, and sends the measurement result 112 to the overall control unit 21. Further, the impedance between the two regions 191 and 192 of the inner electrode 9 is measured with the relays 17c and 17d switched to the closed position, and the measurement result 134 is sent to the overall control unit 21.

  The neutralization processing unit 25 performs a neutralization process that eliminates the dielectric polarization generated in the semiconductor wafer 5 and removes the electrostatic attraction force of the sample stage 6 to the semiconductor wafer 5, and the neutralization processing unit 25 of the present embodiment. Are connected to the regions 181 and 182 of the outer electrode 8 and the regions 191 and 192 of the inner electrode 9 via relays 18a, 18b, 18c and 18d. The region 181 of the outer electrode 8 is connected to the static elimination processing unit 25 when the relay 18a is in the closed position, and is disconnected from the static elimination processing unit 25 when in the open position. The same applies to the region 182 of the outer electrode 8 and the regions 191 and 192 of the inner electrode 9. That is, the region 182 of the outer electrode 8 and the regions 191 and 192 of the inner electrode 9 are connected to the static elimination processing unit 25 when the relays 18b, 18c, and 18d are in the closed position, respectively, and are neutralized when they are in the open position. The connection with the unit 25 is cut off.

  As the charge removal process by the charge removal processing unit 25, for example, a charge that gradually decreases in the opposite direction to the case where the semiconductor wafer 5 is attracted to the sample stage 6 by electrostatic force between the outer electrode 8 and the inner electrode 9 is applied. Processing, static elimination processing in which a voltage in the same direction and a voltage in the opposite direction are applied while decreasing the amplitude alternately when the semiconductor wafer 5 is attracted to the sample stage 6 by electrostatic force, static elimination processing for grounding the electrodes 8 and 9, etc. There is.

  The ground needle 24 is disposed between the outer electrode 8 and the inner electrode 9 of the sample stage 6 so as to pass the sample stage 6 in the vertical direction. One end on the upper side of the ground needle 24 can protrude above the sample stage 6 and is provided so as to be in contact with the semiconductor wafer 5. The lower end of the ground needle 24 is connected to the reference potential 26 via the ground needle driving unit 20 that drives the ground needle 24 in the vertical direction based on a signal (not shown) from the overall control unit 21. The ground needle 24 is at the same potential as the reference potential 26. The ground needle 24 is driven by the ground needle drive unit 20 and brought into contact with the semiconductor wafer 5, thereby bringing the semiconductor wafer 5 into conduction with the reference potential 26.

  The retarding power supply 15 adjusts the potential of the reference potential 26 with respect to the ground potential 27, and is connected to the ground potential 27 and connected to the reference potential 26 via the relay 14. For the purpose of stabilizing the reference potential 26, a resistor 16 is connected in parallel with the retarding power source 15 and the relay 14 connected in series between the reference potential 26 and the ground potential 27. When the relay 14 is in the closed position, the reference potential 26 is adjusted by the retarding power source 15, and a closed circuit is formed by the retarding power source 15, the relay 14, and the resistor 16, and the reference potential 26 is stabilized. When the relay 14 is in the open position, charge is transferred through the resistor 16, and the reference potential 26 becomes the same potential as the ground potential 27.

  The retarding power supply 15 configured and arranged in this way adjusts the reference potential 26 applied to the semiconductor wafer 5 via the ground needle 24, thereby controlling the electrons constituting the electron beam 3a irradiated from the electron gun 1. A deceleration electric field is generated, and landing energy of the electrons to the semiconductor wafer 5 is adjusted. Thus, the reference potential 26 when focusing on the landing energy adjustment of electrons to the semiconductor wafer 5 is particularly called a retarding potential. Note that the outer electrode power source 11 and the inner electrode power source 13 that apply voltages to the outer electrode 8 and the inner electrode 9, respectively, are based on the reference potential 26, and are electrostatic chucks for adjusting and changing the retarding potential. The applied voltage balance (the potential balance between the applied voltage by the outer electrode power supply 11 and the applied voltage by the inner electrode power supply 13) can be kept constant.

  The overall control unit 21 includes an elevation control unit 21 a that controls the operation of the push pin drive unit 23 based on the impedance measurement result from the impedance measurement unit 19. In the present embodiment, the elevation control unit 21 a outputs an operation signal 121 based on the measurement results 112 and 134 from the impedance measurement unit 19 and controls the operation of the push pin drive unit 23. The overall control unit 21 controls the operation of the entire semiconductor inspection apparatus. The operation of the impedance measurement unit 19 and the charge removal processing unit 25, the operation of the ground needle drive unit 20, and the relays 10a, 10b, 12a, 12b. , 14, 17a,..., 17d, 18a,..., 18d, and the voltage applied by each power source 11, 13, 15 are controlled. The overall control unit 21 controls the operation of the electron gun 1, detector 7, lens, scanner (not shown) and the like, and the electron beam 3 a emitted from the electron gun 1 is applied to the surface of the semiconductor wafer 5. The secondary electron generated from the semiconductor wafer 5 is detected by the detector 7, the surface image of the semiconductor wafer 5 is generated from the information on the scanning position and the detection information of the secondary electrons, and the semiconductor wafer 5 is used using this surface image. The surface inspection process (not detailed) is performed.

  Next, the inspection process of the semiconductor inspection apparatus according to the present embodiment will be briefly described. First, as an initial state, all relays 10a, 10b, 12a, 12b, 14, 17a, ..., 17d, 18a, ..., 18d are opened, and the push pin 22 and the ground needle 24 are lowered (samples). (A position that does not protrude from the base 6). Next, the push pin 22 is raised, the semiconductor wafer 5 is placed on the push pin 22 by a sample moving mechanism (not shown), the push pin 22 is lowered, and the semiconductor wafer 5 is placed on the sample stage 6. Then, the relays 10 a, 10 b, 12 a, 12 b are switched to the closed position, a voltage is applied to the outer electrode 8 and the inner electrode 9, and the semiconductor wafer 5 is attracted to the sample stage 6. Thereafter, the ground needle 24 is raised and brought into contact with the semiconductor wafer 5, the relay 14 is switched to the closed position, and the reference potential 26 is adjusted by the retarding power source 25. In this state, the above-described surface inspection process is performed on the semiconductor wafer 5. Thereafter, the semiconductor wafer 5 is detached from the sample stage 6 (inspected sample removal process) (see FIG. 4).

  FIG. 4 is a flowchart showing the processing contents of the specimen removal processing to be inspected by the overall control unit 21 including the elevation control unit 21a.

  The overall control unit 21 first switches the relay 14 to the open position (step S01), then switches the relays 10a, 10b, 12a, and 12b to the open position (step S02), and the ground needle 24 is moved by the ground needle drive unit 20. The ground needle 24 and the semiconductor wafer 5 are made non-conductive (step S03), and the relays 17a,..., 17d are switched to the closed position (step S04).

  Here, the push pin drive unit 23 starts to raise the push pin 22 (step S05). When a predetermined time elapses after the push pin 22 starts to rise, the impedance measuring unit 19 causes the two of the outer electrodes 8 to rise. The impedance between the regions 181 and 182 and the impedance between the two regions 191 and 192 of the inner electrode 9 are measured to obtain measurement results 112 and 134 (step S06).

  Here, it is determined whether or not the measurement results 112 and 134 acquired in step S06 are larger than a predetermined threshold (step S07). If the determination result is YES, the push pin 22 is raised to a specified position and the sample is moved. The semiconductor wafer 5 is detached from the table 6 (step S08), and the sample separation process is completed. If the determination result in step S07 is NO, the push pin 22 is switched to the lowering operation and lowered to the lowered position (steps S70, S71), and the abnormality detection count is incremented by 1 (step S72). .

  Here, it is determined whether or not the number of abnormality detections is greater than a predetermined set value (step S73). If the determination result is YES, an abnormality detection signal is transmitted to a host control device (not shown) ( Step S74), the specimen removal process is terminated. If the determination result in step S73 is YES, the relays 17a, ..., 17d are switched to the open position (step S75), the relays 18a, ..., 18d are switched to the closed position (step S76), and static elimination The charge removal process is performed by the processing unit 25 (step S77). Thereafter, the relays 18a,..., 18d are switched to the open position (step S78), the process returns to step S04, and the inspected sample removal process is repeated.

  5 to 8 show the elapsed time when the semiconductor wafer 5 placed on the sample stage 6 is pushed up (removed) from the sample stage 6 side by the push pin 22 and the impedance between the regions 181 and 182 of the outer electrode 8. FIG. 5 is a diagram showing an example of the relationship of measured values 134, FIG. 5 shows the relationship when normally separated, FIG. 6 shows the relationship when partially separated, and FIG. 7 shows the relationship when not separated. FIG. 8 is a diagram showing the relationships shown in FIGS. 5 to 7 together. 5 to 8, the horizontal axis represents the time since the push pin 22 started to rise, and the vertical axis represents the impedance measurement value 134.

  FIG. 5 shows a case where the residual adsorption force is not generated between the sample stage 6 and the semiconductor wafer 5 and the semiconductor wafer 5 is normally detached from the sample stage 6. As shown in FIG. 5, at time 0 to t1, the impedance is constant at Zd. When time t1 is exceeded, the impedance increases with time, and after time t3, impedance is constant at Ze. Considering the relationship between the sample stage 6 and the semiconductor 5 in the case of FIG. 5, at time 0 to t1, the push pin 22 starts to rise from the lowered position at time 0 and comes into contact with the semiconductor wafer 5 at time t1. The impedance during this period is constant. From time t1 to time t3, the semiconductor wafer 5 is pushed up by the push pin 22 and detached from the sample stage 6, so that the distance (gap length) between the sample stage 6 and the semiconductor wafer 5 becomes longer and the impedance becomes larger. The separation of the semiconductor wafer 5 from the sample stage 6 is completed at time t3, and the impedance becomes constant.

  FIG. 6 shows a case where a residual attracting force is generated between the sample stage 6 and the semiconductor wafer 5 and the semiconductor wafer 5 is not partly detached in the range of the outer electrode 8 of the sample stage 6. As shown in FIG. 6, at time 0 to t1, the impedance is constant at Zd. When time t1 is exceeded, the impedance increases with time, and at time t4 (> t3), the impedance becomes Ze. Considering the relationship between the sample stage 6 and the semiconductor 5 in the case of FIG. 6, at time 0 to t1, the push pin 22 starts to rise from the lowered position at time 0 and comes into contact with the semiconductor wafer 5 at time t1. The impedance during this period is constant. From time t1 to time t4, the contact portion of the semiconductor wafer 5 with the push pin 22 is locally pushed up to increase the gap length, and the other portions are separated from each other due to the influence of the residual adsorption force. Compared to the case, the impedance increases gradually. In such a case, the semiconductor wafer 5 is warped. The separation of the semiconductor wafer 5 from the sample stage 6 is completed at time t4, and the impedance becomes Ze.

  FIG. 7 shows a case where a large residual adsorption force is generated between the sample stage 6 and the semiconductor wafer 5 and the semiconductor wafer 5 cannot be detached from the sample stage 6. As shown in FIG. 7, the impedance is constant at Zd from time 0 to t1, and the impedance does not change even after time t1 and is a constant value (Zd). Considering the relationship between the sample stage 6 and the semiconductor 5 in the case of FIG. 7, at time 0 to t1, the push pin 22 starts to rise from the lowered position at time 0 and contacts the semiconductor wafer 5 at time t1. The impedance during this period is constant. Even when the time t1 is exceeded, the state in which the semiconductor wafer 5 is attracted to the sample stage 6 by the residual attraction force is maintained, and the semiconductor wafer 5 cannot be pushed up by the push pins 22 and cannot be detached from the sample stage 6.

  The impedance measurement value 134 between the regions 191 and 192 of the inner electrode 9 has the same relationship as that of the outer electrode 8. That is, when no residual adsorption force is generated between the sample stage 6 and the semiconductor wafer 5 and the semiconductor wafer 5 is normally detached from the sample stage 6, the same relationship as in FIG. When a residual attracting force is generated between the wafers 5 and the semiconductor wafer 5 is not partly removed normally within the range of the inner electrode 9 of the sample stage 6, the same relationship as in FIG. When a large residual adsorption force is generated between the wafers 5 and the semiconductor wafer 5 cannot be detached from the sample stage 6, the same relationship as in FIG.

  FIG. 8 is a diagram showing the relationships shown in FIGS. 5 to 7 together. In the inspected sample detachment process according to the present embodiment, as shown in FIG. 8, for example, the threshold values at which the measured impedance values 112 and 134 at time t2 when t1 <t2 <t3 satisfy Zc <Zb <Za. When the value is larger than Zb, it is determined that the semiconductor wafer 5 has been normally detached from the sample stage 6, and when the measured impedance values 112 and 134 are smaller than a predetermined threshold value Zb, the separation is abnormal. Is determined to have occurred. This is because, as shown in FIG. 8 (FIGS. 5 to 7), the impedance differs depending on the detached state of the semiconductor wafer 5 with respect to the sample stage 6, so that the detached state can be determined from the measured value of this impedance. This was conceived based on the knowledge of the present inventors.

  The operation of the present embodiment configured as described above will be described.

  In the semiconductor sample inspection apparatus according to the present embodiment, as an initial state, all relays 10a, 10b, 12a, 12b, 14, 17a,..., 17d, 18a,. The pin 22 and the ground needle 24 are moved to a lowered position (a position that does not protrude from the sample stage 6). Next, the push pin 22 is raised, the semiconductor wafer 5 is placed on the push pin 22 by a sample moving mechanism (not shown), the push pin 22 is lowered, and the semiconductor wafer 5 is placed on the sample stage 6. Then, the relays 10 a, 10 b, 12 a, 12 b are switched to the closed position, a voltage is applied to the outer electrode 8 and the inner electrode 9, and the semiconductor wafer 5 is attracted to the sample stage 6. Thereafter, the ground needle 24 is raised and brought into contact with the semiconductor wafer 5, the relay 14 is switched to the closed position, and the reference potential 26 is adjusted by the retarding power source 25. In this state, the surface of the semiconductor wafer 5 is scanned with the electron beam 3a from the electron gun 1, the secondary electrons 3b generated from the semiconductor wafer 5 are detected by the detector 7, and the information on the scanning position and the detection information of the secondary electrons are detected. A surface image of the semiconductor wafer 5 is generated, and surface inspection processing (not detailed) of the semiconductor wafer 5 is performed using the surface image.

  Thereafter, the semiconductor wafer 5 is detached from the sample stage 6 (inspected sample removal process). In the sample separation process, first, the relays 14, 10a, 10b, 12a, and 12b are switched to the open position (steps S01 and S02 in FIG. 4), and the ground needle 24 and the semiconductor wafer 5 are made non-conductive (step in FIG. 4). S03), the relays 17a,..., 17d are switched to the closed position (step S04 in FIG. 4). Here, the rise of the push pin 22 is started, and when the predetermined time t2 has elapsed from the start of the rise of the push pin 22, the impedance measurement unit 19 acquires the measurement results 112 and 134 (step S05 in FIG. 4). , S06).

  If the measurement results 112 and 134 are larger than the predetermined threshold value Zb, the push pin 22 is raised to the specified position and the process is terminated (steps S07 and S08 in FIG. 4). If the measurement results 112 and 134 are smaller than the threshold value Zb, the push is performed. The pin 22 is lowered to perform the charge removal process, and the inspected sample detachment process is repeated (steps S07 and S70 to S78 in FIG. 4). Further, when the number of times determined to be smaller than the threshold value Zb is greater than a predetermined set value, an abnormality detection signal is transmitted to the host control device (step S74 in FIG. 4), and the specimen removal process is performed. Exit.

  The effect in this Embodiment comprised as mentioned above is demonstrated.

  In a semiconductor inspection apparatus using an electrostatic chuck that holds an inspected sample such as a semiconductor wafer using electrostatic force, the voltage application to the electrostatic chuck is stopped when the inspected sample is detached from the sample stage. In some cases, the adsorption force due to electrostatic force may remain. In such a state, if an attempt is made to separate the semiconductor wafer by a mechanism such as a push pin that pushes up the semiconductor wafer from the sample stage side, the sample to be inspected does not leave the sample stage due to the residual adsorption force, or the semiconductor wafer warps due to local separation. Furthermore, there is a risk that friction occurs between the push pin or the sample stage and the sample to be inspected to become a dust generation source.

  On the other hand, in the present embodiment, when the residual adsorption force is present, the semiconductor wafer 5 is not detached from the sample stage 6, so that dust generation when the sample is detached from the sample stage is suppressed. Can do. Thereby, it is possible to suppress the quality deterioration and the yield reduction of the semiconductor wafer 5 due to the foreign matter generated by the dust generation.

  Further, the outer electrode 8 is provided with the regions 181 and 182, and the inner electrode 9 is provided with the regions 191 and 192. The impedance measurement value 112 between the regions 181 and 182 of the outer electrode 8 and the region 191 and 192 of the inner electrode 9 are provided. Impedance measurement value 134 is obtained, and the presence / absence of residual adsorption force is determined for each of the position of the outer electrode 8 and the position of the inner electrode 9, so that the arrangement portion of the outer electrode 8 on the sample stage 6 and the inner electrode In each of the nine arrangement portions, the separation state of the semiconductor wafer 5 can be confirmed, and the improvement can be achieved more efficiently.

  In the present embodiment, the configuration is such that the detached state of the semiconductor wafer 5 is determined by comparing the impedance measurement values 112 and 134 at a predetermined time t2 with a threshold value. However, the present invention is not limited to this. The separation state of the semiconductor wafer 5 may be determined by comparing the rate of change of the impedance measurement value at a predetermined time with a threshold value for a predetermined rate of change.

<Second Embodiment>
In the first embodiment, the outer electrode 8 has two regions 181 and 182 provided concentrically around the inner electrode 9, whereas the second embodiment has the outer electrode 8. 8A has a plurality of (for example, six) regions 281,..., 286 arranged side by side so as to surround the inner electrode 9, and pushes based on the measurement results of the impedance between these regions. The operation of the pin 22 is controlled.

  9 and 10 are cross-sectional views showing details of the sample stage 6A of the present embodiment, FIG. 9 is a plan cross-sectional view taken along the line DD of the sample stage 6A shown in FIG. 10, and FIG. It is side surface sectional drawing in the CC line | wire of the electrostatic chuck shown in FIG. 9 and 10, the same members as those shown in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  9 and 10, the sample stage 6 </ b> A includes the insulating member 4, the outer electrode 8 </ b> A, the inner electrode 9, the push pin 22, and the push pin driving unit 23.

  As shown in FIG. 9, the inner electrode 9 has a disk shape, and is arranged at the center portion of the disk-shaped sample stage 6A. The outer electrode 8A has an annular shape and is arranged so as to surround the inner electrode 9. The outer electrode 8A and the inner electrode 9 are insulated by the insulating member 4. As shown in FIG. 10, the outer electrode 8A and the inner electrode 9 are configured to be embedded in the insulating member 4 of the sample stage 6A and insulated from the semiconductor wafer 5 placed on the sample stage 6A.

  The inner electrode 9 has two semicircular regions 191 and 192 provided to be insulated from each other. The outer electrode 8A has a plurality of (for example, six) regions 281,..., 286 arranged side by side so as to surround the inner electrode 9 in an annular shape. The regions 281,... 286 are also provided so as to be insulated from each other.

  The sample stage 6A is provided with three push pins 22 arranged through the sample stage 6A and the outer electrode 8A in the vertical direction. The three push pins 22 are arranged at positions that are vertices of a triangle (for example, a regular triangle) having the center of gravity of the semiconductor wafer 5 placed on the sample stage 6 as the center of gravity. One end on the upper side of each push pin 22 can protrude above the sample stage 6 </ b> A and is provided so as to be in contact with the semiconductor wafer 5. Further, the lower end of each push pin 22 has a push pin drive unit 23 that drives each push pin 22 in the vertical direction based on an operation signal 121 (see FIG. 1) from the elevation control unit 21a of the overall control unit 21. It is connected to the. The push pin 22 is driven by the drive unit 23 to support the semiconductor wafer 5 from the sample stage 6A side, thereby moving the semiconductor wafer 5 up and down relative to the sample stage 6A. The semiconductor wafer 5 is placed on the sample stage 6A by placing the semiconductor wafer 5 on the push pin 22 in a state of protruding onto the sample stage 6 by a sample placement mechanism (not shown) and lowering the push pin 22. The The semiconductor wafer 5 placed on the sample stage 6A is pushed up from the sample stage 6A side by lifting the push pin 22, and is detached from the sample stage 6A. As described above, the push pin 22 and the push pin driving unit 23 constitute sample lifting / lowering means for lifting / lowering the semiconductor wafer 5 with respect to the sample stage 6A.

  The plurality of regions 281,..., 286 of the outer electrode 8 </ b> A shown in the present embodiment are the outer electrode power source 11, the impedance measuring unit 19, and the charge removal processing unit, as in the first embodiment. Each of 25 is appropriately connected via a relay (not shown).

  As described in FIG. 1, the power supply 11 for the outer electrode adjusts the potential of the outer electrode 8A with respect to the reference potential 26, and each region 281 of the outer electrode 8 via a plurality of relays (not shown). .., 286 are connected.

  The impedance measuring unit 19 measures impedance between a plurality of regions of the outer electrode 8A and impedance between a plurality of regions of the inner electrode 9, and the outer electrode via a plurality of relays (not shown). , 286 of 8A and each of the regions 191 and 192 of the inner electrode 9 are connected. In the present embodiment, the impedance measuring unit 19 has the impedance between the regions of the plurality of (for example, six) regions in the outer electrode 8A, that is, the impedance and region between the regions 281 and 286 of the outer electrode 8A. The impedance between 282 and 283 and the impedance between the regions 284 and 285 are measured, and the measurement results are sent to the overall control unit 21. For the inner electrode 9, as in the first embodiment, the impedance between the regions 191 and 192 is measured, and the measurement result is sent to the overall control unit 21.

  The charge removal processing unit 25 performs a charge removal process for eliminating the dielectric polarization generated in the semiconductor wafer 5 and removing the electrostatic attraction force of the sample stage 6A on the semiconductor wafer 5, via a relay (not shown). , 286 of the outer electrode 8A and the regions 191 and 192 of the inner electrode 9 are connected.

  Other configurations are the same as those of the first embodiment.

  The operation in the present embodiment configured as described above will be described.

  In the semiconductor sample inspection apparatus according to the present embodiment, first, as an initial state, all relays are set to the open position, and the push pins 22 and the ground needle 24 are set to the lowered position (position not protruding from the sample stage 6). Next, the push pin 22 is raised, the semiconductor wafer 5 is placed on the push pin 22 by a sample moving mechanism (not shown), the push pin 22 is lowered, and the semiconductor wafer 5 is placed on the sample stage 6. Then, the relays (not shown) between the outer electrode power source 11 and the outer electrode 8A and the relays 12a and 12b between the inner electrode power source 13 and the inner electrode 9 are switched to the closed position, and the outer electrode 8A and the inner electrode 9 are switched. A voltage is applied to the semiconductor wafer 5 to attract the semiconductor wafer 5 to the sample stage 6A. Thereafter, the ground needle 24 is raised and brought into contact with the semiconductor wafer 5, the relay 14 is switched to the closed position, and the reference potential 26 is adjusted by the retarding power source 25. In this state, the surface of the semiconductor wafer 5 is scanned with the electron beam 3a from the electron gun 1, the secondary electrons 3b generated from the semiconductor wafer 5 are detected by the detector 7, and the information on the scanning position and the detection information of the secondary electrons are detected. A surface image of the semiconductor wafer 5 is generated, and surface inspection processing (not detailed) of the semiconductor wafer 5 is performed using the surface image.

  Thereafter, the semiconductor wafer 5 is detached from the sample stage 6A (inspected sample removal process). In the sample separation process, first, the relay 14, the relay (not shown) between the outer electrode power supply 11 and the outer electrode 8A, and the relays 12a and 12b between the inner electrode power supply 13 and the inner electrode 9 are opened. , 286 of each of the outer electrodes 8A and each of the regions 191 of the inner electrode 9 through a plurality of relays (not shown). , 192 and the impedance measuring unit 19 are switched to a closed position (not shown) and relays 17c and 17d. Here, when the push pin 22 starts to rise and when a predetermined time has elapsed since the push pin 22 starts to rise, the impedance measuring unit 19 causes the impedance between the regions 281 and 286 of the outer electrode 8A, the region 282. , 283, impedance between the regions 284 and 285, and impedance measurement results between the regions 191 and 192 of the inner electrode 9.

  If the measurement result is larger than a predetermined threshold value, the push pin 22 is raised to a specified position and the process is terminated. If the measurement result is smaller than the threshold value, the push pin 22 is lowered and the charge removal process is performed. Repeat the withdrawal process. Further, when the number of times determined to be smaller than the threshold value is greater than a preset value, an abnormality detection signal is transmitted to the host control device, and the inspected sample removal process is terminated.

  Also in the present embodiment configured as described above, the same effects as those of the first embodiment can be obtained.

  In addition, a plurality of (for example, six) regions 281,..., 286 are provided on the outer electrode 8 A so as to surround the inner electrode 9 in an annular shape, and the impedance between the regions 281, 286 of the outer electrode 8 A, Since the impedance between the regions 282 and 283 and the impedance measurement value between the regions 284 and 285 are configured to be acquired, a plurality of directions in the outer peripheral portion of the semiconductor wafer 5 in the arrangement portion of the outer electrode 8A in the sample stage 6A. The state of each separation can be confirmed, and improvement can be achieved more efficiently.

<Third Embodiment>
In this embodiment, the inner electrode 9 in the second embodiment is configured to have a plurality of (for example, six) regions 291,..., 296 arranged side by side so as to surround the center, and the outer electrode The operation of the push pin 22 is controlled based on the measurement result of the impedance between the plurality of regions of the 8A and the inner electrode 9A.

  11 and 12 are cross-sectional views showing the details of the sample stage 6B of the present embodiment, FIG. 11 is a plan cross-sectional view taken along the line FF of the sample stage 6B shown in FIG. 12, and FIG. It is side surface sectional drawing in the EE line | wire of the electrostatic chuck shown in FIG. 11 and 12, the same members as those shown in FIGS. 9 and 10 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  11 and 12, the sample stage 6 </ b> B includes the insulating member 4, the outer electrode 8 </ b> A, the inner electrode 9 </ b> A, the push pin 22, and the push pin driving unit 23.

  As shown in FIG. 11, the inner electrode 9A has a disk shape, and is arranged at the center of the disk-shaped sample stage 6B. The outer electrode 8A has an annular shape and is disposed so as to surround the inner electrode 9A. The outer electrode 8A and the inner electrode 9A are insulated by the insulating member 4. As shown in FIG. 10, the outer electrode 8A and the inner electrode 9A are configured to be embedded in the insulating member 4 of the sample stage 6B and insulated from the semiconductor wafer 5 placed on the sample stage 6B.

  The inner electrode 9A has a plurality of (for example, six) regions 291,..., 296 arranged side by side so as to surround the center thereof. The regions 291,..., 296 are provided so as to be insulated from each other. The outer electrode 8A has a plurality of (for example, six) regions 281,..., 286 arranged side by side so as to surround the inner electrode 9 in an annular shape. The regions 281,... 286 are also provided so as to be insulated from each other.

  The plurality of regions 291,..., 296 of the inner electrode 9 </ b> A shown in the present embodiment are the inner electrode power source 13, the impedance measuring unit 19, and the charge removal processing unit, as in the second embodiment. Each of 25 is appropriately connected via a relay (not shown).

  As described with reference to FIG. 1, the inner electrode power supply 13 adjusts the potential of the inner electrode 9A with respect to the reference potential 26, and each region 291 of the inner electrode 9A via a plurality of relays (not shown). .., 296 are connected.

  The impedance measuring unit 19 measures the impedance between the plurality of regions of the outer electrode 8A and the impedance between the plurality of regions of the inner electrode 9A, and the outer electrode via a plurality of relays (not shown). , 286 of the 8A and the regions 291,..., 296 of the inner electrode 9 are connected. In the present embodiment, the impedance measuring unit 19 has an impedance between regions that are a pair of a plurality of (for example, six) regions for the inner electrode 9A, that is, an impedance and region between the regions 291 and 296 of the inner electrode 9A. The impedance between 292 and 293 and the impedance between the regions 294 and 295 are measured, and the measurement results are sent to the overall control unit 21. For the side electrode 9, as in the second embodiment, the impedance between the regions 281 and 286, the impedance between the regions 282 and 283, and the impedance between the regions 284 and 285 are measured. The measurement result is sent to the overall control unit 21.

  The static elimination processing unit 25 performs a static elimination process for eliminating the dielectric polarization generated in the semiconductor wafer 5 and removing the electrostatic adsorption force of the sample stage 6B on the semiconductor wafer 5, and via a relay (not shown). , 286 of the outer electrode 8A and the regions 291,..., 296 of the inner electrode 9A.

  Other configurations are the same as those of the second embodiment.

  The operation in the present embodiment configured as described above will be described.

  In the semiconductor sample inspection apparatus of the present embodiment, first, as an initial state, all relays are set to the open position, and the push pins 22 and the ground needle 24 are set to the lowered position (positions that do not protrude from the sample stage 6B). Next, the push pin 22 is raised, the semiconductor wafer 5 is placed on the push pin 22 by a sample moving mechanism (not shown), and the push pin 22 is lowered to place the semiconductor wafer 5 on the sample stage 6B. Then, the relay (not shown) between the power supply 11 for the outer electrode and the outer electrode 8A and the relay (not shown) between the power supply 13 for the inner electrode and the inner electrode 9A are switched to the closed position, and the outer electrode 8A and the inner electrode 8A are switched. A voltage is applied to the electrode 9A to attract the semiconductor wafer 5 to the sample stage 6B. Thereafter, the ground needle 24 is raised and brought into contact with the semiconductor wafer 5, the relay 14 is switched to the closed position, and the reference potential 26 is adjusted by the retarding power source 25. In this state, the surface of the semiconductor wafer 5 is scanned with the electron beam 3a from the electron gun 1, the secondary electrons 3b generated from the semiconductor wafer 5 are detected by the detector 7, and the information on the scanning position and the detection information of the secondary electrons are detected. A surface image of the semiconductor wafer 5 is generated, and surface inspection processing (not detailed) of the semiconductor wafer 5 is performed using the surface image.

  Thereafter, the semiconductor wafer 5 is detached from the sample stage 6A (inspected sample removal process). In the sample separation process, first, the relay 14, the relay between the outer electrode power source 11 and the outer electrode 8A (not shown), and the relay between the inner electrode power source 13 and the inner electrode 9 (not shown) are used. Switching to the open position, the ground needle 24 and the semiconductor wafer 5 are made non-conductive, and the regions 281,..., 286 of the outer electrode 8 A and the inner electrodes 9 A are connected via a plurality of relays (not shown). A relay (not shown) that connects the regions 291,..., 296 and the impedance measuring unit 19 is switched to the closed position. Here, when the push pin 22 starts to rise and when a predetermined time has elapsed since the push pin 22 starts to rise, the impedance measuring unit 19 causes the impedance between the regions 281 and 286 of the outer electrode 8A, the region 282. , 283 and the impedance between the regions 284 and 285, the impedance between the regions 291 and 296 of the inner electrode 9A, the impedance between the regions 292 and 293, and the impedance between the regions 294 and 295 Get the measurement result.

  If the measurement result is larger than a predetermined threshold value, the push pin 22 is raised to a specified position and the process is terminated. If the measurement result is smaller than the threshold value, the push pin 22 is lowered and the charge removal process is performed. Repeat the withdrawal process. Further, when the number of times determined to be smaller than the threshold value is greater than a preset value, an abnormality detection signal is transmitted to the host control device, and the inspected sample removal process is terminated.

  In the present embodiment configured as described above, the same effects as those of the first and second embodiments can be obtained.

  In addition, a plurality of (for example, six) regions 291,..., 296 arranged side by side so as to surround the center of the inner electrode 9 A are provided, and the impedance between the regions 291, 296 of the inner electrode 9 A, the region 292, Since the impedance between 293 and the measured impedance between the regions 294 and 295 are acquired, the separation of the inner portion of the sample stage 6B in the center portion of the semiconductor wafer 5 in the plurality of directions is provided. The state can be confirmed, and improvement can be achieved more efficiently.

  Although several embodiments of the present invention have been described above, these embodiments can be variously modified and combined within the spirit of the present invention. For example, also in the second and third embodiments, the separation state of the semiconductor wafer 5 is determined by comparing the change rate of the impedance measurement value at a predetermined time with a threshold value for the predetermined change rate. It may be configured. In addition, a plurality of regions are provided in each of the inner electrode and the outer electrode, and the impedance between the regions is measured for each electrode. However, the present invention is not limited to this, and the region of the inner electrode and the region of the outer electrode are configured. You may comprise so that the impedance between may be measured. Further, the plurality of regions constituting the inner electrode are regarded as one region, and the plurality of regions constituting the outer electrode are regarded as one region, and the impedance between the inner electrode (region) and the outer electrode (region). You may comprise so that it may measure.

DESCRIPTION OF SYMBOLS 1 Electron gun 2 Vacuum container 3a Electron beam 3b Secondary electron 4 Insulating member 5 Semiconductor wafer 6 Sample stand 7 Detector 8 Outer electrode 9 Inner electrode 10a, 10b Relay 11 Outer electrode power source 12a, 12b Relay 13 Inner electrode power source 14 Relay 15 Retarding power supply 16 Resistors 17a, 17b, 17c, 17d Relays 18a, 18b, 18c, 18d Relay 19 Impedance measurement unit 20 Ground needle drive unit 21 Overall control unit 22 Push pin 23 Push pin drive unit 24 Ground needle 25 Static elimination process Part 26 Reference potential 27 Ground potential

Claims (11)

A sample stage on which the sample to be inspected is placed;
A plurality of electrodes provided on the sample stage;
Insulating means for electrically insulating the plurality of electrodes and the sample to be inspected;
Voltage applying means for applying a voltage between at least one pair of the plurality of electrodes;
Measuring means for measuring impedance between at least one pair of electrodes of the plurality of electrodes;
Sample elevating means for elevating the sample to be inspected with respect to the sample stage based on an operation signal;
A semiconductor sample inspection apparatus comprising: an elevation control means for sending an operation signal to the sample elevation means based on a measurement result from the measurement means. A sample stage on which the sample to be inspected is placed;
A plurality of electrodes provided on the sample stage and having a plurality of regions insulated from each other;
Insulating means for electrically insulating the plurality of electrodes and the sample to be inspected;
Voltage applying means for applying a voltage between at least one pair of the plurality of electrodes;
Measuring means for measuring impedance between at least one pair of electrodes in the plurality of regions;
Sample elevating means for elevating the sample to be inspected with respect to the sample stage based on an operation signal;
A semiconductor sample inspection apparatus comprising: an elevation control means for sending an operation signal to the sample elevation means based on a measurement result from the measurement means. In the semiconductor sample inspection apparatus according to claim 1 or 2,
Further comprising static elimination means for removing electrostatic force between the plurality of electrodes provided on the sample stage and the sample to be inspected,
If the measurement result of the measurement means when a predetermined time has elapsed after outputting the operation signal for raising the sample to be inspected is less than a predetermined set value, the elevation control means A semiconductor sample inspection apparatus characterized by performing a charge removal process by means. In the semiconductor sample inspection apparatus according to claim 1 or 2,
Further comprising static elimination means for removing electrostatic force between the plurality of electrodes provided on the sample stage and the sample to be inspected,
When the elevating control means has a change rate of the measurement result of the measuring means when a predetermined time has elapsed after outputting the operation signal for raising the sample to be inspected, when the change rate is smaller than a predetermined set value A semiconductor sample inspection apparatus that performs a charge removal process by the charge removal means. The semiconductor sample inspection apparatus according to claim 3,
The elevating control means outputs an abnormal signal when the number of times of the static elimination processing reaches a set number. The semiconductor sample inspection apparatus according to claim 1,
The semiconductor sample inspection apparatus, wherein the plurality of electrodes are arranged in a plurality of rows concentrically. The semiconductor sample inspection apparatus according to claim 2,
The semiconductor sample inspection apparatus, wherein the plurality of electrodes and the plurality of regions are arranged in a plurality of rows concentrically. The semiconductor sample inspection apparatus according to claim 2,
The semiconductor sample inspection apparatus, wherein the plurality of electrodes are arranged in a plurality of concentric rows, and the plurality of regions are arranged in a circumferential direction. In the semiconductor sample inspection apparatus according to claim 1 or 2,
An electron gun that irradiates the specimen with an electron beam;
A vacuum chamber that houses the sample stage and the electron beam irradiation unit of the electron gun; and a power source that applies a voltage to the sample to be inspected with respect to the electron beam irradiation unit of the electron gun. A semiconductor sample inspection apparatus characterized by the above. A procedure for measuring an impedance between at least one pair of electrodes of a plurality of electrodes provided on a sample stage on which the sample to be inspected is placed and electrically insulated from the sample to be inspected;
A semiconductor sample inspection method comprising: a step of moving the sample to be inspected up and down with respect to the sample stage based on the measurement result. A procedure for measuring impedance between at least one pair of electrodes in a plurality of regions provided in a plurality of electrodes provided on a sample stage on which a sample to be inspected is placed and electrically insulated from the sample to be inspected;
A semiconductor sample inspection method comprising: a step of moving the sample to be inspected up and down with respect to the sample stage based on the measurement result.

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