JP2011013485A - Liquid crystal display device and method for pixel wiring - Google Patents

Abstract

An object of the present invention is to mitigate a decrease in aperture ratio due to a margin for short circuit prevention.
A plurality of color display pixels P composed of RGB subpixels PX, a plurality of thin film transistors W provided at a ratio of three to each color display pixel P, and a ratio of three to the color display pixels P of each row , A plurality of signal lines X provided for one color display pixel P in each column, and two for each color display pixel P provided for each row. A plurality of auxiliary capacitance lines CL that are capacitively coupled to the pixel electrode PE of PX are included. Two of the RGB subpixels PX constituting each color display pixel P are arranged between two first and second scanning lines adjacent to the three corresponding scanning lines Y, and the remaining one of the RGB subpixels PX. Are arranged between two second and third scanning lines adjacent to three corresponding scanning lines, and the RGB corresponding subpixel PX is driven by three corresponding thin film transistors Y through three corresponding thin film transistors. It is connected to one corresponding signal line X via W.
[Selection] Figure 1

Description

  The present invention relates to a liquid crystal display device including a storage capacitor line capacitively coupled to a pixel electrode and a pixel wiring method thereof.

  Liquid crystal display devices are used as displays for various electronic devices because of their advantages of light weight, thinness, and low power consumption. This liquid crystal display device usually has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate. For example, in an active matrix type liquid crystal display device, an array substrate is arranged as a pixel switching element at a plurality of scanning lines, a plurality of signal lines arranged so as to cross these scanning lines, and a position where these scanning lines and signal lines intersect. A plurality of thin film transistors, and a plurality of pixel electrodes respectively connected to the thin film transistors. The counter substrate includes a common electrode facing the plurality of pixel electrodes. The plurality of pixel electrodes and the common electrode constitute a plurality of liquid crystal pixels in cooperation with the pixel region of the liquid crystal layer located between the electrodes.

  Each thin film transistor applies the pixel voltage from the corresponding signal line to the corresponding pixel electrode when driven through the corresponding scanning line. On the other hand, a common voltage is applied to the common electrode. The pixel electrode and the common electrode of each liquid crystal pixel are capacitively coupled through a liquid crystal layer, thereby forming a liquid crystal capacitor that holds a potential difference between the pixel electrode and the common electrode as a liquid crystal driving voltage. Further, in order to suppress the fluctuation of the liquid crystal driving voltage, an auxiliary capacitor is connected in parallel with the liquid crystal capacitor (see, for example, Patent Document 1). The light transmittance of the liquid crystal pixel is set corresponding to the liquid crystal molecule orientation controlled by such a liquid crystal driving voltage.

  In a liquid crystal display device for color display, red (R), green (G), and blue (B) color filters are superimposed on a plurality of liquid crystal pixels in order to obtain RGB subpixels of color display pixels. The RGB sub-pixels are generally long in the direction in which the signal lines extend (= column direction) and are arranged in the direction in which the scanning lines extend (= row direction), but are long in the direction in which the scanning lines extend due to restrictions such as drivers. The signal lines may be arranged in the direction in which the signal lines extend.

JP-A-8-320496

  By the way, each of the plurality of scanning lines is on the same plane as the plurality of auxiliary capacitor lines as the gate lines of the thin film transistors in the corresponding row on the array substrate, and each auxiliary capacitor line is a pixel in the corresponding row in order to obtain the above-described auxiliary capacitor. It is capacitively coupled with the electrode and extends in the direction in which the scanning line extends.

  Each auxiliary capacitance line needs to be separated from a neighboring scanning line so as to secure a margin for preventing a short circuit. For this reason, especially when the RGB subpixels are arranged in the direction in which the signal line extends in a shape that is long in the direction in which the scanning line extends, the occupation ratio of the dead space in the pixel increases. This significantly lowers the aperture ratio of the pixels as compared with the case where the RGB sub-pixels are long in the direction in which the signal lines extend and are arranged in the direction in which the scanning lines extend.

  An object of the present invention is to provide a liquid crystal display device and a pixel wiring method thereof that can alleviate a decrease in aperture ratio due to a short-circuit prevention margin.

  According to the first aspect of the present invention, a plurality of color display pixels each composed of three subpixels arranged in a delta arrangement and arranged in a matrix, and a ratio of three to each color display pixel is provided. A plurality of switching elements, a plurality of scanning lines provided at a ratio of three for the color display pixels in each row, a plurality of signal lines provided at a ratio of one for the color display pixels in each column, and each row And a plurality of auxiliary capacitance lines that are provided on the same plane as each scanning line at a ratio of two to each color display pixel and are capacitively coupled to the pixel electrodes of the corresponding sub-pixels. Two of the sub-pixels are arranged between the first and second scanning lines that are adjacent two of the three corresponding scanning lines, and the remaining one of the three sub-pixels is 3 The second and second adjacent two of the corresponding scanning lines Provided is a liquid crystal display device which is arranged between scanning lines and in which three sub-pixels are connected to one corresponding signal line via three corresponding switching elements which are respectively driven via three corresponding scanning lines. Is done.

  According to a second aspect of the present invention, there is provided a pixel wiring method for a liquid crystal display device including a plurality of color display pixels each including a plurality of subpixels arranged in a delta arrangement and arranged in a matrix. A plurality of switching elements are provided at a ratio of three to the pixels, a plurality of scanning lines are provided at a ratio of three to the color display pixels in each row, and a ratio of one to the color display pixels in each column. A plurality of signal lines are provided, and a plurality of auxiliary capacitance lines that are capacitively coupled to the pixel electrodes of the corresponding sub-pixels are provided on the same plane as each scanning line at a ratio of two for the color display pixels in each row, and each color display Two of the three sub-pixels constituting the pixel are arranged between the first and second scanning lines that are two adjacent ones of the three corresponding scanning lines, and of the three sub-pixels The remaining one is the adjacent two of the three corresponding scanning lines. And a method of wiring a wiring that is arranged between the third scanning lines and connects the three sub-pixels to one corresponding signal line via three corresponding switching elements respectively driven via the three corresponding scanning lines Is provided.

  In these liquid crystal display devices and pixel wiring methods thereof, the first and second scans in which two of the three sub-pixels constituting each color display pixel are adjacent two of the three corresponding scanning lines. The remaining one of the three sub-pixels is disposed between the lines, and is disposed between the second and third scanning lines that are adjacent two of the three corresponding scanning lines. Are connected to one corresponding signal line via three corresponding switching elements respectively driven via three corresponding scanning lines. In this case, one auxiliary capacitance line is omitted for every three scanning lines. Accordingly, it is possible to mitigate a decrease in the aperture ratio due to a margin for preventing a short circuit.

1 is a diagram schematically showing a circuit configuration of a liquid crystal display device according to a first embodiment of the present invention. It is a figure which shows roughly the cross-section of the liquid crystal display panel shown in FIG. It is a top view which shows the pixel wiring structure of the array substrate shown in FIG. It is sectional drawing which shows the pixel wiring structure of the array substrate along the IV-IV line | wire shown in FIG. It is a top view of the comparative example compared with the pixel wiring structure shown in FIG. It is sectional drawing of the comparative example along the VI-VI line shown in FIG. It is a figure which shows the modification of the color display pixel arrangement | sequence shown in FIG.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 schematically shows a circuit configuration of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel 10 in which a plurality of color display pixels P are arranged in a matrix, and a controller 20 that controls the liquid crystal display panel 10. The liquid crystal display panel 10 has a structure in which a liquid crystal layer 13 is sandwiched between an array substrate 11 and a counter substrate 12 which are a pair of electrode substrates. The liquid crystal layer 13 is obtained by filling the gap between the array substrate 11 and the counter substrate 12 with a liquid crystal material. In this liquid crystal display panel 10, as shown in FIG. 2, a pair of polarizing plates PL is attached to the outside of the array substrate 11 and the counter substrate 12, and the backlight BL for the light source is outside the polarizing plate PL on the array substrate 11 side. Placed in.

  As shown in FIG. 1, the array substrate 11 includes a plurality of scanning lines Y (Y1, Y2, Y3,...) And a plurality of signal lines X (X1, X2, X3,. ), A plurality of thin film transistors W arranged as pixel switching elements at intersections of the scanning lines Y and the signal lines X, a plurality of pixel electrodes PE respectively connected to the thin film transistors W, and a plurality of capacitors coupled to the pixel electrodes PE. Of the auxiliary capacitance line CL. In the array substrate 11, as shown in FIG. 2, a transparent insulating substrate GL made of a glass plate or the like is provided as a support substrate for a plurality of scanning lines Y, signal lines X, thin film transistors W, etc., and an alignment film AL is a plurality of pixel electrodes PE. Cover. The counter substrate 12 has a color filter CF composed of colored layers of red (R), green (G), and blue (B) selectively assigned to the plurality of pixel electrodes PE and a color facing the plurality of pixel electrodes PE. A common electrode CE disposed on the filter CF is included. In the counter substrate 12, as shown in FIG. 2, a transparent insulating substrate GL made of a glass plate or the like is provided as a support substrate for the color filter CF, and the alignment film AL covers the common electrode CE. Incidentally, each pixel electrode PE and common electrode CE are made of a transparent electrode material such as ITO. The plurality of pixel electrodes PE and the common electrode CE constitute a plurality of sub-pixels PX in cooperation with the pixel region of the liquid crystal layer 13 located between the electrodes PE and CE. The array substrate 11 is provided with the scanning line driver 30 for driving the plurality of scanning lines Y, and the signal line driver 40 is provided for driving the plurality of signal lines X. The scanning line driver 30 and the signal line driver 40 are controlled by the controller 20.

  FIG. 3 shows a pixel wiring structure of the array substrate 11 shown in FIG. Each color display pixel P includes three subpixels PX arranged in a delta arrangement facing the red (R), green (G), and blue (B) colored layers, that is, RGB subpixels PX. That is, these RGB subpixels PX are assigned to red, green and blue, respectively. Incidentally, the pixel electrode PE of the RGB sub-pixel PX has a longer shape in the direction (= row direction) in which the scanning line Y extends than in the direction (= column direction) in which the signal line X extends. The plurality of thin film transistors W are provided at a ratio of three for each color display pixel P. The plurality of scanning lines Y are provided at a ratio of three to the color display pixels P in each row. The plurality of signal lines X are provided at a ratio of one to the color display pixels P in each column. The plurality of auxiliary capacitance lines CL are provided at a ratio of two to the color display pixels P in each row, and are arranged on the same plane of the transparent insulating substrate GL as the respective scanning lines Y as shown in FIG. Capacitively coupled to the pixel electrode PE. The plurality of scanning lines Y and the plurality of auxiliary capacitance lines CL are insulated from the plurality of signal lines X by the insulating film INS, and the plurality of pixel electrodes PE are formed on the insulating film INS.

  Two of the RGB sub-pixels PX constituting each color display pixel P are arranged between the first and second scanning lines which are adjacent two of the three corresponding scanning lines Y, and the RGB sub-pixels PX Of the three corresponding scanning lines Y is disposed between the second and third scanning lines that are adjacent to each other, and the RGB sub-pixels PX pass through the three corresponding scanning lines Y. Each signal line X is connected to one corresponding signal line X through three corresponding thin film transistors W driven. Each scanning line Y is connected to the corresponding switching element W assigned to the subpixel PX of the same color. The color display pixels P in each row are arranged so that the top and bottom of the delta arrangement are alternately reversed.

  Each thin film transistor W applies the pixel voltage from the corresponding signal line X driven by the signal line driver 4 to the corresponding pixel electrode PE when driven by the scanning line driver 30 via the corresponding scanning line Y. On the other hand, the common voltage VCOM is applied to the common electrode CE. Here, the plurality of storage capacitor lines CL are connected so as to be set to the same potential as the common electrode CE. The pixel electrode PE and the common electrode CE of each subpixel PX are capacitively coupled via the liquid crystal layer 13 to form a liquid crystal capacitor Clc that holds a potential difference between the pixel electrode PE and the common electrode CE as a liquid crystal driving voltage. Each auxiliary capacitance line CL and the corresponding pixel electrode PE capacitively coupled to the auxiliary capacitance line CL constitute an auxiliary capacitance Cs that suppresses fluctuations in the liquid crystal driving voltage. The light transmittance of each sub-pixel PX is set corresponding to the liquid crystal molecule alignment controlled by the liquid crystal driving voltage.

  In the liquid crystal display device of this embodiment, as shown in FIG. 3, red (R) subpixels PX are provided in odd rows, green (G) subpixels PX are provided in both odd and even rows, and blue The sub-pixels PX in (B) are provided in even rows. Two of the RGB sub-pixels PX constituting each color display pixel P are arranged between the first and second scanning lines which are adjacent two of the three corresponding scanning lines Y, and the RGB sub-pixels PX The remaining one is disposed between the second and third scanning lines which are two adjacent ones of the three corresponding scanning lines Y. These RGB subpixels PX are connected to one corresponding signal line X via three corresponding switching elements, ie, thin film transistors W, which are driven via three corresponding scanning lines Y, respectively. These RGB subpixels PX have a delta arrangement different from the normal delta arrangement in which red (R), green (G), and blue (B) subpixels PX are provided in each row, but three corresponding scanning lines Y Are connected so as to drive the thin film transistors W of the red (R), green (G), and blue (B) subpixels PX, and these RGB subpixels PX are connected to the same corresponding signal line X via the thin film transistors W. Since they are connected, the scanning line driver 30 and the signal line driver 40 may have the same driving format as that applied in the case of the sub-pixel arrangement of the comparative example shown in FIGS. Furthermore, in this case, the distance that the scanning line Y and the auxiliary capacitance line CL cross the pixel electrode PE is reduced, and a plurality of scanning lines Y are bundled every other line. One auxiliary capacitance line CL is omitted. Accordingly, it is possible to mitigate a decrease in the aperture ratio due to a margin for preventing a short circuit. Incidentally, the average aperture ratio obtained with the pixel wiring of the comparative example shown in FIG. 5 is 44.2%, whereas the average aperture ratio obtained with the pixel wiring shown in FIG. 1 is 49%.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

  The color display pixel array shown in FIG. 1 can be modified, for example, as in the modification shown in FIG. In this modification, two of the RGB sub-pixels PX constituting each color display pixel P are arranged between the first and second scanning lines which are two adjacent ones of the three corresponding scanning lines Y. The remaining one of the RGB sub-pixels PX is arranged between the second and third scanning lines that are adjacent two of the three corresponding scanning lines Y, as in the above-described embodiment. .

  In FIG. 7, a red (R) subpixel PX is provided in the first row, a green (G) subpixel PX is provided in both the first row and the second row, and a blue (B) subpixel PX. Is provided in the second row. In the second row, the arrangement of the blue (B) sub-pixels PX and the green (G) sub-pixels PX is opposite to the arrangement shown in FIG. One auxiliary capacitance line CL is omitted for each scanning line Y. Accordingly, it is possible to mitigate a decrease in the aperture ratio due to a margin for preventing a short circuit.

  DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display panel, 11 ... Array substrate, 22 ... Opposite substrate, 13 ... Liquid crystal layer, 20 ... Controller, CL ... Auxiliary capacity line, P ... Color display pixel, PE ... Pixel electrode, W ... Thin-film transistor, X ... Signal line , Y: scanning lines.

Claims (5)

A plurality of color display pixels each composed of three sub-pixels arranged in a delta arrangement and arranged in a matrix;
A plurality of switching elements provided at a ratio of three for each color display pixel;
A plurality of scanning lines provided at a ratio of three to the color display pixels in each row;
A plurality of signal lines provided at a ratio of one to the color display pixels of each column;
A plurality of auxiliary capacitance lines provided on the same plane as each scanning line at a ratio of two to the color display pixels in each row and capacitively coupled to the pixel electrodes of the corresponding subpixels,
Two of the three sub-pixels constituting each color display pixel are arranged between the first and second scanning lines which are two adjacent ones of the three corresponding scanning lines, and the three sub-pixels. The remaining one of them is arranged between the second and third scanning lines that are adjacent two of the three corresponding scanning lines, and the three sub-pixels are respectively connected via the three corresponding scanning lines. A liquid crystal display device connected to one corresponding signal line through three corresponding switching elements to be driven.   The three sub-pixels constituting each color display pixel are respectively assigned to red, green and blue, and each scanning line is connected to a corresponding switching element assigned to the sub-pixel of the same color. Item 2. A liquid crystal display device according to item 1.   2. The liquid crystal display device according to claim 1, wherein the three sub-pixels constituting each color display pixel have a longer shape in the direction in which the signal line extends than in the direction in which the scanning line extends.   2. The liquid crystal display device according to claim 1, wherein the color display pixels in each row are arranged so that the upper and lower sides of the delta arrangement are alternately reversed. A wiring method of a liquid crystal display device comprising a plurality of color display pixels each composed of three subpixels arranged in a delta arrangement and arranged in a matrix,
A plurality of switching elements are provided at a ratio of three for each color display pixel, and a plurality of scanning lines are provided at a ratio of three for the color display pixels in each row,
A plurality of signal lines are provided at a rate of one for each column of color display pixels,
A plurality of auxiliary capacitance lines that are capacitively coupled to the pixel electrodes of the corresponding sub-pixels are provided on the same plane as each scanning line at a ratio of two for the color display pixels in each row,
Two of the three sub-pixels constituting each color display pixel are arranged between the first and second scanning lines that are adjacent two of the three corresponding scanning lines,
The remaining one of the three sub-pixels is disposed between the second and third scanning lines that are adjacent two of the three corresponding scanning lines,
3. A pixel wiring method comprising connecting three sub-pixels to one corresponding signal line via three corresponding switching elements respectively driven via three corresponding scanning lines.

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