JP2010286334A - Semiconductor tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor tester which can perform a test on even an asynchronous DUT without changing the configuration of a timing signal generation system within the tester. <P>SOLUTION: The semiconductor tester for performing a test on a DUT which can switch transmission speed includes a timing signal frequency switching means for switching the frequency of a timing signal for performing a test in accordance with the switching of the transmission speed of the DUT. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus, and more particularly, to an improvement in a timing generator that generates a timing signal for detecting a DUT output signal while inputting a test signal to a DUT (device under test). It is.

  For example, in a semiconductor test apparatus for testing a semiconductor memory, a pattern output from the DUT by inputting a test pattern signal to the DUT is compared with an expected value pattern set in advance according to the test pattern signal. The quality of the DUT is determined based on the comparison result.

  FIG. 4 is a block diagram showing an example of a conventional semiconductor test apparatus. In FIG. 4, the pattern signal generated by the pattern generator 1 is input to the timing generator 2 and the comparator 3.

  In the timing generator 2, timing information based on the basic timing signal generated by the reference oscillator 4 is added to the pattern signal generated by the pattern generator 1 and input to the driver 5.

  The driver 5 converts the logic level data input from the timing generator 2 into a voltage level corresponding to the specification of the DUT 6 and inputs the voltage level to the DUT 6.

  The DUT 6 executes a predetermined internal processing operation based on the data input from the driver 5 and outputs a corresponding processing result as output data from the output pin.

  Data output from the DUT 6 is input to the comparator 7 and converted to a logic level, and input to the receiving unit 8 and sampled. At this time, timing data to be sampled by the receiving unit 8 is generated by the timing generating unit 2 and input to the receiving unit 8.

  Expected value pattern data that will be output by the DUT 6 is generated by the pattern generator 1 and input to the comparator 3. The comparison unit 3 compares the data sampled by the reception unit 8 with the expected value data input from the pattern generation unit 1 and determines the quality of the output data of the DUT 6.

  A series of these operations is executed by a control signal generated from the control unit 9 based on an internal program and output to each unit.

  Patent Document 1 describes a semiconductor test apparatus that can cope with high-speed DUT.

JP 2009-68949 A

  Incidentally, the DUT 6 in the apparatus of FIG. 4 mainly outputs a data clock and data synchronized with the data clock, and shapes the data by latching the data in synchronization with the data clock by an external circuit. The data is sampled by the receiving unit 8 on the premise that the timing of the reference signal of the reference oscillator 4 and the received data does not change greatly.

  However, the embedded clock system, which is a transmission system for high-speed serial devices represented by PCI Express, has a tolerance in data transfer frequency. For example, PCI Express allows 2.5 Gbps ± 300 ppm.

  This indicates that the received data is not synchronized with the reference oscillator 4. If the received data is sampled with the configuration of FIG. 4, the data cannot be received at some timing because of the asynchronous state, and an error occurs. .

  In order to avoid this, methods such as “SEMICONDUCTOR TEST DEVICE (WO03091742)” and “Transition tracking (US7248660)” have been proposed, but the circuit method is complicated and it is possible to follow the phase fluctuation of received data in real time. There are issues such as difficulties.

  Further, as an interface of a space-saving and low power consumption device, it is conceivable that the data transmission speed is variable on the same transmission path. When measuring such a DUT, it is necessary to switch the output frequency of the reference oscillator 4 at high speed according to the transmission speed, but it is difficult to realize such high-speed switching.

  The present invention solves these problems, and an object thereof is to provide a semiconductor test apparatus capable of testing an asynchronous DUT without changing the configuration of a timing signal generation system in the apparatus.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a semiconductor test apparatus for testing a DUT whose transmission speed can be switched,
Timing signal frequency switching means for switching a frequency of a timing signal for performing a test in response to switching of the transmission rate of the DUT;
Is provided.

According to a second aspect of the present invention, in the semiconductor test apparatus of the first aspect,
The timing signal frequency switching means is
A clock data separator for separating clock and data from the output data of the DUT;
A signal selection unit that selectively outputs either a basic timing signal generated by a reference oscillator and a clock separated by the clock data separation unit;
It is characterized by comprising.

According to a third aspect of the present invention, in the semiconductor test apparatus of the second aspect,
The clock data separation unit includes a phase locked loop.

According to a fourth aspect of the present invention, in the semiconductor test apparatus according to the first aspect,
The timing signal frequency switching means is
A frequency divider for dividing the basic timing signal generated by the reference oscillator;
A signal selector that selectively outputs either a basic timing signal generated by the reference oscillator or an output signal of the divider;
It is characterized by comprising.

  According to the present invention, it is possible to obtain a semiconductor test apparatus capable of testing a DUT capable of switching the transmission speed without directly switching the frequency of the basic timing signal generated by the reference oscillator.

It is a block diagram which shows one Example of this invention. It is a block diagram which shows the specific example of the clock data separation part 11 of FIG. It is a block diagram which shows the other Example of this invention. It is a block diagram which shows an example of the conventional semiconductor test apparatus.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals are given to portions common to FIG. The difference between FIG. 1 and FIG. 4 is that a signal selection unit 10 and a clock data separation unit 11 are added.

  In FIG. 1, a basic timing signal generated by the reference oscillator 4 is input to one input terminal of the signal selection unit 10, and an extraction clock generated separately by the clock data separation unit 11 is input to the other input terminal. A control signal is input to the control terminal from the control unit 9, and any one of these input signals is selected based on the control signal and input to the timing generation unit 2 as a clock.

  The output data of the DUT 6 is input to the clock data separation unit 11 and separated into a clock and data, the clock is input to one input terminal of the signal selection unit 10, and the data is input to the comparator 7.

  FIG. 2 is a block diagram illustrating a specific example of the clock data separation unit 11. In FIG. 2, the comparator 11a compares the output data of the DUT 6 with a reference level to convert it into a Hi / Lo digital signal, and inputs the converted digital signal to the frequency / phase comparator 11b and the latch 11c.

  In addition to the digital signal converted by the comparator 11a, the frequency / phase comparator 11b also receives an output signal of a reference oscillator 11d provided in the clock data separator 11 and an output signal of a VCO (voltage controlled oscillator) 11f. Have been entered.

  The frequency / phase comparison unit 11b compares the digital signal converted by the comparator 11a with the output signal of the VCO 11f to detect whether the frequency is within the range (coarse adjustment) and the phase difference (fine adjustment) between the two. The difference is smoothed by the filter 11e in the form of a pulse width signal, for example, and input to the VCO 11f. The filter 11e is a low-pass filter having a low passband frequency characteristic of, for example, several MHz to several tens of MHz, and the passband frequency characteristic is defined according to the DUT6 standard, for example.

  The VCO 11f oscillates at a frequency proportional to the input voltage value, and its output signal is fed back to the frequency / phase comparator 11b. These frequency / phase comparator 11b, filter 11e, and VCO 11f form a phase locked loop.

  As a result, the output signal of the VCO 11f changes following the frequency of the output signal of the comparator 11a and its transition. The output signal of the VCO 11f is input to the latch 11c as a clock for latching the output signal of the comparator 11a, and also input to one input terminal of the signal selection unit 10 so as to be selected as a clock for sampling. The

  The latch 11c latches the output signal of the comparator 11a using the output signal of the VCO 11f as a clock, and outputs the latched data to the subsequent comparator 7 as confirmed data.

  Note that the clock data separation unit 11 having such a configuration can mount an existing device inside and outside of the apparatus as needed, and the entire circuit can be built in the IC.

  In FIG. 1 again, the comparator 7 compares the data separated by the clock data separation unit 11 with a predetermined reference level, and transmits data having a certain level or higher as the logical level Hi or Lo to the reception unit 8.

  On the other hand, the extracted clock extracted by the clock data separator 11 is selected as a reference signal by the signal selector 10 and input to the timing generator 2. As a result, the timing generator 2 operates with the extracted clock synchronized with the output data of the DUT 6, the reception timing is almost the same as the output data of the DUT 6, and follows even if the phase of the output data of the DUT 6 fluctuates. become able to.

  The output signal of the comparator 7 is sampled by the reception unit 8 using the reception timing signal of the timing generation unit 2 and input to the comparison unit 3, and compared with the expected value data generated by the pattern generation unit 1. The quality of the output data is determined.

  A series of these operations is executed by a control signal generated from the control unit 9 based on an internal program and output to each unit.

  With this configuration, the asynchronous DUT can be tested without changing the configuration of the timing signal generation system inside the apparatus mainly for the source synchronous DUT.

  FIG. 3 is a block diagram showing another embodiment of the present invention, and the same reference numerals are given to portions common to FIG. In the apparatus of FIG. 3, a frequency divider 12 is provided between the reference oscillator 4 and the signal selection unit 10 instead of the clock data separation unit 11 of FIG.

  That is, the output terminal of the frequency divider 12 is connected to one input terminal of the signal selection unit 10, the output terminal of the reference oscillator 4 is connected to the other input terminal, and the output terminal of the signal selection unit 10 generates timing. Connected to the unit 2.

  When measuring the DUT 6 whose transmission rate can be switched, it is necessary to switch the output frequency of the reference oscillator 4. In general, it takes several hundred μs to several ms to switch the output frequency of the reference oscillator 4. . For this reason, overhead occurs in measurement. Further, there may be a case where the switching time of the output frequency of the reference oscillator 4 does not conform to the DUT 6 standard.

  FIG. 3 solves these problems. In FIG. 3, the reference oscillator 4 generates a high-speed signal and outputs it to the signal selection unit 10, and the frequency divider 12 divides the output signal of the reference oscillator 4 by, for example, 1 / n to generate a low-speed signal. Output to the selector 10. As the frequency divider 12, one having a function of performing synchronous switching based on a control signal is used.

  With the configuration as shown in FIG. 3, the frequency input from the signal selection unit 10 to the timing generation unit 2 can be switched in real time, and the above-described disadvantages such as overhead can be eliminated.

  In addition, although the example which uses what frequency-divides to 1 / n as the frequency divider 12 was demonstrated, irregular division ratios, such as n / m, may be sufficient if a synchronous relationship with an input is maintained.

  As described above, according to the present invention, it is possible to realize a semiconductor test apparatus that can also test an asynchronous DUT without changing the configuration of the timing signal generation system in the apparatus.

1 pattern generator 2 timing generator 3 comparator 4 reference oscillator 5 driver 6 DUT
7 Comparator 8 Reception Unit 9 Control Unit 10 Signal Selection Unit 11 Clock Data Separation Unit 11a Comparator 11b Frequency / Phase Comparison Unit 11c Latch 11d Reference Oscillator 11e Filter 11f VCO
12 divider

Claims (4)

In a semiconductor test apparatus for testing a DUT whose transmission speed can be switched,
Timing signal frequency switching means for switching a frequency of a timing signal for performing a test in accordance with switching of the transmission rate of the DUT;
A semiconductor test apparatus characterized by comprising: The timing signal frequency switching means is
A clock data separator for separating clock and data from the output data of the DUT;
A signal selection unit that selectively outputs either a basic timing signal generated by a reference oscillator and a clock separated by the clock data separation unit;
The semiconductor test apparatus according to claim 1, comprising:   3. The semiconductor test apparatus according to claim 2, wherein the clock data separator includes a phase locked loop. The timing signal frequency switching means is
A frequency divider for dividing the basic timing signal generated by the reference oscillator;
A signal selector that selectively outputs either a basic timing signal generated by the reference oscillator or an output signal of the divider;
The semiconductor test apparatus according to claim 1, comprising:

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