JP2010278654A - Solid-state imaging device, imaging apparatus, and imaging method - Google Patents

Abstract

A solid-state imaging device capable of expanding a dynamic range by a simple driving method is provided.
A solid-state imaging device 10 having a plurality of pixel units 100, wherein the pixel unit 100 includes a photoelectric conversion unit 3 and nonvolatile memory transistors MT1 and MT2 capable of storing charges generated in the photoelectric conversion unit 3. And storing the charge generated in the photoelectric conversion unit 3 during the first exposure period in the non-volatile memory transistor MT1, and starting after the end of the first exposure period. The controller 40 that accumulates charges generated in the photoelectric conversion unit 3 during the second exposure period, which has a length different from the exposure period, in the nonvolatile memory transistor MT2, and charges in the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2. After the accumulation, the first imaging signal corresponding to the charge accumulated in the nonvolatile memory transistor MT1 and the accumulation in the nonvolatile memory transistor MT2 And a read circuit 20 the read and a second image pickup signal corresponding to the charge.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device, an imaging apparatus, and an imaging method.

  In general, a solid-state image sensor has a narrow dynamic range as compared with a negative film. When the dynamic range is narrow, dark areas are blacked out and bright areas are overexposed. In particular, in recent years, there has been a problem that the noise level is not reduced as required even though the amount of saturation charge that can be handled by one pixel is reduced due to pixel miniaturization. In addition, the current dynamic range of a CMOS image sensor is not sufficient to disseminate solid-state imaging devices for in-vehicle applications and monitoring applications.

  Therefore, various methods for expanding the dynamic range have been proposed (see, for example, Patent Documents 1 and 2 and Non-Patent Document 1).

  As a particularly effective method, a method of combining two pieces of image data having different exposure times (shutter speeds) is known. For example, as described in Patent Document 1, a plurality of read-out image data are obtained by performing a read operation a plurality of times within a period of capturing an image for one screen with respect to photoelectric conversion units arranged in a two-dimensional manner. There is a method to expand the dynamic range by combining.

  However, in the above method, it is necessary to take the steps of first exposure → readout → second exposure → readout → composition. For this reason, there is a time difference between the first exposure and the second exposure, and when a moving subject is photographed, the composition processing becomes difficult. Further, since it is necessary to perform reading at high speed, power consumption increases.

JP 7-322147 A JP 2004-111817 A

Kazuya Yonemoto, Basics and Applications of CCD / CMOS Image Sensor, CQ Publishing Co., 2003, p212

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of expanding a dynamic range by simple driving, an imaging apparatus including the same, and an imaging method.

  The solid-state imaging device of the present invention is a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit, a first charge storage unit capable of storing charges generated in the photoelectric conversion unit, and a first charge storage unit. A charge storage unit, and after resetting the photoelectric conversion unit, charges generated in the photoelectric conversion unit during a first exposure period are stored in the first charge storage unit, Writing means for storing charges generated in the photoelectric conversion unit in the second charge storage unit during the second exposure period which is started after the end of the exposure period and having a length different from that of the first exposure period; and the writing A first imaging signal corresponding to the charge accumulated in the first charge accumulation unit and the second charge accumulation unit after the charge is accumulated in the first charge accumulation unit and the second charge accumulation unit by means; A second imaging signal corresponding to the charge stored in the charge storage unit And a signal read-out means that out look.

  The imaging device of the present invention includes the solid-state imaging device.

  The imaging method of the present invention is an imaging method using a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit and a first charge capable of accumulating charges generated in the photoelectric conversion unit. Having a storage part and a second charge storage part, and after resetting the photoelectric conversion part, the charge generated in the photoelectric conversion part during the first exposure period is stored in the first charge storage part, A writing step of accumulating charges generated in the photoelectric conversion unit in the second charge accumulation unit during the second exposure period which is started after the end of the first exposure period and has a length different from that of the first exposure period. And a first imaging signal corresponding to the charges accumulated in the first charge accumulation unit after accumulating charges in the first charge accumulation unit and the second charge accumulation unit by the writing unit, A second charge corresponding to the charge accumulated in the second charge accumulation section. And a signal readout step of reading out an imaging signal.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can expand a dynamic range by simple drive, an imaging device provided with this, and an imaging method can be provided.

1 is a schematic plan view showing a schematic configuration of a solid-state imaging device for explaining an embodiment of the present invention. 1 is an equivalent circuit diagram of a pixel portion of the solid-state imaging device shown in FIG. FIG. 2 is a schematic plan view showing a planar layout example of the pixel portion shown in FIG. A-A 'line cross-sectional schematic view of the pixel portion shown in FIG. B-B 'line cross-sectional schematic diagram of the pixel portion shown in FIG. The figure which shows schematic structure of the imaging device carrying the solid-state image sensor shown in FIG. Timing chart for explaining a method of driving the solid-state imaging device shown in FIG. Diagram for explaining the dynamic range expansion process 1 is an equivalent circuit diagram showing a first modification of the pixel portion of the solid-state imaging device shown in FIG. The equivalent circuit diagram which shows the 2nd modification of the pixel part of the solid-state image sensor shown in FIG. The figure which showed the example of a plane layout of the equivalent circuit diagram shown in FIG. The equivalent circuit diagram which shows the 3rd modification of the pixel part of the solid-state image sensor shown in FIG.

  Hereinafter, a solid-state imaging device for describing an embodiment of the present invention will be described with reference to the drawings. This solid-state imaging device is used by being mounted on an imaging unit built in an imaging device such as a digital camera or a digital video camera, a mobile phone, an electronic endoscope, or the like.

  FIG. 1 is a schematic plan view showing a schematic configuration of a solid-state imaging device for explaining an embodiment of the present invention. FIG. 1A is a diagram illustrating the entire solid-state imaging device, and FIG. 1B is a diagram illustrating a configuration example of a readout circuit of the solid-state imaging device in FIG. 1 includes a pixel unit 100, a readout circuit 20, an output circuit (a transistor 30, a signal line 70, a horizontal shift register 50, an output unit 60), a control unit 40, and an overall control unit 80. With.

  A plurality of the pixel portions 100 are provided, and are arranged in a two-dimensional shape (in this example, a square lattice shape) in the column direction of the semiconductor substrate K and the row direction orthogonal thereto.

  The readout circuit 20 is provided for each pixel unit column including the pixel units 100 arranged in the column direction, and is used for reading out an imaging signal from each pixel unit 100.

  The output circuit is a circuit for outputting an imaging signal for one pixel unit row read by the readout circuit 20.

  The control unit 40 controls each pixel unit 100.

  The overall control unit 80 performs overall control of the entire solid-state imaging device 10. The solid-state imaging device 10 operates by the overall control unit 80 controlling each unit under the control of the system control unit of the imaging apparatus on which the solid-state imaging device 10 is mounted.

  FIG. 2 is a diagram showing an equivalent circuit of the pixel portion in the solid-state imaging device shown in FIG. As shown in FIG. 2, the pixel unit 100 includes a photoelectric conversion unit 3, a nonvolatile memory transistor MT1, a nonvolatile memory transistor MT2, and a reset transistor RT.

  The photoelectric conversion unit 3 is formed in the semiconductor substrate K. The nonvolatile memory transistor MT1 has a MOS transistor structure including a floating gate FG1 which is a charge storage region formed above the semiconductor substrate K and a control gate CG1 which is a gate electrode. The nonvolatile memory transistor MT2 has a MOS transistor structure including a floating gate FG2 which is a charge storage region formed above the semiconductor substrate K and a control gate CG2 which is a gate electrode. The reset transistor RT is for resetting the electric charge of the photoelectric conversion unit 3. Each of the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2 functions as a charge accumulation unit capable of accumulating charges generated in the photoelectric conversion unit 3.

  The outputs (drain regions D1, D2) of the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2 are commonly connected to a column signal line 12 which is an output signal line provided for each pixel unit column. A readout circuit 20 is connected to the signal line 12. The source regions S of the nonvolatile memory transistors MT1 and MT2 are commonly connected to a source line SL provided for each pixel unit column.

  The reset transistor RT has a MOS structure including a reset drain RD, a photoelectric conversion unit 3 that functions as a source region, and a reset gate RG that is a gate electrode. A reset power supply line Vcc for supplying a reset voltage is connected to the reset drain RD.

  The control gate CG1 of the nonvolatile memory transistor MT1 is connected to a gate control line CGL1 provided for each line including the pixel units 100 arranged in the row direction. The gate control line CGL1 of each line is connected to the control unit 40, and a voltage can be applied independently for each line.

  A gate control line CGL2 provided for each line is connected to the control gate CG2 of the nonvolatile memory transistor MT2. The gate control line CGL2 of each line is connected to the control unit 40 so that a voltage can be applied independently for each line.

  A reset control line RL provided for each line is connected to the reset gate RG of the reset transistor RT. The reset control line RL of each line is connected to the control unit 40 so that a voltage can be applied independently for each line. A configuration in which a reset pulse is applied from the control unit 40 via a reset control line RL, whereby the reset transistor RT is turned on, and the charge accumulated in the photoelectric conversion unit 3 is discharged to the drain RD of the reset transistor RT It has become.

  As shown in FIG. 1B, the read circuit 20 includes a read control unit 20a, a sense amplifier 20b, a precharge circuit 20c, a ramp-up circuit 20d, and transistors 20e and 20f. Yes.

  The read control unit 20a controls on / off of the transistors 20e and 20f. The precharge circuit 20 c is a circuit for supplying a predetermined voltage to the column signal line 12 to precharge the column signal line 12. The sense amplifier 20b monitors the voltage of the column signal line 12, detects that this voltage has changed, and notifies the ramp-up circuit 20d accordingly. For example, it detects that the drain voltage precharged by the precharge circuit 20c has dropped, and inverts the sense amplifier output.

  The ramp-up circuit 20d includes an N-bit counter (for example, N = 8 to 12), and supplies a ramp waveform voltage that gradually increases or decreases to the control gates CG1 and CG2 of the pixel unit 100 via the control unit 40. At the same time, a count value (a combination of N 1, 0) corresponding to the value of the ramp waveform voltage is output.

  When the voltage of the control gate CG1 exceeds the threshold voltage of the nonvolatile memory transistor MT1 in a state where the column signal line 12 is precharged, the nonvolatile memory transistor MT1 becomes conductive, and at this time, the column signal line 12 of the precharged column signal line 12 is turned on. The potential drops. This is detected by the sense amplifier 20b and an inverted signal is output. The ramp-up circuit 20d holds (latches) a count value corresponding to the value of the ramp waveform voltage at the time when the inverted signal is received. As a result, the amount of change in the threshold voltage of the nonvolatile memory transistor MT1 (the amount of change based on the threshold voltage when no charge is accumulated in the floating gate FG1) is read as a signal as a digital value (combination of 1 and 0). be able to.

  When the voltage of the control gate CG2 exceeds the threshold voltage of the nonvolatile memory transistor MT2 in a state where the column signal line 12 is precharged, the nonvolatile memory transistor MT2 becomes conductive, and at this time, the column signal line 12 of the precharged column signal line 12 is turned on. The potential drops. This is detected by the sense amplifier 20b and an inverted signal is output. The ramp-up circuit 20d holds a count value corresponding to the value of the ramp waveform voltage when the inverted signal is received. Thereby, the change amount of the threshold voltage of the nonvolatile memory transistor MT2 (change amount based on the threshold voltage when no charge is accumulated in the floating gate FG2) can be read as a signal as a digital value.

  When one horizontal selection transistor 30 is selected by the horizontal shift register 50, the counter value held in the ramp-up circuit 20d connected to the horizontal selection transistor 30 is output to the signal line 70, and this is output as an imaging signal. Output from the unit 60.

  Note that the method of reading out the change amount of the threshold voltage of the nonvolatile memory transistors MT1 and MT2 as a signal is not limited to the above. For example, the drain current of the nonvolatile memory transistor MT1 when a constant voltage is applied to the control gate CG1 and the drain region D1, and the nonvolatile memory transistor MT2 when a constant voltage is applied to the control gate CG2 and the drain region D2. The drain current may be read out as a signal.

  The control unit 40 controls the non-volatile memory transistors MT1 and MT2, and performs driving for injecting and accumulating charges generated in the photoelectric conversion unit 3 into the floating gates FG1 and FG2. In the nonvolatile memory transistor MT1 (MT2), when a write pulse is applied to the control gate CG1 (CG2), FN tunnel injection and direct tunnel injection in which charges are injected using a Fowler-Nordheim (FN) tunnel current. For example, charges generated in the photoelectric conversion unit 3 are injected into the floating gate FG1 (FG2) and accumulated.

  Further, the control unit 40 resets the electric charge generated and accumulated in the photoelectric conversion unit 3 of each pixel unit 100 to the outside to make the photoelectric conversion unit 3 in an empty state, and the floating gates FG1 and FG2 Charge erasure driving is also performed in which the accumulated charges are discharged to the semiconductor substrate and erased.

  FIG. 3 is a schematic plan view showing a planar layout example of the pixel portion of the solid-state imaging device shown in FIG. 4 is a schematic cross-sectional view taken along line A-A ′ of the pixel portion shown in FIG. 3. FIG. 5 is a schematic cross-sectional view taken along line B-B ′ of the pixel portion shown in FIG. 3.

  As shown in FIG. 4, the photoelectric conversion unit 3 is an N-type impurity region formed in the P-well layer 2 on the N-type silicon substrate 1, and a PN junction between the N-type impurity region and the P-well layer 2. Thus, the photoelectric conversion function is realized. The photoelectric conversion unit 3 is a so-called embedded photodiode in which a P-type impurity layer 5 is formed on the surface for complete depletion and dark current suppression. The N-type silicon substrate 1 and the P well layer 2 constitute the semiconductor substrate K.

  Adjacent pixel portions 100 are separated from each other by an element isolation layer 4 formed in the p well layer 2. As the element isolation method, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a method using high-concentration impurity ion implantation, and the like can be applied.

  The source region S of the nonvolatile memory transistor MT1 is an N-type impurity region that is provided adjacent to the photoelectric conversion unit 3 in the column direction. In addition, the drain region D1 of the nonvolatile memory transistor MT1 is an N-type impurity region that is provided adjacent to the source region S in the row direction. A channel region 6a, which is a P-type impurity region, is formed between the source region S and the drain region D1. The floating gate FG1 is provided above the semiconductor substrate between the source region S and the drain region D1 via the insulating film 7, and the control gate CG1 is provided above the floating gate FG1 via the insulating film 14. Yes. The channel region 6a is a region where carriers flow according to the voltage applied to the control gate CG1. Here, a P-type impurity is implanted into a region sandwiched between the source region S and the drain region D1 to form the channel region 6a. However, the channel region 6a may be left as it is.

  The drain region D2 of the nonvolatile memory transistor MT2 is an N-type impurity region that is provided adjacent to the source region S in the row direction. A channel region 6b which is a P-type impurity region is formed between the source region S and the drain region D2. The floating gate FG2 is provided above the semiconductor substrate between the source region S and the drain region D2 via the insulating film 7, and the control gate CG2 is provided above the floating gate FG2 via the insulating film 14. Yes. The channel region 6b is a region where carriers flow according to the voltage applied to the control gate CG2. Here, for the purpose of controlling the charge injection efficiency and the threshold voltage (Vth) in the region sandwiched between the source region S and the drain region D2, for example, a P-type impurity is implanted to form the channel region 6b. This may be left as the p-well layer 2.

  For example, polysilicon can be used as the conductive material forming the control gates CG1 and CG2. A doped polysilicon that is highly doped with phosphorus (P), arsenic (As), and boron (B) may be used. Alternatively, silicide (Silicide) or salicide (Self-alingn Silicide) in which various metals such as titanium (Ti) and tungsten (W) are combined with silicon may be used. The same conductive material as that of the control gates CG1 and CG2 can be used as the conductive material constituting the floating gates FG1 and FG2.

  In the layout example of FIG. 3, the source region S and the drain regions D1, D2 are arranged side by side in the row direction, and the gap between them is elongated so that the floating gates FG1, FG2 and the control gates CG1, CG2 extend in the column direction. Is formed. The control gate CG1 extends below the gate control line CGL1, which is an aluminum wiring extending in the row direction. Here, the control gate CG1 is connected to the gate control line CGL1 by a contact portion 11 formed of aluminum or the like.

  The control gate CG2 extends below the gate control line CGL2, which is an aluminum wiring extending in the row direction. Here, the control gate CG2 is connected to the gate control line CGL2 by a contact portion 16 formed of aluminum or the like.

  Above the drain regions D1 and D2, a part of the column signal line 12 which is an aluminum wiring extending in the column direction extends, and this part and the drain region D1 are electrically connected by a contact portion 9 formed of aluminum or the like. A part of the drain region D2 and the drain region D2 are electrically connected by a contact portion 10a formed of aluminum or the like.

  A contact portion 8a made of aluminum or the like is formed on the source region S, and a wiring 8 is connected to the contact portion 8a. The wiring 8 passes under the reset power supply line Vcc, which is an aluminum wiring extending in the column direction, and extends below the source line SL. The wiring 8 and the source line SL are electrically connected by a contact portion 8b made of aluminum or the like. The source line SL is provided for each column including the pixel portions 100 arranged in the column direction, and is connected to a predetermined potential (for example, ground potential).

  The reset transistor RT includes a photoelectric conversion unit 3 that functions as a source region, a drain region RD that is an N-type impurity region that is provided adjacent to the photoelectric conversion unit 3 in the column direction, a photoelectric conversion unit 3 and a drain region RD. And a reset gate RG provided via an insulating film 7 above the semiconductor substrate.

  In the layout example of FIG. 3, the reset gate RG is arranged below the reset control line RL that is an aluminum wiring extending in the row direction. Here, the reset control line RL and the reset control line RL are formed by a contact portion RGa formed of aluminum or the like. It is connected.

  A part of the reset power supply line Vcc extends above the drain region RD, and this part and the drain region RD are electrically connected by a contact portion RDa formed of aluminum or the like. The reset power supply line Vcc is provided for each column including the pixel units 100 arranged in the column direction, and is connected to a predetermined power supply voltage.

  The arrangement of the reset transistor RT and the nonvolatile memory transistors MT1 and MT2 is not limited to that shown in FIG. 3, and may be appropriately arranged according to the space.

  The positional relationship between the various wirings is that the source line SL, the reset power supply line Vcc, and the column signal line 12 are formed in an upper layer than the gate control lines CGL1, CGL2, the reset control line RL, and the wiring 8. ing.

  The pixel unit 100 has a structure in which light does not enter a region other than a part of the photoelectric conversion unit 3 by a light shielding film W made of, for example, tungsten. As shown in FIGS. 4 and 5, an opening WH is formed above a part of the photoelectric conversion unit 3 above the semiconductor substrate (above the source line SL, the reset power supply line Vcc, and the column signal line 12). A light shielding film W is formed.

  In the solid-state imaging device 10, for the purpose of improving the efficiency of charge injection into the floating gates FG1 and FG2, as shown in FIGS. 4 and 5, the photoelectric conversion unit 3 is not only below the opening WH of the light shielding film W, The nonvolatile memory transistors MT1 and MT2 extend below the channel regions 6a and 6b.

  As shown in FIGS. 4 and 5, the photoelectric conversion unit 3 includes a main body 3a formed below the opening WH and an extending portion 3b extending from the main body 3a to below the channel region 6a (6b). In FIG. 4, a boundary line (broken line) is shown on the main body 3a and the extension 3b. However, this is for explanation, and such a boundary does not actually exist.

  The main body 3a is a portion formed below the opening WH in order to receive light. The extending portion 3b is a portion extending from the main body portion 3a to the bottom of the channel regions 6a and 6b of the nonvolatile memory transistors MT1 and MT2 inside the p well layer 2. The extension 3b is formed to extend in the column direction from the position facing the region between the source region S and the drain regions D1 and D2 of the main body 3a in plan view. That is, in the plan view, in the region where the nonvolatile memory transistors MT1 and MT2 and the reset transistor RT are formed, the photoelectric conversion unit 3 exists only under the channel regions 6a and 6b of the nonvolatile memory transistors MT1 and MT2. The photoelectric conversion unit 3 is formed. Note that the extending portion 3b may be formed so that the photoelectric conversion portion 3 exists not only under the channel regions 6a and 6b but also under the entire nonvolatile memory transistors MT1 and MT2.

  The channel region 6a (6b) is immediately below the control gate CG1 (CG2) and the floating gate FG1 (FG2). For this reason, by extending the photoelectric conversion unit 3 under the channel region 6a (6b) (preferably the entire range overlapping the channel region 6a (6b) in plan view), the charge of the photoelectric conversion unit 3 is reduced to FN. When injecting into the floating gate FG1 (FG2) by tunnel injection or direct tunnel injection, the voltage (CG voltage) applied to the control gate CG1 (CG2) causes the photoelectric conversion unit 3 to move to the floating gate FG1 (FG2) in a substantially vertical direction. An electric field can be applied. Thereby, the electric charge of the photoelectric conversion unit 3 is easily accelerated toward the control gate CG1 (CG2). As a result, tunneling can be caused with a low CG voltage.

  In the solid-state imaging device 10, since the photoelectric conversion unit 3 extends under the channel region 6a (6b) while securing the channel region 6a (6b), the photoelectric conversion unit 3 and the control gate CG1 (CG2). There is no restriction on the size of the overlapping portion, and the electric field direction can be made almost vertical. As a result, a tunnel current can be generated efficiently.

  The photoelectric conversion unit 3 can control the length in the direction parallel to the substrate surface by controlling the mask pattern during ion implantation, and can control the length in the direction perpendicular to the substrate surface by controlling ion implantation energy. it can. By doing in this way, it is possible to form the photoelectric conversion part 3 which consists of the main-body part 3a and the extension part 3b.

  Next, an example of an imaging device on which the solid-state imaging element 10 is mounted will be described.

FIG. 6 is a diagram illustrating a schematic configuration of an imaging apparatus in which the solid-state imaging device illustrated in FIG. 1 is mounted.
The imaging system of the illustrated imaging apparatus includes a photographic lens 41, a solid-state imaging device 10, a diaphragm 42 provided between them, an infrared cut filter 43, and an optical low-pass filter 44.

  A system control unit 51 that performs overall control of the entire electric control system of the imaging apparatus controls a flash light emitting unit 52 and a light receiving unit 53 that emit light for illuminating a subject, and controls a lens driving unit 48. Then, the position of the photographic lens 41 is adjusted to the focus position or zoom adjustment is performed, and the exposure amount is adjusted by controlling the aperture amount of the aperture 42 via the aperture drive unit 49. The flash light emitting unit 52 is configured by a xenon lamp or the like.

  In addition, the system control unit 51 drives the solid-state imaging device 10 to output a subject image captured through the photographing lens 41 as an imaging signal. An instruction signal from a user is input to the system control unit 51 through the operation unit 54.

  The electric control system of the imaging apparatus performs image data by performing main memory 56, memory control unit 55 connected to main memory 56, dynamic range expansion processing, interpolation calculation, gamma correction calculation, RGB / YC conversion processing, and the like. A digital signal processing unit 57 to be generated, a compression / decompression processing unit 58 that compresses the image data generated by the digital signal processing unit 57 into a JPEG format or decompresses the compressed image data, and digital signal processing by integrating the photometric data Display control to which an integration unit 59 for obtaining a gain for white balance correction performed by the unit 57, an external memory control unit 60 to which a detachable recording medium 61 is connected, and a liquid crystal display unit 63 mounted on the back of the camera or the like are connected. Are connected to each other by a control bus 64 and a data bus 65, and in response to a command from the system control unit 51. It is controlled me.

  Next, an imaging operation by the imaging apparatus configured as described above will be described.

  FIG. 7 is a timing chart for explaining a method of driving the solid-state imaging device shown in FIG. In FIG. 7, the voltage change supplied to each part in the pixel part 100 of an arbitrary line is shown with time.

  When an imaging instruction is given by the system control unit 51, in the solid-state imaging device 10, the control unit 40 supplies a reset pulse to the reset gates RG of the reset transistors RT of all the pixel units 100 using the imaging instruction as a start trigger. At the same time, a voltage having a polarity opposite to that of the reset pulse is supplied to the control gates CG1 and CG2 of all the pixel units 100. Thereby, unnecessary charges accumulated in the photoelectric conversion unit 3 are discharged to the drain RD of the reset transistor RT, and charges accumulated in the floating gates FG1 and FG2 are also transferred to the drain RD via the photoelectric conversion unit 3. As a result, the floating gates FG1, FG2 become empty. When the application of the reset pulse is completed, a first exposure period (also referred to as a short exposure period) for exposing the photoelectric conversion unit 3 for a time t1 is started, and according to light incident on the photoelectric conversion unit 3 during this period. Charge is accumulated in the photoelectric conversion unit 3.

  Immediately before the end of the first exposure period, the control unit 40 supplies a write voltage (for example, 7 V) to the control gates CG1 of all the pixel units 100, and the photoelectric conversion unit from the start of the first exposure period to the present time. 3 is injected into the floating gate FG1. Even during the application of the write voltage, light is incident on the photoelectric conversion unit 3, so that charges generated in the photoelectric conversion unit 3 in response to the light are also injected into the floating gate FG 1. The charge accumulated in the photoelectric conversion unit 3 moves from the main body 3a to the extension 3b, and is injected from the extension 3b into the floating gate FG1 through the channel region 6a.

  When the application of the write voltage to the control gate CG1 ends, the first exposure period ends. Along with the end of the first exposure period, a second exposure period (also referred to as a long exposure period) for exposing the photoelectric conversion unit 3 for a time t2 longer than the time t1 is started, and during this period, the photoelectric conversion unit Charges corresponding to the light incident on 3 are accumulated in the photoelectric conversion unit 3.

  Immediately before the end of the second exposure period, the control unit 40 supplies a write voltage (for example, 7 V) to the control gates CG2 of all the pixel units 100, and the photoelectric conversion unit from the start of the second exposure period to the present time. 3 is injected into the floating gate FG2. Even during the application of the write voltage, the light is incident on the photoelectric conversion unit 3, so that charges generated in the photoelectric conversion unit 3 in response to the light are also injected into the floating gate FG 2. The electric charge accumulated in the photoelectric conversion unit 3 moves from the main body 3a to the extension 3b, and is injected from the extension 3b into the floating gate FG2 through the channel region 6b. Then, when the application of the write voltage to the control gate CG2 is finished, the second exposure period is finished.

  When the second exposure period ends, the read control unit 20a turns on the transistor 20f to precharge the column signal line 12. Next, the read control unit 20a turns on the transistor 20e to conduct the column signal line 12 and the sense amplifier 20b. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth readout voltage) to the control gate CG1 of each pixel unit 100 in the first line via the control unit 40.

  When the drain potential of the nonvolatile memory transistor MT1 of each pixel unit 100 in the first line drops after the ramp waveform voltage is applied, a count value corresponding to the value of the ramp waveform voltage at that time is held in each readout circuit 20. Is done. The held count value is a signal line under the control of the horizontal shift register 50 as an imaging signal (hereinafter referred to as a short exposure imaging signal) corresponding to the electric charge generated and accumulated in the photoelectric conversion unit 3 during the first exposure period. Is output from the output unit 60 via 70. After the short exposure imaging signal is output, the transistor 20f is turned off, the application of the ramp waveform voltage is stopped, and the count value is reset.

  Next, the read control unit 20a turns on the transistor 20f to precharge the column signal line 12. Next, the read control unit 20a turns on the transistor 20e to conduct the column signal line 12 and the sense amplifier 20b. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth read voltage) to the control gate CG2 of each pixel unit 100 in the first line via the control unit 40.

  When the drain potential of the nonvolatile memory transistor MT2 of each pixel unit 100 on the first line drops after the ramp waveform voltage is applied, a count value corresponding to the value of the ramp waveform voltage at that time is held in each readout circuit 20. Is done. The held count value is a signal line under the control of the horizontal shift register 50 as an imaging signal (hereinafter referred to as a long exposure imaging signal) corresponding to the electric charge generated and accumulated in the photoelectric conversion unit 3 during the second exposure period. Is output from the output unit 60 via 70. After outputting the long exposure imaging signal, the transistor 20f is turned off, the application of the ramp waveform voltage is stopped, and the count value is reset.

  Similarly, for each pixel unit 100 in the second and subsequent lines, the precharge of the column signal line 12, the application of the ramp waveform voltage to the control gate CG1, and the count corresponding to the value of the ramp waveform voltage when the drain voltage drops. Holding a value, outputting the count value, precharging the column signal line 12, applying a ramp waveform voltage to the control gate CG2, holding a count value corresponding to the value of the ramp waveform voltage when the drain voltage drops, A series of operations for outputting the count value is performed, and the short exposure imaging signal and the long exposure imaging signal are read from all the pixel units 100. The short exposure image signal and the long exposure image signal output from the solid-state image sensor 10 are temporarily stored in the main memory 56.

  After the short-exposure imaging signal and the long-exposure imaging signal are read from all the pixel units 100, the digital signal processing unit 57 is temporarily stored in the main memory 56 and obtained from the same photoelectric conversion unit 3. A process for expanding the dynamic range by combining the signal and the long exposure imaging signal is performed.

  FIG. 8 is a diagram for explaining an example of the dynamic range expansion process. As shown in FIG. 8A, the optical signal intensity-output signal characteristic curve of the short-exposure imaging signal obtained by the first exposure period is as shown by symbol D, and is obtained by the second exposure period. The characteristic curve of the optical signal intensity-output signal of the long-exposure imaging signal is as indicated by the symbol C.

  In the digital signal processing unit 57, first, threshold processing is performed on the long exposure imaging signal. The threshold processing is processing for setting a portion of the long exposure imaging signal whose level is a predetermined value or more to a constant value. For example, as shown in FIG. 8B, all the long exposure imaging signals of level L or higher are processed so as to become level L.

  Next, the digital signal processing unit 57 performs level adjustment so that the level of the short exposure imaging signal corresponding to the optical signal intensity corresponding to the level L becomes the level L. The characteristic curve C of the long-exposure imaging signal in the region where the optical signal intensity is smaller than the optical signal intensity corresponding to the level L and the level adjustment in the region where the optical signal intensity is larger than the optical signal intensity corresponding to the level L Are combined with the characteristic curve D of the short-exposure imaging signal to obtain a combined curve. As a result, the dynamic range can be expanded.

  As described above, according to the solid-state imaging device 10, in imaging for obtaining one image, two imaging signals having different exposure periods can be obtained. Therefore, the dynamic range can be expanded by combining these signals. Can do. In addition, since the first exposure period and the second exposure period are continuously performed without a gap, the dynamic range expansion process can be easily performed even for a moving subject. Further, since it is not necessary to read out the short exposure imaging signal and the long exposure imaging signal at high speed, the power consumption can be suppressed low.

  Further, according to the solid-state imaging device 10, since the photoelectric conversion unit 3 exists under the channel region 6a of the nonvolatile memory transistor MT1 and the channel region 6b of the nonvolatile memory transistor MT2, it enters from the light shielding film opening WH. The charges generated in the photoelectric conversion unit 3 in response to the received light are efficiently injected from the overlapping portions of the photoelectric conversion unit 3 with the channel regions 6a and 6b into the floating gates FG1 and FG2 through the channel regions 6a and 6b. Therefore, the sensitivity can be improved.

  Note that the control unit 40 stores the storage destination of the charge generated in the photoelectric conversion unit 3 during the first exposure period and the charge generated in the photoelectric conversion unit 3 during the second exposure period, as a nonvolatile memory transistor. It is preferable to alternately switch between MT1 and nonvolatile memory transistor MT2 at regular intervals. That is, charges generated in the photoelectric conversion unit 3 during the first exposure period are accumulated in the nonvolatile memory transistor MT1, and charges generated in the photoelectric conversion unit 3 during the second exposure period are accumulated in the nonvolatile memory transistor MT2. Charge generated in the photoelectric conversion unit 3 during the first exposure period is accumulated in the non-volatile memory transistor MT2, and the charge generated in the photoelectric conversion unit during the second exposure period is stored in the first control. It is preferable to provide a second control for accumulating in the electric charge accumulating unit, and to alternately switch these at regular intervals. For example, it is only necessary to switch between the first control and the second control every frame or every 10 times. Thereby, the lifetime improvement of an element can be anticipated.

  In the above description, the signal is read from the floating gate FG1 first, but this order may be any. Moreover, although the time t1 of the first exposure period is made smaller than the time t2 of the second exposure period, t1> t2 may be satisfied.

  The solid-state imaging device 10 is designed so that the channel length and the channel width of the nonvolatile memory transistor MT1 are the same as the channel length and the channel width of the nonvolatile memory transistor MT2 in order to perform the dynamic range expansion process with high accuracy. It is preferable to keep it.

  In the imaging apparatus shown in FIG. 6, when the subject is dark, the light emitting unit 52 can illuminate the subject and take an image. When imaging is performed by causing the light emitting unit 52 to emit light, it is preferable that t1> t2 and light is emitted from the light emitting unit 52 during the second exposure period in order to perform favorable imaging. That is, it is preferable that the exposure period with a long exposure time is performed first, and light is emitted during the exposure period with a short exposure time. Specifically, when the setting for emitting light from the light emitting unit 52 is performed automatically or manually, the system control unit 51 performs the first exposure period and the second exposure period so that t1> t2. Thus, the solid-state imaging device 10 may be controlled so that light is emitted from the light emitting unit 52 during the second exposure period.

  For example, when shooting a person and the background at night, the first exposure period is mainly aimed at shooting the background, but the strobe is not fired, but the next exposure period is aimed at shooting the person in front. By flashing the strobe light, a person can be photographed, and even when the person moves, the exposure time is short in the second exposure period, so that the influence (blur) due to the movement can be minimized.

  In the above description, the dynamic range expansion process is performed outside the solid-state image sensor 10. However, this may be performed within the solid-state image sensor 10.

  In the above description, the MOS transistors having the floating gates FG1 and FG2 are taken as examples of the nonvolatile memory transistors MT1 and MT2. However, the nonvolatile memory transistors MT1 and MT2 can adopt a structure other than the MOS structure. . For example, there are a MNOS type transistor structure in which the floating gates FG1 and FG2 are nitride films and the control gates CG1 and CG2 are formed directly on the nitride film, and a MONOS type transistor structure in which the floating gates FG1 and FG2 are nitride films. May be. In either case, the nitride film functions as a charge storage region for storing charges.

  In the above description, it is assumed that the handling charge (charge taken out as a signal) is an electron, but the idea is the same even when the handling charge is a hole. In the case where the charge handled is a hole, the N-type region and the P-type region are exchanged in the drawing, and the polarity of the voltage applied to each part is reversed.

  Hereinafter, modifications of the solid-state imaging device 10 illustrated in FIG. 1 will be described.

(First modification)
FIG. 9 is an equivalent circuit diagram showing a first modification of the pixel portion of the solid-state imaging device shown in FIG. In FIG. 9, the same components as those in FIG. The difference between the pixel portion shown in FIG. 9 and the pixel portion shown in FIG. 2 is that two readout circuits 20 are provided for each column of pixel portions arranged in the column direction. Separate column signal lines 12a and 12b are connected to the output (drain region D1) of the nonvolatile memory transistor MT1 and the output (drain region D2) of the nonvolatile memory transistor MT2, respectively. The readout circuit 20 is connected to each.

  In the solid-state imaging device shown in FIG. 9, a threshold processing unit 21 and a synthesis processing unit 22 are further provided for each column. The threshold processing unit 21 performs the above-described threshold processing on the long exposure imaging signal read by the reading circuit 20 connected to the column signal line 12b, and outputs the processed signal. The combination processing unit 22 combines the long-exposure imaging signal after the threshold processing and the short-exposure imaging signal read by the reading circuit 20 connected to the column signal line 12a to perform a process of expanding the dynamic range. The signal processed by the synthesis processing unit 22 is output from the output circuit including the horizontal shift register 50 to the outside of the solid-state imaging device.

  An imaging operation of the solid-state imaging device configured as described above will be described. The operation until the charges generated in the first exposure period are accumulated in the floating gate FG1 and the charges generated in the second exposure period are accumulated in the floating gate FG2 is the same as described in FIG.

  After the first exposure period and the second exposure period, the short exposure imaging signal is read by the reading circuit 20 connected to the column signal line 12a. First, the read control unit 20a turns on the transistor 20f to precharge the column signal line 12a. Next, the read control unit 20a turns on the transistor 20e to make the column signal line 12a and the sense amplifier 20b conductive. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth readout voltage) to the control gate CG1 of each pixel unit 100 in the first line via the control unit 40. A count value corresponding to the value of the ramp waveform voltage at the time when the drain potential of the nonvolatile memory transistor MT1 of each pixel unit 100 in the first line drops is held in each readout circuit 20. After holding the short exposure imaging signal, the application of the ramp waveform voltage is stopped and the transistor 20f is turned off. The held short exposure imaging signal is input to the composition processing unit 22.

  Next, the long exposure imaging signal is read out by the readout circuit 20 connected to the column signal line 12b. First, the read control unit 20a turns on the transistor 20f to precharge the column signal line 12b. Next, the read control unit 20a turns on the transistor 20e to make the column signal line 12b and the sense amplifier 20b conductive. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth read voltage) to the control gate CG2 of each pixel unit 100 in the first line via the control unit 40. A count value corresponding to the value of the ramp waveform voltage at the time when the drain potential of the nonvolatile memory transistor MT2 of each pixel unit 100 in the first line drops is held in each readout circuit 20. After holding the long exposure imaging signal, the application of the ramp waveform voltage is stopped and the transistor 20f is turned off. The held long exposure image signal is subjected to threshold processing, and is then combined with the short exposure image signal and output to the outside of the solid-state image sensor. After the composite signal is output, the counter is reset.

  The same driving is performed for the pixel units 100 in the second and subsequent lines, and an imaging signal that has been subjected to dynamic range expansion processing is output from all lines.

  As described above, even with the configuration shown in FIG. 9 (configuration in which the dynamic range expansion processing is performed inside the solid-state imaging device), power consumption can be suppressed and high image quality can be achieved without performing complex driving. Can do. The configuration shown in FIG. 2 is a configuration in which the read circuit 20 is shared by the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2, and thus has an advantage that the circuit scale can be reduced compared to the configuration shown in FIG.

(Second modification)
FIG. 10 is an equivalent circuit diagram showing a second modification of the pixel portion of the solid-state imaging device shown in FIG. In this modification, the nonvolatile memory transistor MT1 shown in FIG. 2 is replaced with a write transistor WT1 for writing charges into the floating gate FG1 and a threshold value of the nonvolatile memory transistor MT1 according to the charges accumulated in the floating gate FG1. The read transistor RT1 for detecting the voltage is composed of two transistors, and each has a configuration as described in Patent Document 1 in which the floating gate FG1 is shared. Similarly, the nonvolatile memory transistor MT2 includes a write transistor WT2 and a read transistor RT2, and has a structure in which the floating gate FG2 is shared by the transistors.

  In FIG. 10, the photoelectric conversion unit 3 and the source regions of the write transistors WT1 and WT2 are connected. Further, the drain regions of the read transistors RT1 and RT2 are commonly connected to the column signal line 12, and the read circuit 20 shown in FIG. 1B is connected to the column signal line 12. The gate electrode (write control gate) of the write transistor WT1 is indicated by WCG1, the gate electrode (write control gate) of the write transistor WT2 is indicated by WCG2, the gate electrode (read control gate) of the read transistor RT1 is indicated by RCG1, and the read transistor The gate electrode (read control gate) of RT1 is indicated by RCG2. A wiring wcg1 is connected to the write control gate WCG1, a wiring wcg2 is connected to the write control gate WCG2, a wiring rcg1 is connected to the read control gate RCG1, and a wiring rcg2 is connected to the read control gate RCG2. The wirings wcg1, wcg2, rcg1, and rcg2 are provided for each line of the pixel unit 100 arranged in the row direction, respectively, and a voltage can be applied by the control unit 40.

  FIG. 11 is a diagram showing a planar layout example of the equivalent circuit diagram shown in FIG. FIG. 11 illustrates two pixel portions 100 adjacent in the row direction. In each line, a plurality of patterns of the two pixel portions 100 shown in FIG. 11 are arranged in the row direction. Since the two pixel portions shown in FIG. 11 are symmetrical with respect to the drain 32 of the reset transistor RT, only the left pixel portion 100 will be described below.

  The photoelectric conversion unit 3 is formed in the P well layer of the pixel unit 100, and the drain 34 of the readout transistor RT1, the source 33 shared by the readout transistors RT1 and RT2, and the readout are slightly spaced to the left of the photoelectric conversion unit 3. The drains 35 of the transistors RT2 are formed side by side in the column direction. Further, a drain 32 of the reset transistor RT is formed slightly adjacent to the right side of the photoelectric conversion unit 3.

  An insulating film (not shown) is formed on the P well layer, and a floating gate FG1 and a floating gate FG2 are formed thereon. The floating gate FG1 extends from the upper side of the photoelectric conversion unit 3 to the upper side between the drain 34 and the source 33 along the left side. The floating gate FG2 is formed to extend from the lower side of the photoelectric conversion unit 3 to the upper part between the drain 35 and the source 33 along the left side.

  An insulating film is provided on the floating gates FG1 and FG2, and write control gates WCG1 and WCG2, read control gates RCG1 and RCG2, and a reset gate RG are formed thereon.

  The write control gate WCG1 is formed so as to overlap the floating gate FG1. The read control gate RCG1 is formed so as to overlap with the floating gate FG1 above between the drain 34 and the source 33.

  The write control gate WCG2 is formed so as to overlap the floating gate FG2. The read control gate RCG2 is formed to overlap the upper floating gate FG2 between the drain 35 and the source 33.

  The reset gate RG is formed above the photoelectric conversion unit 3 and the drain 32. In the layout example of FIG. 11, the drain 32 of the reset transistor RT is shared by two adjacent pixel units 100, and the reset gate RG is connected to the photoelectric conversion unit 3 and the drain 32 of the adjacent pixel unit 100. It is also formed to extend above the gap.

  Global wiring (read control line rcg1, write control line wcg1, write control line wcg2, read) extending in the row direction via an insulating film above the write control gates WCG1, WCG2, read control gates RCG1, RCG2, and reset gate RG. A control line rcg2 and a reset line RL) are formed.

  The read control line rcg1 and the write control line wcg1 are formed on the upper side of the line of the pixel unit 100 so as to extend in the row direction. The write control line wcg2, the read control line rcg2, and the reset line RL are formed to extend in the row direction on the lower side of the line of the pixel portion 100.

  The read control gate RCG1 extends below the read control line rcg1, and is electrically connected to the read control line rcg1 through the contact via 38 here. The write control gate WCG1 extends below the write control line wcg1, and is electrically connected to the write control line wcg1 through the contact via 37 here.

  The read control gate RCG2 extends below the read control line rcg2, and is electrically connected to the read control line rcg2 through the contact via 39 here. The write control gate WCG2 extends below the write control line wcg2, and is electrically connected to the write control line wcg2 through the contact via 36 here.

  The reset gate RG extends below the reset line RL, and is electrically connected to the reset line RL through the contact via RGa.

  An insulating film is formed on the read control line rcg1, the write control line wcg1, the write control line wcg2, the read control line rcg2, and the reset line RL, and a global wiring extending in the column direction (column signal line 12, source) Line SL, reset drain line Vcc) are formed.

  The column signal line 12 and the source line SL are provided for each column of the pixel portion 100, and one reset drain line Vcc is provided for every two columns.

  The column signal line 12 extends to above the drain 34 and is electrically connected to the drain 34 through a contact via 34a. The column signal line 12 also extends above the drain 35 and is electrically connected to the drain 35 through a contact via 35a.

  The source line SL extends to above the source 33 and is electrically connected to the source 33 through a contact via 33a.

  The reset drain line Vcc is formed so as to pass above the drain 32, and is electrically connected to the drain 32 via the contact via 32a above the drain 32.

  In the layout example of FIG. 11, the drains of the write transistors WT1 and WT2 are omitted, and the write transistors WT1 and WT2 are each a two-terminal MOS transistor in which the source (also used as the drain) is connected to the photoelectric conversion unit 3. It is said. As the two-terminal device, there are a resistor, a coil, a capacitor, a diode and the like, but there is no active device such as switching or signal amplification.

  It is understood as common sense that a transistor, which is an active device for performing pixel selection, reset, signal recording, readout, and the like in a general solid-state imaging device, does not function with two terminals, and no one has tried.

  Since the structure of the solid-state imaging device in FIG. 11 has a structure in which the writing transistor WT1 and the reading transistor RT1 share the floating gate FG1, the writing transistor WT1 is exclusively called writing (charge injection and recording to the floating gate FG1). Only single operation and charge transfer in only one direction are required, and at the time of signal reading, the signal can be read also on the adjacent reading transistor RT1 side by the shared FG structure, so that the writing transistor WT1 has a two-terminal structure. It turns out that there is no problem in operation even if it exists. The same applies to the write transistor WT2.

  In the solid-state imaging device shown in FIG. 11, since it is necessary to form a plurality of readout units in the pixel unit 100, the degree of freedom in design is reduced. Therefore, it is effective to simplify the configuration by providing the write transistors WT1 and WT2 with a two-terminal structure including a source connected to the photoelectric conversion unit 11 and a write control gate. In addition, in the example of FIG. 11, the sources of the read transistor RT1 and the read transistor RT2 are also shared, and the reset transistors RT of the two adjacent pixel units 100 are also shared. For this reason, it is possible to reduce the size and chip size of the pixel unit 100, and it is possible to realize a large number of pixels and miniaturization.

  The imaging operation of the solid-state imaging device shown in FIG. 10 is the same as that shown in FIG. Specifically, after resetting the photoelectric conversion unit 3, charges generated in the photoelectric conversion unit 3 during the first exposure period are accumulated in the floating gate FG1, and generated in the photoelectric conversion unit 3 during the second exposure period. The stored charges are stored in the floating gate FG2. Next, the read circuit 20 reads the change in the threshold voltage of the nonvolatile memory transistor MT1 as a signal, and then reads the change in the threshold voltage of the nonvolatile memory transistor MT2 as a signal.

  As described above, even in the shared FG structure illustrated in FIG. 10, power consumption can be suppressed and high image quality can be achieved without complicating the configuration and driving of the pixel portion. Also in the configuration shown in FIG. 11, the floating gate FG1 and the channel region of the nonvolatile memory transistor MT1 and the floating gate FG2 and the channel region of the nonvolatile memory transistor MT2 are shielded by the light shielding film, and the photoelectric conversion unit 3 is nonvolatile. The charge injection efficiency can be improved by extending the channel region of the volatile memory transistor MT1 and the channel region of the nonvolatile memory transistor MT2.

(Third modification)
FIG. 12 is an equivalent circuit diagram showing a third modification of the pixel portion of the solid-state imaging device shown in FIG. In FIG. 2, the two transistors of the non-volatile memory transistor MT1 and the non-volatile memory transistor MT2 are provided as the charge storage units for the photoelectric conversion unit 3 in the pixel unit 100, but the pixel unit shown in FIG. In this case, the charge storage unit is provided with a floating diffusion capacitor, which is a PN junction capacitor charge storage unit, instead of the nonvolatile memory transistor.

  The first charge storage unit of the pixel unit shown in FIG. 12 includes a switch transistor ST1, a floating diffusion capacitor C1 that functions as a charge storage region of the charge storage unit, a reset transistor RET1, and a source follower amplifier SFA1.

  The switch transistor ST1 performs transfer control of charges in the photoelectric conversion unit 3 to the floating diffusion capacitor C1. The source follower amplifier SFA1 outputs a signal corresponding to the amount of charge accumulated in the floating diffusion capacitor C1. The reset transistor RET1 is for resetting the potential of the floating diffusion capacitor C1 to the power supply voltage Vcc.

  The second charge storage section of the pixel section shown in FIG. 12 includes a switch transistor ST2, a floating diffusion capacitor C2 that functions as a charge storage area of the charge storage section, a reset transistor RET2, and a source follower amplifier SFA2.

  The switch transistor ST2 performs transfer control of charges in the photoelectric conversion unit 3 to the floating diffusion capacitor C2. The source follower amplifier SFA2 outputs a signal corresponding to the amount of charge accumulated in the floating diffusion capacitor C2. The reset transistor RET2 is for resetting the potential of the floating diffusion capacitor C2 to the power supply voltage Vcc.

  In the solid-state imaging device having the pixel portion shown in FIG. 12, the source follower amplifier SFA1 and the source follower amplifier SFA2 each amplify and read out a signal corresponding to the charge generated in the photoelectric conversion unit 3 for each pixel portion. A readout circuit different from the readout circuit 20 shown in FIG. 1, for example, a correlated double sampling circuit and an AD conversion circuit used in a known CMOS image sensor may be provided.

  Hereinafter, the operation of the solid-state imaging device having the pixel portion shown in FIG. 12 will be described. In response to the shooting instruction, first, the switch transistors ST1 and ST2 and the reset transistors RET1 and RET2 of all the pixel portions are turned on. Thereby, unnecessary charges in the photoelectric conversion unit 3 are transferred to the floating diffusion capacitors C1 and C2, and are discharged from here to the drains of the reset transistors RET1 and RET2. Next, the switch transistors ST1 and ST2 and the reset transistors RET1 and RET2 of all the pixel portions are turned off, respectively. Thereby, the first exposure period is started. When the first exposure period ends, the switch transistors ST1 of all the pixel units are turned on, the charges generated in the photoelectric conversion unit 3 are transferred to the floating diffusion capacitor C1, and the switch transistors ST1 are turned off. Thereby, the second exposure period is started. When the second exposure period ends, the switch transistors ST2 of all the pixel units are turned on, the charges generated in the photoelectric conversion unit 3 are transferred to the floating diffusion capacitor C2, and the switch transistors ST2 are turned off.

  After accumulating the charge generated in the photoelectric conversion unit 3 during the first exposure period and the charge generated in the photoelectric conversion unit 3 during the second exposure period, the amount of charge accumulated in the floating diffusion capacitor C1 is increased. The image pickup signals are read out by driving all the lines to read out the corresponding image pickup signals to the outside by the source follower amplifier SFA1. Next, the image pickup signal corresponding to the amount of charge accumulated in the floating diffusion capacitor C2 is read out to the outside by the source follower amplifier SFA2 to read out the image pickup signal. In the digital signal processing unit inside the imaging apparatus equipped with the solid-state imaging device, the dynamic range is expanded by combining two imaging signals output from the solid-state imaging device.

  Even with the configuration as described above, the power consumption can be suppressed and the image quality can be improved without complicating the driving.

  As described above, the following items are disclosed in this specification.

  The disclosed solid-state imaging device is a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit, a first charge storage unit capable of storing charges generated in the photoelectric conversion unit, and a first charge storage unit. A charge storage unit, and after resetting the photoelectric conversion unit, charges generated in the photoelectric conversion unit during a first exposure period are stored in the first charge storage unit, Writing means for storing charges generated in the photoelectric conversion unit in the second charge storage unit during the second exposure period which is started after the end of the exposure period and having a length different from that of the first exposure period; and the writing A first imaging signal corresponding to the charge accumulated in the first charge accumulation unit and the second charge accumulation unit after the charge is accumulated in the first charge accumulation unit and the second charge accumulation unit by means; A second imaging signal corresponding to the charge stored in the charge storage section; And a signal reading means for reading.

  With this configuration, two imaging signals with different exposure periods can be obtained, so that the dynamic range can be expanded by combining them. Further, since it is possible to eliminate the time difference between the two exposure periods, the dynamic range can be expanded without any problem even for a moving subject.

  In the disclosed solid-state imaging device, the first charge accumulation unit is a first transistor including a first charge accumulation region formed above a semiconductor substrate on which the photoelectric conversion unit is formed, and the second transistor The charge storage portion is a second transistor including a second charge storage region formed above the semiconductor substrate on which the photoelectric conversion portion is formed, and the first charge storage region and the second charge storage region Each of the regions is a region where the electric charge is accumulated by the writing unit.

  In the disclosed solid-state imaging device, each of the first charge accumulation region and the second charge accumulation region is a floating gate.

  With this configuration, noise can be suppressed.

  In the disclosed solid-state imaging device, the photoelectric conversion unit is formed in a semiconductor substrate on which the first transistor and the second transistor are formed, and is provided above the semiconductor substrate. A light-shielding film having an opening above the portion, wherein the charge storage part and channel region of the first transistor and the charge storage part and channel region of the second transistor are covered with the light-shielding film. The photoelectric conversion portion extends to a position below the channel region of the first transistor and the channel region of the second transistor.

  With this configuration, since the photoelectric conversion unit exists under the channel regions of the first transistor and the second transistor, the charge generated in the photoelectric conversion unit according to the light entering from the light shielding film opening is converted into the photoelectric conversion unit. It is possible to efficiently inject into the charge accumulating portion through the channel region from the overlapping portion of the conversion portion with the channel region.

  In the disclosed solid-state imaging device, the channel length and channel width of the first transistor and the channel length and channel width of the second transistor are the same.

  With this configuration, high image quality can be achieved.

  In the disclosed solid-state imaging device, each of the charge generated by the photoelectric conversion unit during the first exposure period and the charge generated by the photoelectric conversion unit during the second exposure period is provided by the writing unit. The storage destination is switched alternately between the first charge storage unit and the second charge storage unit at regular intervals.

  With this configuration, the lifetime of the element can be expected to be extended.

  The disclosed imaging device includes the solid-state imaging device.

  The disclosed imaging device is the imaging device, and includes signal processing means for combining the first imaging signal and the second imaging signal to perform a dynamic range expansion process.

  The disclosed imaging apparatus includes a light emitting unit for illuminating a subject, and the first exposure period is longer than the second exposure period, and when the setting for emitting light is made, The light emitting means emits light during the second exposure period.

  The disclosed imaging method is an imaging method using a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit and a first charge capable of accumulating charges generated in the photoelectric conversion unit. Having a storage part and a second charge storage part, and after resetting the photoelectric conversion part, the charge generated in the photoelectric conversion part during the first exposure period is stored in the first charge storage part, A writing step of accumulating charges generated in the photoelectric conversion unit in the second charge accumulation unit during the second exposure period which is started after the first exposure period and has a length different from that of the first exposure period. And a first imaging signal corresponding to the charges accumulated in the first charge accumulation unit after accumulating charges in the first charge accumulation unit and the second charge accumulation unit by the writing unit, The second charge according to the charge accumulated in the second charge accumulation unit. And a signal readout step of reading out the imaging signal.

  In the disclosed imaging method, the first charge storage unit is a first transistor including a first charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed, and the second transistor The charge storage unit is a second transistor including a second charge storage region formed above the semiconductor substrate on which the photoelectric conversion unit is formed, and the first charge storage region and the second charge storage region Are regions where the charge is accumulated by the writing means.

  In the disclosed imaging method, each of the first charge accumulation region and the second charge accumulation region is a floating gate.

  In the disclosed imaging method, in the writing step, accumulation of charges generated in the photoelectric conversion unit during the first exposure period and charges generated in the photoelectric conversion unit during the second exposure period, respectively. The first is alternately switched between the first charge accumulation unit and the second charge accumulation unit at regular intervals.

  The disclosed imaging method includes a signal processing step of performing dynamic range expansion processing by combining the first imaging signal and the second imaging signal.

  In the disclosed imaging method, the first exposure period is longer than the second exposure period, and light is emitted during the second exposure period when light emission is set to be emitted. .

3 photoelectric conversion unit 10 solid-state imaging device 20 readout circuit 40 control unit 100 pixel unit RT reset transistor WT1, WT2 nonvolatile memory transistors FG1, FG2 floating gate

Claims (15)

A solid-state imaging device having a plurality of pixel portions,
The pixel unit includes a photoelectric conversion unit, a first charge accumulation unit and a second charge accumulation unit capable of accumulating charges generated in the photoelectric conversion unit,
After resetting the photoelectric conversion unit, charges generated in the photoelectric conversion unit during the first exposure period are accumulated in the first charge accumulation unit, and are started after the first exposure period ends and the first Writing means for accumulating charges generated in the photoelectric conversion unit during the second exposure period having a length different from that of the exposure period in the second charge accumulation unit;
A first imaging signal corresponding to the charge accumulated in the first charge accumulation unit after the charge is accumulated in the first charge accumulation unit and the second charge accumulation unit by the writing unit; A solid-state imaging device comprising: a signal readout unit that reads out a second imaging signal corresponding to the charge accumulated in the second charge accumulation unit. The solid-state imaging device according to claim 1,
The first charge storage unit is a first transistor including a first charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
The second charge storage unit is a second transistor including a second charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
A solid-state imaging device, wherein each of the first charge accumulation region and the second charge accumulation region is a region where the charge is accumulated by the writing unit. The solid-state imaging device according to claim 2,
A solid-state imaging device in which each of the first charge accumulation region and the second charge accumulation region is a floating gate. The solid-state imaging device according to claim 2 or 3,
The photoelectric conversion unit is formed in a semiconductor substrate on which the first transistor and the second transistor are formed,
A light-shielding film provided above the semiconductor substrate and having an opening formed above a portion of the photoelectric conversion unit;
The charge storage portion and channel region of the first transistor and the charge storage portion and channel region of the second transistor are covered with the light shielding film,
The solid-state imaging device in which the photoelectric conversion unit extends below a channel region of the first transistor and a channel region of the second transistor. The solid-state image sensor according to any one of claims 2 to 4,
A solid-state imaging device in which a channel length and a channel width of the first transistor are the same as a channel length and a channel width of the second transistor. The solid-state imaging device according to any one of claims 1 to 5,
The writing means is configured to store the charge generated in the photoelectric conversion unit during the first exposure period and the storage destination of the charge generated in the photoelectric conversion unit during the second exposure period, respectively. A solid-state imaging device that switches alternately between a charge storage unit and the second charge storage unit at regular intervals.   An imaging device provided with the solid-state image sensor of any one of Claims 1-6. The imaging apparatus according to claim 7,
An image pickup apparatus comprising signal processing means for combining the first image pickup signal and the second image pickup signal to perform dynamic range expansion processing. The imaging device according to claim 7 or 8,
With light emitting means for illuminating the subject,
The first exposure period is longer than the second exposure period;
An imaging apparatus in which the light emitting means emits light during the second exposure period when setting to emit light is made. An imaging method using a solid-state imaging device having a plurality of pixel portions,
The pixel unit includes a photoelectric conversion unit, a first charge storage unit capable of storing charges generated in the photoelectric conversion unit, and a second charge storage unit,
After resetting the photoelectric conversion unit, charges generated in the photoelectric conversion unit during the first exposure period are accumulated in the first charge accumulation unit, and are started after the first exposure period ends and the first A writing step for accumulating charges generated in the photoelectric conversion unit in the second charge accumulation unit during a second exposure period having a length different from that of the exposure period;
A first imaging signal corresponding to the charge accumulated in the first charge accumulation unit after the charge is accumulated in the first charge accumulation unit and the second charge accumulation unit by the writing unit; An image pickup method comprising: a signal reading step of reading out a second image pickup signal corresponding to the charge accumulated in the second charge accumulation unit. The imaging method according to claim 10, comprising:
The first charge storage unit is a first transistor including a first charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
The second charge storage unit is a second transistor including a second charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
An imaging method in which each of the first charge storage region and the second charge storage region is a region in which the charge is stored by the writing unit. The imaging method according to claim 11,
An imaging method in which each of the first charge accumulation region and the second charge accumulation region is a floating gate. It is the imaging method of any one of Claims 10-12,
In the writing step, the accumulation destinations of the charges generated in the photoelectric conversion unit during the first exposure period and the charges generated in the photoelectric conversion unit during the second exposure period are respectively stored in the first exposure period. An imaging method in which the charge accumulation unit and the second charge accumulation unit are alternately switched at regular intervals. It is an imaging method of any one of Claims 10-13,
An imaging method comprising a signal processing step of performing dynamic range expansion processing by combining the first imaging signal and the second imaging signal. The imaging method according to any one of claims 10 to 14,
The first exposure period is longer than the second exposure period;
An imaging method in which light is emitted during the second exposure period when light emission is set.

Images