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JP2010272585A - Flip-chip mounting structure - Google Patents

Flip-chip mounting structure Download PDF

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Publication number
JP2010272585A
JP2010272585A JP2009121241A JP2009121241A JP2010272585A JP 2010272585 A JP2010272585 A JP 2010272585A JP 2009121241 A JP2009121241 A JP 2009121241A JP 2009121241 A JP2009121241 A JP 2009121241A JP 2010272585 A JP2010272585 A JP 2010272585A
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Prior art keywords
flip
ground layer
mounting structure
chip mounting
frequency circuit
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Japanese (ja)
Inventor
Hideyuki Koide
秀之 小出
Kazunori Sugaya
和則 菅谷
Koichi Muroi
浩一 室井
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2009121241A priority Critical patent/JP2010272585A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-chip mounting structure which suppresses resonance occurring in a prescribed region in a simple structure so as to improve an isolation characteristic and to miniaturize the structure. <P>SOLUTION: The flip-chip mounting structure includes a ground pattern 25 formed on a multilayer dielectric substrate 20, and connection parts (through-holes 12 and 28, and bumps 27) that electrically connect a ground pattern 11 formed on a high-frequency circuit chip 10 which is flip-chip mounted so that it may be confronted with the ground pattern 25, with the ground pattern 25. A part of the ground pattern 25 is made as a resistor 30. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、フリップチップ実装構造に関し、マイクロ波又はミリ波帯の回路で使用されフリップチップ実装構造の改良に関するものである。   The present invention relates to a flip chip mounting structure, and relates to an improvement of a flip chip mounting structure used in a microwave or millimeter wave band circuit.

従来のフリップチップ実装構造では、誘電体基板の高周波回路チップに対向した部分を切り欠き、さらに誘電体基板下側に、電波吸収体を装着する基台を設けるようにしている。その結果、高周波回路チップと誘電体基板との間、及び高周波回路チップと基台との間の電磁波の伝搬が抑制され、高周波回路チップの各ポート間のアイソレーションが向上する（例えば、特許文献１参照）。   In the conventional flip chip mounting structure, a portion of the dielectric substrate facing the high frequency circuit chip is cut out, and a base for mounting the radio wave absorber is provided below the dielectric substrate. As a result, propagation of electromagnetic waves between the high-frequency circuit chip and the dielectric substrate and between the high-frequency circuit chip and the base is suppressed, and isolation between each port of the high-frequency circuit chip is improved (for example, Patent Documents). 1).

特開２００２−５７５１３号公報JP 2002-57513 A

しかしながら、上記従来のフリップチップ実装構造によれば、誘電体基板の高周波回路チップに対向した部分を切り欠く必要があり、この部分に配線のためのスペースを確保できず、他の場所に設けなければならず、また切り欠きを設ける厚みが必要となり、誘電体基板が大型化するという問題があった。   However, according to the above conventional flip chip mounting structure, it is necessary to cut out a portion of the dielectric substrate facing the high frequency circuit chip, and a space for wiring cannot be secured in this portion, and it must be provided elsewhere. In addition, there is a problem that the thickness of the notch is required and the dielectric substrate becomes large.

本発明は、上記に鑑みてなされたものであって、所定の領域に発生する共振を簡素な構造にて抑制することができ、これにより、アイソレーション特性の向上と小型化を図ることができるフリップチップ実装構造を提供することを目的とする。   The present invention has been made in view of the above, and can suppress resonance generated in a predetermined region with a simple structure, thereby improving isolation characteristics and downsizing. An object is to provide a flip chip mounting structure.

上述した課題を解決し、目的を達成するために、本発明のフリップチップ実装構造は、誘電体基板上に高周波回路チップをフリップチップ実装するフリップチップ実装構造において、誘電体基板に形成された第１のグランド層と、高周波回路チップに第１のグランド層と対向するように形成された第２のグランド層と、第１のグランド層及び第２のグランド層を電気的に接続する接続部とを備え、第１のグランド層の少なくとも一部を抵抗体としたことを特徴とする。   In order to solve the above-described problems and achieve the object, the flip chip mounting structure of the present invention is a flip chip mounting structure in which a high frequency circuit chip is flip chip mounted on a dielectric substrate. A first ground layer, a second ground layer formed on the high-frequency circuit chip so as to face the first ground layer, and a connection portion that electrically connects the first ground layer and the second ground layer. And at least part of the first ground layer is a resistor.

また、本発明の他のフリップチップ実装構造は、誘電体基板上に高周波回路チップをフリップチップ実装するフリップチップ実装構造において、誘電体基板に形成された第１のグランド層と、高周波回路チップに第１のグランド層と対向するように形成された第２のグランド層と、第１のグランド層及び第２のグランド層を電気的に接続する接続部とを備え、第１のグランド層の少なくとも一部の部分に高周波減衰材料を配設したことを特徴とする。   Another flip-chip mounting structure of the present invention is a flip-chip mounting structure in which a high-frequency circuit chip is flip-chip mounted on a dielectric substrate. The first ground layer formed on the dielectric substrate and the high-frequency circuit chip include A second ground layer formed so as to face the first ground layer; and a connection portion that electrically connects the first ground layer and the second ground layer, and at least one of the first ground layers A high-frequency attenuating material is disposed in a part of the structure.

本発明のフリップチップ実装構造によれば、第１のグランド層に設けられた抵抗体は、この抵抗体を流れる高周波電流を熱に変換して、所定の領域に発生する共振を抑制する。これにより、簡素な構成で共振を抑制することができ、アイソレーション特性の向上と装置の小型化を図ることができるという効果を奏する。   According to the flip chip mounting structure of the present invention, the resistor provided in the first ground layer converts the high-frequency current flowing through the resistor into heat and suppresses resonance generated in a predetermined region. Thereby, resonance can be suppressed with a simple configuration, and the effect of improving the isolation characteristics and reducing the size of the apparatus can be achieved.

また、本発明の他のフリップチップ実装構造によれば、第１のグランド層に設けられた高周波減衰材料は、所定の領域に流れる高周波信号を減衰させる。これにより、簡素な構成で共振を抑制することができ、アイソレーション特性の向上と装置の小型化を図ることができるという効果を奏する。   According to another flip chip mounting structure of the present invention, the high frequency attenuation material provided in the first ground layer attenuates a high frequency signal flowing in a predetermined region. Thereby, resonance can be suppressed with a simple configuration, and the effect of improving the isolation characteristics and reducing the size of the apparatus can be achieved.

図１は、この発明の実施の形態１によるフリップチップ実装構造を示す平面図である。1 is a plan view showing a flip chip mounting structure according to Embodiment 1 of the present invention. 図２は、図１のＢ−Ｂ線に沿う横断面図である。2 is a cross-sectional view taken along line BB in FIG. 図３は、この発明の実施の形態２によるフリップチップ実装構造を示す横断面図である。3 is a cross-sectional view showing a flip chip mounting structure according to Embodiment 2 of the present invention.

以下に、本発明にかかるフリップチップ実装構造の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。   Embodiments of a flip chip mounting structure according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

実施の形態１．
図１は、この発明の実施の形態１によるフリップチップ実装構造を示す平面図である。図２は、図１のＢ−Ｂ線に沿う横断面図である。なお、図１は、入出力線路の配置が見えるように高周波回路チップ１０を外した状態の平面図である（高周波回路チップ１０の輪郭を破線で示す）。フリップチップ実装構造は、多層誘電体基板（以降、多層基板）２０上にフリップフリップ実装されるＭＭＩＣ（Monolithic Microwave Integrated Circuit）などの高周波回路チップ１０を有している。このようなフリップフリップ実装では、多層基板２０上に高周波回路チップ１０を実装する際にバンプ２１、２２、２７と呼ばれる突起状の端子によって接続する。 Embodiment 1 FIG.
1 is a plan view showing a flip chip mounting structure according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along line BB in FIG. FIG. 1 is a plan view of the state in which the high-frequency circuit chip 10 is removed so that the arrangement of the input / output lines can be seen (the outline of the high-frequency circuit chip 10 is indicated by a broken line). The flip chip mounting structure includes a high frequency circuit chip 10 such as an MMIC (Monolithic Microwave Integrated Circuit) which is flip flip mounted on a multilayer dielectric substrate (hereinafter referred to as a multilayer substrate) 20. In such flip-flip mounting, when the high-frequency circuit chip 10 is mounted on the multilayer substrate 20, connection is made by protruding terminals called bumps 21, 22, and 27.

多層基板２０の表層には、マイクロストリップなどの入力線路２３および出力線路２４が形成されている。なお図２においては、この入力線路２３および出力線路２４を模式的に連続する黒丸にて表現している。入力線路２３がバンプ２１により高周波回路チップ１０の入力端子に接続される。また、高周波回路チップ１０の出力端子はバンプ２２により出力線路２４に接続される。入力線路２３と出力線路２４とは、高周波回路チップ１０を挟んで両側に形成されている。   An input line 23 such as a microstrip and an output line 24 are formed on the surface layer of the multilayer substrate 20. In FIG. 2, the input line 23 and the output line 24 are schematically represented by continuous black circles. The input line 23 is connected to the input terminal of the high-frequency circuit chip 10 by the bump 21. The output terminal of the high-frequency circuit chip 10 is connected to the output line 24 by the bump 22. The input line 23 and the output line 24 are formed on both sides of the high frequency circuit chip 10.

多層基板２０の中間部には、グランドパターン（第１のグランド層）２５が、多層基板２０の全領域にわたって形成されている。このグランドパターン２５は、多層基板２０の各層のうち、高周波回路チップ１０側となる、高周波信号が流れる伝送路などが設けられる層と、多層基板２０の高周波回路チップ１０と反対側で、電源供給路を形成したり、制御信号を配線する層とを分離して、両領域の電気的な結合を防止する目的で設けられている。   A ground pattern (first ground layer) 25 is formed over the entire area of the multilayer substrate 20 in the intermediate portion of the multilayer substrate 20. The ground pattern 25 supplies power to each of the layers of the multilayer substrate 20 on the side of the high-frequency circuit chip 10, the layer provided with a transmission path through which a high-frequency signal flows, and the opposite side of the multilayer substrate 20 to the high-frequency circuit chip 10. It is provided for the purpose of forming a path or separating a layer for wiring a control signal to prevent electrical coupling between the two regions.

高周波回路チップ１０の図２中上側の外方に臨む表面には全面にわたってグランドパターン（第２のグランド層）１１が形成されている。このグランドパターン１１は、高周波回路チップ１０を貫通するスルーホール１２と、多層基板２０中を積層方向に延びるスルーホール２８と、高周波回路チップ１０及び多層基板２０の間に設けられたバンプ２７により電気的に接続されている。なお、スルーホール１２、２８及びバンプ２７は、グランドパターン（第１のグランド層）２５とグランドパターン（第２のグランド層）１１を電気的に接続するグランド層接続部（接続部）を構成している。   A ground pattern (second ground layer) 11 is formed on the entire surface of the high-frequency circuit chip 10 facing the outside in FIG. The ground pattern 11 is electrically connected by through holes 12 penetrating the high frequency circuit chip 10, through holes 28 extending in the stacking direction in the multilayer substrate 20, and bumps 27 provided between the high frequency circuit chip 10 and the multilayer substrate 20. Connected. The through holes 12 and 28 and the bumps 27 constitute a ground layer connecting portion (connecting portion) that electrically connects the ground pattern (first ground layer) 25 and the ground pattern (second ground layer) 11. ing.

高周波回路チップ１０に形成されたグランドパターン１１と、多層基板２０に形成されたグランドパターン２５により挟まれた図２中点線で示す領域（グランドパターン１１とこのグランドパターン１１をグランドパターン２５に投影した部分とを、対向する２面とする直方体の領域）を領域Ａとする。上記グランド層接続部を構成する、スルーホール１２、２８及びバンプ２７は、この領域Ａを囲む位置（境界）に複数個設けられている。   An area indicated by a dotted line in FIG. 2 sandwiched between the ground pattern 11 formed on the high-frequency circuit chip 10 and the ground pattern 25 formed on the multilayer substrate 20 (the ground pattern 11 and the ground pattern 11 are projected onto the ground pattern 25. The region A is a rectangular parallelepiped region having two portions facing each other. A plurality of through holes 12, 28 and bumps 27 constituting the ground layer connecting portion are provided at a position (boundary) surrounding the region A.

ここで、領域Ａの大きさを、図１に示すように、幅方向大きさをａ、長さ方向大きさをｂ、積層方向大きさ（高さ）をｃとすると、領域Ａは、

Figure 2010272585
で表される波長で共振する。なお、ｎ、ｍ、ｐは、自然数である。 Here, when the size of the region A is as shown in FIG. 1, the width direction size is a, the length direction size is b, and the stacking direction size (height) is c.
Figure 2010272585
 Resonates at a wavelength represented by Note that n, m, and p are natural numbers.

そして、この領域Ａが共振する周波数では、その振動のために空間のアイソレーション特性が劣化し、高周波回路チップ１０の入力端子（バンプ２１）と出力端子（バンプ２２）間の結合が増大する。これにより、周波数特性が劣化し、特に高周波回路チップ１０が増幅器等の動作をする場合には発振現象を起こすこともある。   At the frequency at which the region A resonates, the space isolation characteristics deteriorate due to the vibration, and the coupling between the input terminal (bump 21) and the output terminal (bump 22) of the high-frequency circuit chip 10 increases. As a result, the frequency characteristics deteriorate, and an oscillation phenomenon may occur particularly when the high-frequency circuit chip 10 operates as an amplifier or the like.

そこで、本実施の形態では、グランドパターン２５の一部を抵抗体３０にしている。グランドパターン２５の一部を抵抗体３０とすることにより、この抵抗体３０を高周波電流が流れる際、高周波電流は熱に変換される。これにより、共振に伴う高周波電流が減衰し、共振を抑制することができる。   Therefore, in this embodiment, a part of the ground pattern 25 is the resistor 30. By using a part of the ground pattern 25 as the resistor 30, when the high frequency current flows through the resistor 30, the high frequency current is converted into heat. Thereby, the high frequency current accompanying resonance is attenuated, and resonance can be suppressed.

以上のように、本実施の形態のフリップチップ実装構造は、多層基板２０に形成されたグランドパターン２５と、この多層基板２０にフリップチップ実装される高周波回路チップ１０に、このグランドパターン２５と対向するように形成されたグランドパターン１１と、グランドパターン２５とを電気的に接続する接続部（スルーホール１２、２８及びバンプ２７）とを備え、グランドパターン２５の一部を抵抗体３０としているので、抵抗体３０は、この抵抗体３０を流れる高周波電流を熱に変換して、領域Ａに発生する共振を抑制する。このようにして、簡素な構成で共振を抑制することができ、アイソレーション特性の向上と装置の小型化を図ることができる。   As described above, the flip chip mounting structure of the present embodiment has the ground pattern 25 formed on the multilayer substrate 20 and the high frequency circuit chip 10 flip-chip mounted on the multilayer substrate 20 facing the ground pattern 25. Since the ground pattern 11 formed so as to be connected to the ground pattern 25 is electrically connected to the ground pattern 25 (through holes 12, 28 and bumps 27), and the resistor 30 is a part of the ground pattern 25. The resistor 30 converts the high-frequency current flowing through the resistor 30 into heat and suppresses the resonance generated in the region A. In this way, resonance can be suppressed with a simple configuration, and isolation characteristics can be improved and the apparatus can be downsized.

実施の形態２．
図３は、この発明の実施の形態２によるフリップチップ実装構造を示す横断面図である。本実施の形態においては、実施の形態１の抵抗体３０に替えて、グランドパターン２５の一部の箇所に、高周波を減衰するフェライト等の高周波減衰材料３１が配設されている。その他の構成は実施の形態１と同様である。 Embodiment 2. FIG.
FIG. 3 is a cross-sectional view showing a flip chip mounting structure according to Embodiment 2 of the present invention. In the present embodiment, instead of the resistor 30 of the first embodiment, a high frequency attenuation material 31 such as ferrite that attenuates the high frequency is disposed at a part of the ground pattern 25. Other configurations are the same as those of the first embodiment.

本実施の形態のように、グランドパターン２５の一部に高周波減衰材料を配設することによっても、領域Ａの共振を抑制することができる。   As in the present embodiment, the resonance of the region A can also be suppressed by disposing a high frequency attenuation material in a part of the ground pattern 25.

なお、上記実施の形態１及び２の誘電体基板は、多層誘電体基板２０であるが、必ずしも多層の誘電体基板に限られるものではなく、単層の誘電体基板であってもよい。また、上記実施の形態１の抵抗体３０及び実施の形態２の高周波減衰材料３１は、グランドパターン２５の一部に設けられているが、グランドパターン２５の高周波回路チップ１０に対向する部分の全体にわたって設けられてもよい。   The dielectric substrate of the first and second embodiments is the multilayer dielectric substrate 20, but is not necessarily limited to a multilayer dielectric substrate, and may be a single-layer dielectric substrate. Further, the resistor 30 of the first embodiment and the high-frequency attenuation material 31 of the second embodiment are provided in a part of the ground pattern 25, but the entire portion of the ground pattern 25 facing the high-frequency circuit chip 10. May be provided.

また、上記実施の形態１の抵抗体３０及び実施の形態２の高周波減衰材料３１は、多層誘電体基板２０の中間層に設けられているが、多層誘電体基板２０の高周波回路チップ１０側の表面に設けられてもよいし、逆に多層誘電体基板２０の高周波回路チップ１０と反対側の裏面に設けられてもよい。   Further, the resistor 30 of the first embodiment and the high-frequency attenuation material 31 of the second embodiment are provided in the intermediate layer of the multilayer dielectric substrate 20, but on the high-frequency circuit chip 10 side of the multilayer dielectric substrate 20. It may be provided on the front surface, or conversely, may be provided on the back surface of the multilayer dielectric substrate 20 opposite to the high frequency circuit chip 10.

以上のように、本発明にかかるフリップチップ実装構造は、誘電体基板と、この誘電体基板上にフリップチップ実装される高周波半導体とを有する高周波パッケージなどに有用である。   As described above, the flip chip mounting structure according to the present invention is useful for a high frequency package having a dielectric substrate and a high frequency semiconductor flip chip mounted on the dielectric substrate.

１０ 高周波回路チップ、１１ グランドパターン（第２のグランド層）、１２ スルーホール、２０ 多層誘電体基板（誘電体基板）、２１ バンプ（高周波回路チップの入力端子）、２２ バンプ（高周波回路チップの出力端子）、２３ 入力線路、２４ 出力線路、２５ グランドパターン（第１のグランド層）、２７ バンプ、２８ スルーホール。   10 high frequency circuit chip, 11 ground pattern (second ground layer), 12 through hole, 20 multilayer dielectric substrate (dielectric substrate), 21 bump (input terminal of high frequency circuit chip), 22 bump (output of high frequency circuit chip) Terminal), 23 input lines, 24 output lines, 25 ground pattern (first ground layer), 27 bumps, 28 through holes.

Claims (6)

誘電体基板上に高周波回路チップをフリップチップ実装するフリップチップ実装構造において、
前記誘電体基板に形成された第１のグランド層と、
前記高周波回路チップに前記第１のグランド層と対向するように形成された第２のグランド層と、
前記第１のグランド層及び前記第２のグランド層を電気的に接続する接続部とを備え、 前記第１のグランド層の少なくとも一部を抵抗体とした
ことを特徴とするフリップチップ実装構造。 In a flip chip mounting structure in which a high frequency circuit chip is flip chip mounted on a dielectric substrate,
A first ground layer formed on the dielectric substrate;
A second ground layer formed on the high-frequency circuit chip so as to face the first ground layer;
A flip chip mounting structure comprising: a connecting portion that electrically connects the first ground layer and the second ground layer, wherein at least a part of the first ground layer is a resistor. 前記抵抗体は、前記抵抗体に流れる高周波電流を熱に変換する
ことを特徴とする請求項１に記載のフリップチップ実装構造。 The flip-chip mounting structure according to claim 1, wherein the resistor converts a high-frequency current flowing through the resistor into heat. 前記第１のグランド層の前記第２のグランド層に対向する全ての部分が抵抗体である
ことを特徴とする請求項１または２に記載のフリップチップ実装構造。 3. The flip-chip mounting structure according to claim 1, wherein all portions of the first ground layer that face the second ground layer are resistors. 前記抵抗体は、多層の前記誘電体基板間に充填されて形成されている
ことを特徴とする請求項１から３のいずれか１項に記載のフリップチップ実装構造。 4. The flip-chip mounting structure according to claim 1, wherein the resistor is formed by being filled between multilayer dielectric substrates. 5. 誘電体基板上に高周波回路チップをフリップチップ実装するフリップチップ実装構造において、
前記誘電体基板に形成された第１のグランド層と、
前記高周波回路チップに前記第１のグランド層と対向するように形成された第２のグランド層と、
前記第１のグランド層及び前記第２のグランド層を電気的に接続する接続部とを備え、 前記第１のグランド層の少なくとも一部に高周波減衰材料を配設した
ことを特徴とするフリップチップ実装構造。 In a flip chip mounting structure in which a high frequency circuit chip is flip chip mounted on a dielectric substrate,
A first ground layer formed on the dielectric substrate;
A second ground layer formed on the high-frequency circuit chip so as to face the first ground layer;
A flip chip comprising: a connecting portion for electrically connecting the first ground layer and the second ground layer; and a high-frequency attenuating material disposed on at least a part of the first ground layer. Mounting structure. 前記高周波減衰材料は、フェライトである
ことを特徴とする請求項５に記載のフリップチップ実装構造。 The flip-chip mounting structure according to claim 5, wherein the high-frequency attenuation material is ferrite.
JP2009121241A 2009-05-19 2009-05-19 Flip-chip mounting structure Pending JP2010272585A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011122311A1 (en) * 2010-03-31 2011-10-06 古河電気工業株式会社 High-frequency circuit board
WO2015190236A1 (en) * 2014-06-10 2015-12-17 株式会社日立製作所 Chip module and information processing device
CN113629042A (en) * 2021-06-29 2021-11-09 北京七芯中创科技有限公司 Integrated structure based on flip-chip technology chip and substrate antenna

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011122311A1 (en) * 2010-03-31 2011-10-06 古河電気工業株式会社 High-frequency circuit board
US9082785B2 (en) 2010-03-31 2015-07-14 Furukawa Electric Co., Ltd. High-frequency circuit board
WO2015190236A1 (en) * 2014-06-10 2015-12-17 株式会社日立製作所 Chip module and information processing device
CN113629042A (en) * 2021-06-29 2021-11-09 北京七芯中创科技有限公司 Integrated structure based on flip-chip technology chip and substrate antenna

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