JP2010246190A - DC-DC converter and control unit thereof - Google Patents

Abstract

【Task】
Provided is a DC-DC converter that effectively suppresses an increase in output voltage due to a leakage current of an output switching transistor.
[Solution]
First and second switches connected in series between an input terminal to which an input voltage is supplied and the ground; an inductor provided between a connection node of the first and second switches and an output terminal; In a DC-DC converter having a smoothing capacitor connected to an output terminal, a switching control circuit for performing burst control to turn on the second switch after turning on the first switch when the output voltage drops to the reference voltage; , And a pseudo load current generating circuit for monitoring the burst control and flowing a pseudo load current from the output terminal when the burst control is not performed for a predetermined period.
[Selection] Figure 2

Description

  The present invention relates to a DC-DC converter that generates an output DC voltage of a different voltage from an input DC voltage, and a control unit thereof.

  The constant voltage circuit is a power generation circuit that inputs a DC power supply, converts it to a required voltage value, and outputs it. Due to the recent demand for power saving, demand for DC-DC converters with good power efficiency among constant voltage circuits is increasing.

  In addition, there is an increasing demand for expanding the operating temperature range of electronic devices, and a stable output voltage is required over a wide temperature range.

  The constant voltage circuit includes a switching regulator that intermittently switches the transistor connected to the input DC voltage according to the output voltage level, and supplies the output voltage to the load circuit via a smoothing filter consisting of an inductor and a capacitor. There is a linear regulator that generates an output voltage by controlling the current of a transistor connected to a DC voltage in an analog manner according to the level of the output voltage. In addition, an AC-DC converter that has a rectifier circuit and generates an output DC power source having a predetermined voltage from an AC power source has also been proposed.

  The above circuits are described in, for example, Patent Document 1 (switching regulator), Patent Document 2 (linear regulator), Patent Document 3 (AC-DC converter), and the like.

  FIG. 1 is a circuit diagram of a conventional linear regulator. This linear regulator is provided between a PMOS transistor M1 provided between an input terminal to which an input voltage Vin is supplied and an output terminal OUT from which an output voltage Vo is output, and between the output terminal OUT and the ground Vss. The feedback resistor R1, R2 and the error amplifier A14 that compares the connection node n10 of the feedback resistor R1, R2 with the reference voltage Vref and generates a voltage corresponding to the difference between them at the output node n12. The error amplifier A14 includes a pair of PMOS transistors M5 and M6 constituting a current mirror circuit, a pair of NMOS transistors M3 and M4 constituting a differential circuit, and a current source NMOS transistor M2. The output terminal OUT is connected to the load circuit 10, and the output voltage Vo is supplied to the load circuit 10.

  Briefly explaining the operation, the output voltage Vo decreases as the load current Io by the load circuit 10 increases. As a result, the potential of the connection node n10 is lowered, the transistor M3 is turned on, and the potential of the output node n12 is further lowered. As a result, the gate voltage of the PMOS transistor M1 decreases, the current Ix flowing therethrough increases, and the output voltage Vo increases. When the output voltage Vo increases due to the decrease in the load current Io, the output voltage Vo is decreased by the reverse operation to the above. In this way, the output voltage Vo is kept constant (Vo = ((R1 + R2) / R2) * Vref) by linearly controlling the current Ix of the output power transistor M1.

  When the load circuit 10 is in a light load state, the load current Io decreases, and when the current Ix exceeds the load current Io, the supply voltage becomes excessive and the output voltage Vo tends to increase. As a result, the transistor M1 is controlled to be almost non-conductive and the output voltage is kept constant. However, a constant leakage current is generated even when the transistor M1 is in the off state. In particular, this leakage current increases as the temperature rises.

  When the transistor M1 is in the off state, if this leakage current exceeds the sum of the load current Io in the light load state and the current Ia to the feedback resistor, the supply will be excessive and the output voltage cannot be kept constant. And the failure such as destruction of the load circuit 10 occurs. In order to cope with this, in the circuit of FIG. 1, an NMOS transistor M7 and a constant current source A12 are provided between the output terminal OUT and the ground Vss, and the input voltage Vin is compared with the output n12 of the error amplifier A14. Thus, a comparator A10 for controlling the gate of the NMOS transistor M7 is provided.

  According to such a circuit, when the leakage current of the output transistor M1 becomes larger than Io + Ia and the output voltage Vo rises, the potential of the node n12 rises to about the input voltage Vin, the output of the comparator A10 becomes H level, and the transistor Turn on M7. As a result, current from the current source A12 flows from the output terminal OUT, and the leakage current of the output transistor M1 is absorbed. As a result, an excessive increase in the output voltage Vo can be suppressed.

JP 2008-67454 A JP 2007-334573 A Japanese Patent Laid-Open No. 10-80135

  In the linear regulator of FIG. 1, the leakage current of the output transistor M1 is absorbed by flowing a constant current of the current source A12 from the output terminal OUT, thereby preventing an excessive increase in the output voltage Vo. Since the current is constant, it is necessary to design the current amount of the current source A12 to be large including a margin in consideration of the characteristic variation of the output transistor M1, which may lead to waste of power consumption. Further, since a relatively large constant current flows from the output terminal OUT at the moment when the leakage current increases at a high temperature and the output voltage Vo rises and the transistor M7 is turned on, the output voltage Vo changes rapidly. In addition, when the specifications of the output voltage Vo are changed and the resistance values of the feedback resistors R1 and R2 are changed to cope with this, the current Ia also changes, and the current amount of the current source A12 must also be changed. Changes are entered. Further, since the size of the output transistor M1 is changed even when the specification of the output current capability is changed and the leakage current is changed, the current amount of the current source A12 needs to be changed accordingly.

  Further, the circuit of FIG. 1 is applied to a linear regulator, and a switching regulator is also required to prevent an increase in output voltage due to a leakage current of an output switching transistor.

  Therefore, an object of the present invention is to provide a DC-DC converter that effectively suppresses an increase in output voltage due to a leakage current of an output switching transistor.

A first aspect of the present embodiment is a DC-DC converter having an input terminal to which an input voltage is supplied and an output terminal to which an output voltage is output and connected to a load circuit.
First and second switches connected in series between the input terminal and ground;
An inductor provided between a connection node of the first and second switches and the output terminal;
A smoothing capacitor connected to the output terminal;
A switching control circuit for performing burst control for turning on the second switch after turning on the first switch when the output voltage drops to a reference voltage;
A pseudo load current generation circuit that monitors the burst control and causes a pseudo load current to flow from the output terminal when the burst control is not performed for a predetermined period.

  According to the first aspect, since the pseudo load current flows when the output voltage increases for some reason, the increase can be suppressed.

It is a circuit diagram of the linear regulator provided with the conventional leak compensation circuit. It is a block diagram of the DC-DC converter in this Embodiment. 2 is a configuration diagram of a current control circuit 24. FIG. It is an operation waveform diagram in PWM control of a DC-DC converter. It is a figure which shows the operation | movement of the PFM control of the DC-DC converter in this Embodiment, and a pseudo load current generation circuit.

  FIG. 2 is a configuration diagram of the DC-DC converter in the present embodiment. The DC-DC converter includes a first switch M11 and a second switch M12 connected in series between an input voltage terminal IN to which an input voltage Vin is applied and a ground Vss, and first and second switches. And an inductor Lout provided between the switch connection point LX and the output terminal OUT from which the output voltage Vout is output, and a smoothing capacitor Co provided between the output terminal OUT and the ground Vss. A load circuit 10 to which an output voltage Vo is supplied is connected to the output terminal OUT, and a load current Io corresponding to the magnitude of the load is supplied from the output terminal OUT to the load circuit 10. The input voltage VIN is a predetermined DC voltage, and the output voltage Vout is a DC voltage lower than the input voltage VIN.

  Further, the DC-DC converter includes feedback resistors R11 and R12 connected to the output terminal OUT, an error amplifier A1 for detecting a difference voltage between the feedback voltage Vfb at the connection point and the first reference voltage Vref1, and an error. Based on the comparator A2 that compares the output Ver of the amplifier A1 and the second reference voltage Vref2, and the output Ver of the error amplifier A1 and the output VB of the comparator A2, the first and second switches M11 and M12 are turned on / off. And a switching control circuit 20 for controlling OFF.

  The first switch M11 is a high-side output transistor composed of a P-channel MOS transistor, and conduction and non-conduction are controlled by the gate drive signal Vgh generated by the switching control circuit 20. The second switch M12 is a low-side output transistor composed of an N-channel MOS transistor, and conduction and non-conduction are controlled by the gate drive signal Vgl generated by the switching control circuit 20.

  The output Ver of the error amplifier A1 corresponds to the difference voltage from the reference voltage Vref1. Then, when the load circuit 10 is in a normal load state, the switching control circuit 20 alternately turns on and off the first and second switches M11 and M12 at a constant cycle, and the magnitude of the load current Io. Pulse width modulation control (PWM control) is performed to variably control the duty ratio for turning on the first switch M11 in accordance with (the potentials of the output voltages Vo, Vfb or the error voltage Ver).

  Furthermore, when the load circuit 10 is in a light load state, the switching control circuit 20 has a frequency corresponding to the magnitude of the load current Io (or the potential of the output voltage Vo, Vfb or error voltage Ver) at the first and second frequencies. Pulse frequency modulation control (PFM control) is performed for burst control of the switches M11 and M12 on / off and off / on. Specifically, the first and second switches M11 and M12 are burst controlled based on the output VB of the comparator A2. In FIG. 2, the load state detection circuit is omitted.

  Furthermore, this DC-DC converter has an excessively high output voltage Vo when the leakage current ILEAK of the first switch M11 increases due to a temperature rise or the like and ILEAK> Ia + Io at light load. In order to suppress the increase, a pseudo load current generation circuit 22 is provided. The pseudo load current generation circuit 22 includes a burst pulse detection circuit 23 and a current control circuit 24. When the output voltage Vo rises due to an increase in leakage current, an appropriate amount of pseudo load current is output from the output terminal OUT. Run Ib.

  FIG. 3 is an example of the current control circuit 24. The current control circuit 24 includes a plurality of current sources M20 and M21 formed of NMOS transistors, and a control unit 26 that controls the current source transistors. The number of current sources M20 and M21 is not limited to two, and it is preferable that a larger number be provided. Note that the embodiment is not limited to the current control circuit 24 and a configuration that realizes the operation of a pseudo-current generation circuit described later can be applied as the current control circuit.

  Next, PWM control using a DC-DC converter is described.

  FIG. 4 is an operation waveform diagram in PWM control of the DC-DC converter. In FIG. 4, in the first half period ton of the cycle T1, the gate drive signal Vgh becomes L level, the first switch M11 becomes conductive, and the high side output current IoutH flows. At that time, the gate drive signal Vgl is at L level, and the second switch M12 becomes non-conductive. In the first half period ton, when the first switch M1 is turned on, the voltage VLX at the connection point LX rises to near the input voltage Vin, and the high-side output current IoutH overcomes the resistance of the inductor Lout and gradually increases. The point voltage VLX gradually decreases. The high-side output current IoutH is the same as the inductor current ILX, increases during the first half period ton, and the inductor Lout stores electromagnetic energy. In response to this, the output voltage Vo and the feedback voltage Vfb also rise.

  Next, in the second half period toff of the cycle T1, the gate drive signal Vgh becomes H level, the first switch M11 becomes non-conductive, the gate drive signal Vgl becomes H level, and the second switch M12 becomes conductive. When the second switch M12 is turned on, the inductor Lout keeps flowing the inductor current ILX due to the regenerative operation by the accumulated electromagnetic energy. Flowing. Therefore, the connection point voltage VLX once becomes a negative potential as shown in the figure. Then, the inductor Lout releases electromagnetic energy by the regenerative operation, the inductor current ILX gradually decreases, and accordingly, the connection point voltage VLX increases from a negative voltage toward 0 V = Vss. As the inductor current ILX decreases, the output voltage Vo and the feedback voltage Vfb also decrease.

  As described above, in the first half period ton of the cycle T1, the first switch M11 is turned on to supply charges from the input voltage Vin to the output terminal OUT, the output voltage Vo rises, and the feedback voltage Vfb also rises. On the other hand, in the second half period toff, the second switch M12 conducts and charges are supplied to the output terminal OUT by the regenerative operation of the inductor LOUT, so that the output voltage Vo decreases and the feedback voltage Vfb also decreases.

  The switching control circuit 20 receives the error voltage Ver, which is the output of the error amplifier A1, and variably controls the duty ratio of the first half period ton of the cycle T1 indirectly based on the potential of the feedback voltage Vfb corresponding to the output voltage Vo. PWM control is performed. In this PWM control, when the load current Io of the load circuit 10 increases, the switching control circuit 20 relatively decreases the feedback voltage Vfb, so the period ton during which the first switch M11 is turned on is lengthened, and the inductor Lout The amount of charge (energy) supplied to the is increased. Conversely, when the load current Io decreases, the feedback voltage Vfb relatively increases, so the period ton during which the first switch M11 is turned on is shortened, and the amount of charge (energy) supplied to the inductor Lout is reduced. . This PWM control keeps the output voltage Vo at the specified potential. Further, the current ILX flowing through the inductor Lout is always a positive current from the connection point toward the output terminal OUT.

  Next, PFM control using a DC-DC converter is described.

  As indicated by a broken line in FIG. 4, when the load circuit 10 enters a light load state such as a sleep state, the output voltage Vo or the feedback voltage Vfb rises to a higher potential by turning on the first switch M11. Therefore, PFM control is performed in which the first and second switches M11 and M12 are turned on and off in the cycle T1, and the PFM control is turned on and off at a frequency corresponding to the magnitude of the load.

  FIG. 5 is a diagram illustrating the PFM control of the DC-DC converter and the operation of the pseudo load current generation circuit in the present embodiment. The horizontal direction of FIG. 5 is the time axis t, and shows the voltage VLX at the connection point LX, the output voltage Vo (corresponding to the feedback voltage Vfb), the pulse detection signal Vp, the reset signal Vrst, and the pseudo load current Ib. Has been. Further, the leakage current ILEAK of the first switch M11 is small (ILEAK <Ia + Io) before time t5, and the leakage current ILEAK of the first switch M11 is large (ILEAK> Ia + after time t5). Io) state.

  The basic operation in PFM control is as follows. The switching control circuit 20 detects a light load state by monitoring the magnitude of the high side current IoutH of the first switch M11 and enters the PFM control mode. In FIG. 2, the output voltage Vo is resistance-divided by feedback resistors R11 and R12 and input to the error amplifier A1 as the feedback voltage Vfb. When the output voltage Vo decreases, the output Ver of the error amplifier A1 increases. When the output Ver becomes equal to or higher than the second reference voltage Vref2, the output VB of the comparator A2 becomes H level. In response to this output VB = H, the switching control circuit 20 outputs gate drive signals Vgh and Vgl that alternately turn on the output transistors M11 and M12, turns on the output transistor M11, and turns off the output transistor M11. Burst control to turn off M11 and turn on M12. Thus, at time t1, the output voltage Vo rises due to the output transistor M11 being turned on. Before and after time t1, the node voltage VLX becomes a positive pulse when the output transistor M11 is turned on and becomes a negative pulse when the output transistor M12 is turned on. The positive pulse and the negative pulse of the connection point voltage VLX are burst pulses.

  As a result of the increase in the output voltage Vo due to the burst control, the output Ver of the error amplifier A1 decreases, and when the output Ver becomes lower than the second reference voltage Vref2, the comparator A2 sets the output VB to the L level. In response to this, the switching control circuit 20 stops the burst control and enters a pause state in which both the output transistors M11 and M12 are turned off. In the rest state, the electric charge stored in the smoothing capacitor Co is consumed by the load current Io and the feedback current Ia, and the output voltage Vo decreases. When the output voltage Vo falls below a certain threshold voltage Vth, the output VB of the comparator A2 becomes H level, and the switching control circuit 20 executes burst control again.

  As described above, in the PFM control at light load, the switching control circuit 20 repeats the burst control and the resting state. Then, as the load current Io + Ia increases, the rate of decrease of the output voltage Vo in the resting state increases, so that the burst control is repeated at a frequency corresponding to the load current Io + Ia. That is, the larger the load current, the higher the burst control frequency, and the smaller the load current, the lower the burst control frequency.

  Next, the operation when the off-leakage current ILEAK of the output voltage M11 as the first switch rises due to a high temperature or the like will be described. When the mode signal MODE from the switching control circuit 20 indicates the PFM control mode, the burst pulse detection circuit 23 of the pseudo load current generation circuit 22 is connected to the connection point LX of the first and second switches M11 and M12. Monitor burst pulses. The burst pulse detection circuit 23 detects a burst pulse at times t1 and t3 in FIG. 5, and sets the pulse detection signal Vp to the H level. Further, the reset signal Vrst is input to the burst pulse detection circuit 23 at a constant cycle T10, and when the pulse detection signal Vp is at H level, it is reset to L level (time t2, t4). This reset operation requires a predetermined delay time from the rising edge of the reset signal Vrst.

  Here, the off-leakage current ILEAK of the output transistor M11 rises after time t5, and if ILEAK> Io + Ia, the supply voltage becomes excessive and the output voltage Vo rises even if the quiescent state is entered (A in the figure). ). At time t6, in response to the second reset signal Vrst1 having the same timing as the reset signal Vrst, the control unit 26 in the current control circuit 24 detects that the pulse detection signal Vp is not at the H level. Then, the gate control signal G20 is set to H level to turn on the current source transistor M20, and the pseudo load current Ib is set to I1. That is, at time t4, the pulse detection signal Vp is reset to L level, but at time t6 after period T10, the pulse detection signal Vp remains at L level, so burst control has occurred during period T10. Not detected. At time t6, the pseudo load current Ib becomes the current I1 of the current source M20.

  Further, the output voltage Vo cannot be sufficiently reduced by time t7 after the next cycle T10, and the control unit 26 in the current control circuit 24 pulses that burst control has not occurred in response to the reset signal Vrst2. When detection is performed at the L level of the detection signal Vp (B in the figure), the gate control signal G21 is set to H level, the current source transistor M21 is turned on, and the pseudo load current Ib is further increased by I1. As a result, Ib = 2 * I1. As the pseudo load current Ib increases, the output voltage Vo decreases to the threshold level Vth, whereby the output VB of the comparator A2 becomes VH = H. In response to this, the switching control circuit 20 performs burst control. This burst pulse is detected by the burst pulse detection circuit 23, and the pulse detection signal Vp becomes H level.

  Although the burst burst output rises, the load Ib = 2 * I1 flows from the output, so the output voltage gradually decreases when entering the resting state. At time t9 after the next cycle T10, the control unit 26 in the current control circuit 24 detects the H level of the pulse detection signal Vp, sets the gate control signal G21 to L level, and turns off the current source transistor M21. As a result, the pseudo load current Ib decreases by the current I1, and the output voltage Vo increases again. In the state of ILEAK> Ia + Io, the control from t6 to t9 is automatically repeated, and the output voltage Vo is kept almost constant.

  As described above, during the PFM control mode, the pseudo load current generation circuit 22 according to the present embodiment variably controls the current amount of the pseudo load current Ib according to the degree of increase in the output voltage Vo, so that an optimal current value is obtained. Automatically set to Therefore, the pseudo load current Ib customized to the off-leakage characteristic of the output transistor M11 is generated, and waste of current consumption can be avoided.

  Standards for the period T10 of the reset signal Vrst that monitors the burst pulse, the pseudo load current Ib, and its minimum unit current I1 are the magnitude of the off-leakage current of the output transistor M11 and how much the output voltage Vo should be suppressed within mV It is decided from.

[Modification]
In the modification, the period T10 for monitoring the generation of burst pulses is set to be equal to or less than the period corresponding to the maximum audible frequency (20 kHz). According to the PFM control in the light load state described above, a burst pulse is generated at a frequency corresponding to the decreasing speed of the output voltage Vo. Therefore, when the load is very low, the rate of decrease of the output voltage Vo is reduced and the burst pulse generation frequency is also reduced. When this burst frequency is about 20 kHz or less, which is the maximum value of human audible frequency, the ripple at the time of burst becomes voice noise, which may cause a problem as system noise.

  Therefore, in the modification, the cycle T10 for monitoring the burst pulse is set to 1/20 kHz = 50 μsec or less. As a result, the pseudo load current Ib is generated at a frequency higher than the maximum audible frequency of 20 kHz and the output voltage Vo is lowered, so that the burst control is forcibly performed and the burst frequency can be set to 20 kHz or higher. . As a result, the frequency of voice noise at the time of bursting becomes high and can be made inaudible to human ears.

  Furthermore, the pseudo load current generation circuit 22 of the present embodiment can be operated not only in the PFM control mode. For example, when the load circuit 10 is switched from a heavy load state to a light load state, the control circuit shifts from PWM control to PFM control via a feedback circuit to put the output transistor into a resting state and try to suppress an increase in the output voltage Vo. During this quiescent state, the pseudo load current generation circuit 23 cannot detect the burst pulse and generates the pseudo load current Ib. Therefore, the output voltage Vo can be decreased temporarily, and the output voltage Vo increases. Can be reduced.

  The above embodiment is summarized as follows.

(Appendix 1)
In a DC-DC converter having an input terminal to which an input voltage is supplied and an output terminal to which an output voltage is output and connected to a load circuit,
First and second switches connected in series between the input terminal and a reference power source;
An inductor provided between a connection node of the first and second switches and the output terminal;
A smoothing capacitor connected to the output terminal;
A switching control circuit for performing burst control for turning on the second switch after turning on the first switch when the output voltage drops to a reference voltage;
A DC-DC converter having a pseudo load current generation circuit that monitors the burst control and causes a pseudo load current to flow from the output terminal when the burst control is not performed for a predetermined period.

(Appendix 2)
In Appendix 1,
The pseudo load current generation circuit is a DC-DC converter that monitors the burst control at a monitoring timing of a predetermined cycle and causes a pseudo load current to flow from the output terminal when the burst control does not occur during the monitoring timing.

(Appendix 3)
In Appendix 2,
The pseudo load current generation circuit increases the pseudo load current every time it detects that the burst control does not occur during the monitoring timing, and detects that the burst control occurs during the monitoring timing. A DC-DC converter that reduces the pseudo load current each time.

(Appendix 4)
In any one of appendices 1 to 3,
The pseudo load current generation circuit is a DC-DC converter that monitors the burst pulse by the burst control at the connection node of the first and second switches and detects the occurrence of the burst control.

(Appendix 5)
In Appendix 1,
The switching control circuit performs on / off control of the first and second switches by pulse width modulation when the load of the load circuit is in the first load state, and the load of the load circuit is the first load. In the case of the second load state lighter than the load state, the on / off control of the first and second switches is performed by pulse frequency modulation,
The DC-DC converter, wherein the pseudo load current generation circuit allows the pseudo load current to flow while being controlled by the pulse frequency modulation.

(Appendix 6)
In Appendix 2,
The DC-DC converter characterized in that the predetermined period is equal to or less than a period corresponding to the maximum audible frequency.

(Appendix 7)
An input terminal to which an input voltage is supplied; an output terminal to which an output voltage is output and connected to a load circuit; first and second switches connected in series between the input terminal and ground; In a control unit of a DC-DC converter having an inductor provided between a connection node of first and second switches and the output terminal, and a smoothing capacitor connected to the output terminal,
A switching control circuit for performing burst control for turning on the second switch after turning on the first switch when the output voltage drops to a reference voltage;
A control unit for a DC-DC converter, comprising: a pseudo load current generation circuit that monitors the burst control and causes a pseudo load current to flow from the output terminal when the burst control is not performed for a predetermined period.

(Appendix 8)
In Appendix 7,
The pseudo load current generation circuit monitors the burst control at a monitoring timing of a predetermined cycle, and when the burst control does not occur during the monitoring timing, the pseudo load current generating circuit control unit.

(Appendix 9)
In Appendix 8,
The pseudo load current generation circuit increases the pseudo load current each time it detects that the burst control does not occur during the monitoring timing, and detects that the burst control occurs during the monitoring timing. A control unit for a DC-DC converter that reduces the pseudo load current each time.

Vin: Input voltage IN: Input terminal
Vo: Output voltage OUT: Output terminal
M11, M12: 1st and 2nd switch LX: Connection terminal
Lout: inductor Co: smoothing capacitor 10: load circuit Io: load current 20: switching control circuit 22: pseudo load current generation circuit
Ib: pseudo load current Vss: ground, reference power supply

Claims (6)

In a DC-DC converter having an input terminal to which an input voltage is supplied and an output terminal to which an output voltage is output and connected to a load circuit,
First and second switches connected in series between the input terminal and ground;
An inductor provided between a connection node of the first and second switches and the output terminal;
A smoothing capacitor connected to the output terminal;
A switching control circuit for performing burst control for turning on the second switch after turning on the first switch when the output voltage drops to a reference voltage;
A DC-DC converter having a pseudo load current generation circuit that monitors the burst control and causes a pseudo load current to flow from the output terminal when the burst control is not performed for a predetermined period. In claim 1,
The pseudo load current generation circuit is a DC-DC converter that monitors the burst control at a monitoring timing of a predetermined cycle and causes a pseudo load current to flow from the output terminal when the burst control does not occur during the monitoring timing. In claim 2,
The pseudo load current generation circuit increases the pseudo load current every time it detects that the burst control does not occur during the monitoring timing, and detects that the burst control occurs during the monitoring timing. A DC-DC converter that reduces the pseudo load current each time. In claim 1,
The switching control circuit performs on / off control of the first and second switches by pulse width modulation when the load of the load circuit is in the first load state, and the load of the load circuit is the first load. In the case of the second load state lighter than the load state, the on / off control of the first and second switches is performed by pulse frequency modulation,
The DC-DC converter, wherein the pseudo load current generation circuit allows the pseudo load current to flow while being controlled by the pulse frequency modulation. In claim 2,
The DC-DC converter characterized in that the predetermined period is equal to or less than a period corresponding to the maximum audible frequency. An input terminal to which an input voltage is supplied; an output terminal to which an output voltage is output and connected to a load circuit; first and second switches connected in series between the input terminal and ground; In a control unit of a DC-DC converter having an inductor provided between a connection node of first and second switches and the output terminal, and a smoothing capacitor connected to the output terminal,
A switching control circuit for performing burst control for turning on the second switch after turning on the first switch when the output voltage drops to a reference voltage;
A control unit for a DC-DC converter, comprising: a pseudo load current generation circuit that monitors the burst control and causes a pseudo load current to flow from the output terminal when the burst control is not performed for a predetermined period.

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