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JP2010245413A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP2010245413A
JP2010245413A JP2009094532A JP2009094532A JP2010245413A JP 2010245413 A JP2010245413 A JP 2010245413A JP 2009094532 A JP2009094532 A JP 2009094532A JP 2009094532 A JP2009094532 A JP 2009094532A JP 2010245413 A JP2010245413 A JP 2010245413A
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circuit
semiconductor integrated
circuit block
integrated circuit
power supply
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Osamu Fujii
治 藤井
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that is capable of controlling power consumption while suppressing expansion of SOC chip area. <P>SOLUTION: The semiconductor integrated circuit device includes first and second circuit blocks in which power supply wires are separated from each other, an SOC chip 12 wherein the first and second circuit blocks are formed, and SW chips 16a to 16c, in each of which a regulator circuit is formed for controlling supply of power source to the second circuit block based on the control signal from the first circuit block. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体集積回路装置に係り、特に、大規模なＳＯＣ（System On Chip）に関する。   The present invention relates to a semiconductor integrated circuit device, and more particularly to a large-scale SOC (System On Chip).

近年、半導体製造プロセスの微細化の進展に伴って、半導体集積回路装置はより大規模化し、システム全体を１つの半導体チップに集積したＳＯＣが開発されている。しかし、微細化プロセスを使用した半導体チップでは回路素子の耐圧が低下する傾向にあり、このため、降圧型レギュレータ回路を別チップに形成し、これをＳＯＣチップと同じパッケージに封入する方法（例えば、「特許文献１」を参照。）が考えられている。   In recent years, with the progress of miniaturization of semiconductor manufacturing processes, semiconductor integrated circuit devices have become larger in scale, and SOCs in which the entire system is integrated on one semiconductor chip have been developed. However, in a semiconductor chip using a miniaturization process, the withstand voltage of the circuit element tends to decrease. Therefore, a method of forming a step-down regulator circuit in another chip and encapsulating it in the same package as the SOC chip (for example, "See Patent Document 1").

一方、微細化の進展、ＳＯＣの大規模化とトレードオフの関係でスタンバイ電力（待機電力）の増加が顕著と成ってきている。このスタンバイ電力を抑制するため、回路全体をいくつかの回路ブロックに分割し、ＳＯＣの動作状況に応じて不要な回路ブロックへの電源供給を遮断する方法が考えられる。   On the other hand, an increase in standby power (standby power) has become conspicuous due to the trade-off between the progress of miniaturization and the increase in the scale of SOC. In order to suppress this standby power, a method is considered in which the entire circuit is divided into several circuit blocks, and power supply to unnecessary circuit blocks is cut off according to the operating state of the SOC.

しかしながら、従来の半導体集積回路装置でこのような分割を行うためには、ＳＯＣチップ内に回路ブロックごとに制御可能な専用電源回路を形成しなければならず、各専用電源回路の分だけＳＯＣチップの面積が増加し、コストが増加してしまうという問題があった。また、最先端の微細化プロセスを使用したＳＯＣチップの面積を抑制するためにこれら専用電源をパッケージ外部から供給する場合には、回路ブロックごとに専用電源端子が必要となり、パッケージの総端子数が増加し結果的にコストの増大につながるという問題があった。   However, in order to perform such division in the conventional semiconductor integrated circuit device, it is necessary to form a dedicated power supply circuit that can be controlled for each circuit block in the SOC chip, and the SOC chip for each dedicated power supply circuit. There is a problem that the area of the device increases and the cost increases. In addition, when these dedicated power supplies are supplied from the outside of the package in order to reduce the area of the SOC chip using the most advanced miniaturization process, a dedicated power supply terminal is required for each circuit block, and the total number of terminals of the package is There is a problem that the cost increases as a result.

特開２００６−２６１６０３号公報JP 2006-261603 A

本発明は、ＳＯＣチップの面積増加を抑えつつ消費電力を抑制することができる半導体集積回路装置を提供する。   The present invention provides a semiconductor integrated circuit device capable of suppressing power consumption while suppressing an increase in the area of an SOC chip.

本発明の一態様によれば、互いに電源配線が分離された第１および第２の回路ブロックと、前記第１および第２の回路ブロックが形成されている第１の半導体チップと、前記第１の回路ブロックからの制御信号に基づいて、前記第２の回路ブロックへの電源供給を制御するレギュレータ回路が形成されている第２の半導体チップを有することを特徴とする半導体集積回路装置が提供される。   According to one aspect of the present invention, the first and second circuit blocks in which the power supply wirings are separated from each other, the first semiconductor chip on which the first and second circuit blocks are formed, and the first There is provided a semiconductor integrated circuit device comprising a second semiconductor chip on which a regulator circuit for controlling power supply to the second circuit block is formed based on a control signal from the circuit block. The

本発明によれば、ＳＯＣチップの面積増加を抑えつつ消費電力を抑制することができるので、製造コストを抑えつつ高品質の半導体集積回路装置を実現することができる。   According to the present invention, power consumption can be suppressed while suppressing an increase in the area of the SOC chip, so that a high-quality semiconductor integrated circuit device can be realized while suppressing manufacturing costs.

本発明の実施例に係る半導体集積回路装置におけるＭＣＰ（Multi Chip Package）の構造を示す断面図。Sectional drawing which shows the structure of MCP (Multi Chip Package) in the semiconductor integrated circuit device based on the Example of this invention. 本発明の実施例に係る半導体集積回路装置の一例を示す回路ブロック図。1 is a circuit block diagram showing an example of a semiconductor integrated circuit device according to an embodiment of the present invention. 本発明の実施例に係る半導体集積回路装置におけるレギュレータ回路の一例を示す回路図。1 is a circuit diagram showing an example of a regulator circuit in a semiconductor integrated circuit device according to an embodiment of the present invention. 本発明の実施例に係る半導体集積回路装置におけるレギュレータ回路の別の一例を示す回路図。FIG. 5 is a circuit diagram showing another example of a regulator circuit in the semiconductor integrated circuit device according to the embodiment of the present invention.

以下、図面を参照しながら、本発明の実施の形態を説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の実施例に係る半導体集積回路装置におけるＭＣＰ（Multi Chip Package）の構造を示す断面図である。ここでは、一例として、レギュレータ回路が搭載された３つの半導体チップ（以下、「ＳＷチップ」という。）をＳＯＣチップ上に表面実装したＢＧＡ（Ball Grid Array）パッケージを示した。   FIG. 1 is a cross-sectional view showing the structure of an MCP (Multi Chip Package) in a semiconductor integrated circuit device according to an embodiment of the present invention. Here, as an example, a BGA (Ball Grid Array) package in which three semiconductor chips (hereinafter referred to as “SW chips”) mounted with a regulator circuit are mounted on an SOC chip is shown.

本発明の実施例に係る半導体集積回路装置は、プリント基板１１、ＳＯＣチップ１２、およびＳＷチップ１６ａ〜１６ｃを備えている。   The semiconductor integrated circuit device according to the embodiment of the present invention includes a printed circuit board 11, an SOC chip 12, and SW chips 16a to 16c.

プリント基板１１の片面には外部との接続に用いる複数の半田ボール１３が接着され、プリント基板１１を挟んで半田ボール１３と対向する面にはＳＯＣチップ１２が接着され、半田ボール１３とＳＯＣチップ１２はボンディングワイヤ１４とプリント基板１１中に形成されたスルー配線とで電気的に接続され、ＳＷチップ１６ａ〜１６ｃはＳＯＣチップ１２上にナノボール１５を挟んで対向して接着され、ＳＷチップ１６ａ〜１６ｃとＳＯＣチップ１２はそれぞれ複数のナノボール１５を介して電気的に接続され、ＳＯＣチップ１２、ＳＷチップ１６ａ〜１６ｃ、ボンディングワイヤ１４、およびナノボール１５はモールド樹脂１７に封入されている。   A plurality of solder balls 13 used for connection to the outside are bonded to one side of the printed circuit board 11, and an SOC chip 12 is bonded to a surface facing the solder balls 13 with the printed circuit board 11 interposed therebetween. The solder ball 13 and the SOC chip 12 is electrically connected by a bonding wire 14 and through wiring formed in the printed circuit board 11, and the SW chips 16a to 16c are bonded to the SOC chip 12 so as to face each other with the nanoball 15 interposed therebetween. 16c and the SOC chip 12 are electrically connected to each other via a plurality of nanoballs 15, and the SOC chip 12, SW chips 16a to 16c, the bonding wire 14, and the nanoball 15 are sealed in a mold resin 17.

ＳＯＣチップ１２には電源配線が互いに分離された複数の回路ブロックが形成され、それぞれの回路ブロックには、ＳＷチップ１６ａ〜１６ｃのレギュレータ回路から供給される電源、または、外部から供給される電源が接続されている。   The SOC chip 12 is formed with a plurality of circuit blocks in which power supply lines are separated from each other. Each circuit block is supplied with power supplied from a regulator circuit of the SW chips 16a to 16c or power supplied from the outside. It is connected.

ＳＷチップ１６ａ〜１６ｃは、それぞれ、ＳＯＣチップ１２上の対応する回路ブロックに合わせて必要な定電圧を供給するレギュレータ回路を搭載し、制御信号に基づいて対応する回路ブロックに対して電源の供給を停止したり複数の異なる電源電圧を切り替えて供給したりすることができる。   Each of the SW chips 16a to 16c includes a regulator circuit that supplies a necessary constant voltage in accordance with the corresponding circuit block on the SOC chip 12, and supplies power to the corresponding circuit block based on the control signal. It can be stopped or supplied with a plurality of different power supply voltages.

また、ＳＷチップ１６ａ〜１６ｃには、ＳＯＣチップ１２より緩いデザインルールが用いられている。これにより、動作時の消費電流が大きくかつ比較的高耐圧が要求されるＳＷチップ１６ａ〜１６ｃを安価に製造することができる。   Further, looser design rules than the SOC chip 12 are used for the SW chips 16a to 16c. As a result, the SW chips 16a to 16c that consume a large amount of current during operation and require a relatively high breakdown voltage can be manufactured at low cost.

図２は、本発明の実施例に係る半導体集積回路装置を示す回路ブロック図である。ここでは、一例として、互いに電源配線が分離された３つの回路ブロックとそれらにかかわる２つのレギュレータ回路を示した。   FIG. 2 is a circuit block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. Here, as an example, three circuit blocks in which power supply lines are separated from each other and two regulator circuits related to them are shown.

本発明の実施例に係る半導体集積回路装置は、ＳＯＣチップ１２上に回路ブロック２１〜２３、およびアイソレーション回路２４ａ〜２４ｄを備え、ＳＷチップ上にレギュレータ回路２５、２６を備えている。   The semiconductor integrated circuit device according to the embodiment of the present invention includes circuit blocks 21 to 23 and isolation circuits 24a to 24d on the SOC chip 12, and regulator circuits 25 and 26 on the SW chip.

回路ブロック２１の出力ＯＵＴはアイソレーション回路２４ａの入力に接続され、回路ブロック２１の入力ＩＮにはアイソレーション回路２４ｂの出力が接続され、回路ブロック２１の電源入力ＰＳには半田ボール１３からなる電源端子２７が接続され、回路ブロック２１の制御出力/ＣＥ２はレギュレータ回路２５の制御入力に接続され、回路ブロック２１の制御出力/ＣＥ３はレギュレータ回路２６の第１の制御入力に接続され、回路ブロック２１の制御出力ＳＥＬはレギュレータ回路２６の第２の制御入力に接続され、レギュレータ回路２５および２６の入力には電源端子２７が接続されている。   The output OUT of the circuit block 21 is connected to the input of the isolation circuit 24 a, the output of the isolation circuit 24 b is connected to the input IN of the circuit block 21, and the power supply input PS of the circuit block 21 is a power supply composed of the solder balls 13. The terminal 27 is connected, the control output / CE2 of the circuit block 21 is connected to the control input of the regulator circuit 25, the control output / CE3 of the circuit block 21 is connected to the first control input of the regulator circuit 26, and the circuit block 21 The control output SEL is connected to the second control input of the regulator circuit 26, and the power supply terminal 27 is connected to the inputs of the regulator circuits 25 and 26.

回路ブロック２２の出力ＯＵＴ１はアイソレーション回路２４ｂの入力に接続され、回路ブロック２２の入力ＩＮ１にはアイソレーション回路２４ａの出力が接続され、回路ブロック２２の出力ＯＵＴ２はアイソレーション回路２４ｃの入力に接続され、回路ブロック２２の入力ＩＮ２にはアイソレーション回路２４ｄの出力が接続され、回路ブロック２２の電源入力ＰＳにはレギュレータ回路２５の出力が接続されている。   The output OUT1 of the circuit block 22 is connected to the input of the isolation circuit 24b, the output of the isolation circuit 24a is connected to the input IN1 of the circuit block 22, and the output OUT2 of the circuit block 22 is connected to the input of the isolation circuit 24c. The output of the isolation circuit 24d is connected to the input IN2 of the circuit block 22, and the output of the regulator circuit 25 is connected to the power input PS of the circuit block 22.

回路ブロック２３の出力ＯＵＴはアイソレーション回路２４ｄの入力に接続され、回路ブロック２３の入力ＩＮにはアイソレーション回路２４ｃの出力が接続され、回路ブロック２３の電源入力ＰＳにはレギュレータ回路２６の出力が接続されている。   The output OUT of the circuit block 23 is connected to the input of the isolation circuit 24d, the output of the isolation circuit 24c is connected to the input IN of the circuit block 23, and the output of the regulator circuit 26 is connected to the power input PS of the circuit block 23. It is connected.

回路ブロック２１は、電源端子２７から供給される外部電源電圧（例えば、１．２Ｖ。以下、「Ｖｄｄ」という。）で動作し、ＳＯＣの動作状態に応じてレギュレータ回路２５および２６を制御する機能を備えている。   The circuit block 21 operates with an external power supply voltage (for example, 1.2 V, hereinafter referred to as “Vdd”) supplied from the power supply terminal 27, and controls the regulator circuits 25 and 26 according to the operating state of the SOC. It has.

すなわち、回路ブロック２１は、必要に応じて回路ブロック２２または２３への電源供給をオン/オフする制御信号（/ＣＥ２、/ＣＥ３）を生成する。また、回路ブロック２１は、回路ブロック２３の動作状態に応じて高い電圧（例えば、１．２Ｖ。：高速動作モード）、または、低い電圧（例えば、０．８Ｖ。：低速動作モードもしくは待機モード）を選択する制御信号ＳＥＬを生成する。   That is, the circuit block 21 generates control signals (/ CE2, / CE3) for turning on / off the power supply to the circuit block 22 or 23 as necessary. The circuit block 21 has a high voltage (for example, 1.2 V .: high-speed operation mode) or a low voltage (for example, 0.8 V .: low-speed operation mode or standby mode) according to the operation state of the circuit block 23. A control signal SEL for selecting is generated.

レギュレータ回路２５〔以下、「ＳＷ_ＴｙｐｅＡ」ともいう。〕は、回路ブロック２１からの/ＣＥ２に基づいて、回路ブロック２２への電源供給をオン/オフする。   Regulator circuit 25 [hereinafter also referred to as “SW_Type A”. ] Turns on / off the power supply to the circuit block 22 based on / CE2 from the circuit block 21.

レギュレータ回路２６〔以下、「ＳＷ_ＴｙｐｅＢ」ともいう。〕は、回路ブロック２１からの/ＣＥ３に基づいて回路ブロック２３への電源供給をオン/オフし、さらに、回路ブロック２１からのＳＥＬに基づいて回路ブロック２３への電源電圧〔例えば、１．２Ｖ/０．８Ｖ。）を選択して供給する。   Regulator circuit 26 [hereinafter also referred to as “SW_Type B”. ] Turns on / off the power supply to the circuit block 23 based on / CE3 from the circuit block 21, and further supplies the power supply voltage [for example, 1.2V to the circuit block 23 based on SEL from the circuit block 21]. /0.8V. ) Select and supply.

アイソレーション回路２４ａ〜２４ｄは、回路ブロック２２または２３に電源が供給されていない時に入力ＩＮを固定する機能を備えている。例えば、回路ブロック２２と回路ブロック２１との間にあるアイソレーション回路２４ｂは、回路ブロック２２に電源が供給されていない時に回路ブロック２２から回路ブロック２１へ出力される信号が不定となるため、回路ブロック２１の入力ＩＮを固定する。   The isolation circuits 24a to 24d have a function of fixing the input IN when power is not supplied to the circuit block 22 or 23. For example, the isolation circuit 24b between the circuit block 22 and the circuit block 21 is configured so that a signal output from the circuit block 22 to the circuit block 21 becomes undefined when power is not supplied to the circuit block 22. The input IN of the block 21 is fixed.

図３は、本発明の実施例に係る半導体集積回路装置におけるレギュレータ回路２５（ＳＷ_ＴｙｐｅＡ）の一例を示す回路図である。
本発明の実施例に係る半導体集積回路装置は、定電流源３１、抵抗３２（Ｖｒｅｆ）、制御入力付きのＯＰアンプ３３、およびｐ型ＭＯＳＦＥＴの出力トランジスタ３４を備えている。 FIG. 3 is a circuit diagram showing an example of the regulator circuit 25 (SW_TypeA) in the semiconductor integrated circuit device according to the embodiment of the present invention.
The semiconductor integrated circuit device according to the embodiment of the present invention includes a constant current source 31, a resistor 32 (Vref), an OP amplifier 33 with a control input, and an output transistor 34 of a p-type MOSFET.

定電流源３１の一端はＶｄｄに接続され、定電流源３１の他端は抵抗３２の一端およびＯＰアンプ３３の(−)入力に接続され、抵抗３２の他端は接地電位（以下、「ＧＮＤ」という。）に接続され、ＯＰアンプ３３の制御入力には回路ブロック２１からの/ＣＥ２が接続され、ＯＰアンプ３３の出力は出力トランジスタ３４のゲートに接続され、出力トランジスタ３４のソースおよびバックゲートはＶｄｄに接続され、出力トランジスタ３４のドレインはＯＰアンプ３３の(＋)入力に接続されるとともにレギュレータ回路２５の出力Ｖｏｕｔとして回路ブロック２２の電源入力ＰＳに接続されている。   One end of the constant current source 31 is connected to Vdd, the other end of the constant current source 31 is connected to one end of the resistor 32 and the (−) input of the OP amplifier 33, and the other end of the resistor 32 is connected to the ground potential (hereinafter referred to as “GND”). The control input of the OP amplifier 33 is connected to / CE2 from the circuit block 21, the output of the OP amplifier 33 is connected to the gate of the output transistor 34, and the source and back gate of the output transistor 34 are connected. Is connected to Vdd, the drain of the output transistor 34 is connected to the (+) input of the OP amplifier 33 and the output Vout of the regulator circuit 25 is connected to the power supply input PS of the circuit block 22.

レギュレータ回路２５は、図３の表に示したように、/ＣＥ２が“Ｌｏｗ”である時にＶｒｅｆ基準電圧に応じた電圧をＶｏｕｔに出力し、/ＣＥ２が“Ｈｉｇｈ”である時にＶｏｕｔ出力をオフする。   As shown in the table of FIG. 3, the regulator circuit 25 outputs a voltage corresponding to the Vref reference voltage to Vout when / CE2 is “Low”, and turns off the Vout output when / CE2 is “High”. To do.

図４は、本発明の実施例に係る半導体集積回路装置におけるレギュレータ回路２６（ＳＷ_ＴｙｐｅＢ）の一例を示す回路図である。
本発明の実施例に係る半導体集積回路装置は、定電流源４１、抵抗４２ａ（Ｖｒｅｆ１）および抵抗４２ｂ（Ｖｒｅｆ２）、制御入力付きのＯＰアンプ４３、ｐ型ＭＯＳＦＥＴの出力トランジスタ４４、および選択スイッチ４５を備えている。 FIG. 4 is a circuit diagram showing an example of the regulator circuit 26 (SW_TypeB) in the semiconductor integrated circuit device according to the embodiment of the present invention.
A semiconductor integrated circuit device according to an embodiment of the present invention includes a constant current source 41, a resistor 42a (Vref1) and a resistor 42b (Vref2), an OP amplifier 43 with a control input, an output transistor 44 of a p-type MOSFET, and a selection switch 45. It has.

定電流源４１の一端はＶｄｄに接続され、定電流源４１の他端は選択スイッチ４５の入力およびＯＰアンプ４３の(−)入力に接続され、選択スイッチ４５の制御入力には回路ブロック２１からのＳＥＬが接続され、選択スイッチ４５の一方の出力は抵抗４２ａの一端に接続され、選択スイッチ４５の他方の出力は抵抗４２ｂの一端に接続され、抵抗４２ａの他端および抵抗４２ｂの他端はＧＮＤに接続され、ＯＰアンプ４３の制御入力には回路ブロック２１からの/ＣＥ３が接続され、ＯＰアンプ４３の出力は出力トランジスタ４４のゲートに接続され、出力トランジスタ４４のソースおよびバックゲートはＶｄｄに接続され、出力トランジスタ４４のドレインはＯＰアンプ４３の(＋)入力に接続されるとともにレギュレータ回路２６の出力Ｖｏｕｔとして回路ブロック２３の電源入力ＰＳに接続されている。   One end of the constant current source 41 is connected to Vdd, the other end of the constant current source 41 is connected to the input of the selection switch 45 and the (−) input of the OP amplifier 43, and the control input of the selection switch 45 is supplied from the circuit block 21. SEL, one output of the selection switch 45 is connected to one end of the resistor 42a, the other output of the selection switch 45 is connected to one end of the resistor 42b, and the other end of the resistor 42a and the other end of the resistor 42b are connected to each other. Connected to GND, / CE3 from the circuit block 21 is connected to the control input of the OP amplifier 43, the output of the OP amplifier 43 is connected to the gate of the output transistor 44, and the source and back gate of the output transistor 44 are set to Vdd. The drain of the output transistor 44 is connected to the (+) input of the OP amplifier 43 and the output V of the regulator circuit 26. It is connected to the power input PS of the circuit block 23 as ut.

レギュレータ回路２６は、図４の表に示したように、/ＣＥ３が“Ｌｏｗ”である時にＶｒｅｆ１またはＶｒｅｆ２基準電圧に応じた電圧をＶｏｕｔに出力し、/ＣＥ３が“Ｈｉｇｈ”である時にＶｏｕｔ出力をオフする。   As shown in the table of FIG. 4, the regulator circuit 26 outputs a voltage corresponding to the Vref1 or Vref2 reference voltage to Vout when / CE3 is “Low”, and outputs Vout when / CE3 is “High”. Turn off.

また、レギュレータ回路２６は、/ＣＥ３が“Ｌｏｗ”でかつＳＥＬが“Ｌｏｗ”である時にＶｒｅｆ１基準電圧に応じた電圧をＶｏｕｔに出力し、/ＣＥ３が“Ｌｏｗ”でかつＳＥＬが“Ｈｉｇｈ”である時にＶｒｅｆ２基準電圧に応じた電圧をＶｏｕｔに出力する。   The regulator circuit 26 outputs a voltage corresponding to the Vref1 reference voltage to Vout when / CE3 is “Low” and SEL is “Low”, and / CE3 is “Low” and SEL is “High”. At a certain time, a voltage corresponding to the Vref2 reference voltage is output to Vout.

上記実施例によれば、ＳＯＣチップ１２の表面にレギュレータ回路内蔵のＳＷチップ１６ａ〜１６ｃを表面実装（ＭＣＰ）しているので、ＳＯＣチップ面積およびパッケージ面積を増加させずに各回路ブロック単位で必要に応じて電源をオン/オフすることができ、半導体集積回路装置の低消費電力を実現することができる。   According to the embodiment described above, the regulator chip built-in SW chips 16a to 16c are surface-mounted (MCP) on the surface of the SOC chip 12, so that it is necessary for each circuit block unit without increasing the SOC chip area and the package area. Accordingly, the power supply can be turned on / off in accordance with the power consumption of the semiconductor integrated circuit device.

また、上記実施例によれば、ＳＷチップ１６ａ〜１６ｃはレギュレータ機能を有しているので、単に電源供給のオン/オフだけでなく動作状態に応じて各回路ブロックで必要とする最低限の電圧を制御しながら供給することができ、半導体集積回路装置の低消費電力と高性能を同時に達成することができる。   In addition, according to the above embodiment, since the SW chips 16a to 16c have a regulator function, the minimum voltage required for each circuit block according to the operating state as well as on / off of power supply. Thus, the low power consumption and high performance of the semiconductor integrated circuit device can be achieved at the same time.

さらに、上記実施例によれば、ＳＷチップ１６ａ〜１６ｃの制御はＳＯＣチップ１２の内部で行われるため、パッケージに回路ブロック単位での専用電源端子や専用制御端子が不要となり、端子数を削減することができるので、より小型で安価なパッケージを使用することができる。   Furthermore, according to the above-described embodiment, the SW chips 16a to 16c are controlled inside the SOC chip 12, so that dedicated power supply terminals and dedicated control terminals for each circuit block are not required in the package, and the number of terminals is reduced. Therefore, a smaller and cheaper package can be used.

さらに、上記実施例によれば、付加するＳＷチップ１６ａ〜１６ｃは、ＳＯＣチップ１２と同一の微細プロセスを使う必要が無いので、安価なプロセスでＳＷチップ１６ａ〜１６ｃを製造でき、半導体集積回路装置のコストを抑えることが可能となる。   Furthermore, according to the above embodiment, since the added SW chips 16a to 16c do not need to use the same fine process as the SOC chip 12, the SW chips 16a to 16c can be manufactured by an inexpensive process, and the semiconductor integrated circuit device It becomes possible to hold down the cost.

さらに、上記実施例によれば、ＳＯＣチップ１２の面積増加を抑えつつ消費電力を抑制することができるので、製造コストを抑えつつ高品質の半導体集積回路装置を実現することができる。   Furthermore, according to the above embodiment, power consumption can be suppressed while suppressing an increase in the area of the SOC chip 12, so that a high-quality semiconductor integrated circuit device can be realized while suppressing manufacturing costs.

上述の実施例では、レギュレータ回路２６（ＳＷ_ＴｙｐｅＢ）は、２つの異なる電源電圧を選択的に出力するとしたが、本発明はこれに限られるものではなく、原理的には３以上の電源電圧に対しても適用可能である。   In the above-described embodiment, the regulator circuit 26 (SW_TypeB) selectively outputs two different power supply voltages. However, the present invention is not limited to this, and in principle, for three or more power supply voltages. Is applicable.

また、上述の実施例では、３つのＳＷチップ１６ａ〜１６ｃを用いるとしたが、本発明はこれに限られるものではなく、原理的には１つ以上のＳＷチップに対して適用可能である。   In the above-described embodiment, the three SW chips 16a to 16c are used. However, the present invention is not limited to this, and can be applied to one or more SW chips in principle.

さらに、上述の実施例では、ＳＷチップ１６ａ〜１６ｃはＳＯＣチップ１２上に表面実装するとしたが、本発明はこれに限られるものではなく、一般的なマルチチップパッケージの実装方法に適用することが可能である。   Furthermore, in the above-described embodiment, the SW chips 16a to 16c are surface-mounted on the SOC chip 12, but the present invention is not limited to this, and can be applied to a general multi-chip package mounting method. Is possible.

１１ プリント基板
１２ ＳＯＣチップ
１３ 半田ボール
１４ ボンディングワイヤ
１５ ナノボール
１６ａ〜１６ｃ ＳＷチップ
１７ モールド樹脂
２１〜２３ 回路ブロック
２４ａ〜２４ｄ アイソレーション回路
２５、２６ レギュレータ回路
/ＣＥ２、/ＣＥ３、ＳＥＬ 制御信号 11 Printed circuit board 12 SOC chip 13 Solder ball 14 Bonding wire 15 Nano ball 16a to 16c SW chip 17 Mold resin 21 to 23 Circuit blocks 24a to 24d Isolation circuits 25 and 26 Regulator circuit
/ CE2, / CE3, SEL control signal

Claims (5)

互いに電源配線が分離された第１および第２の回路ブロックと、
前記第１および第２の回路ブロックが形成されている第１の半導体チップと、
前記第１の回路ブロックからの制御信号に基づいて、前記第２の回路ブロックへの電源供給を制御するレギュレータ回路が形成されている第２の半導体チップを有することを特徴とする半導体集積回路装置。 First and second circuit blocks in which power supply lines are separated from each other;
A first semiconductor chip in which the first and second circuit blocks are formed;
A semiconductor integrated circuit device having a second semiconductor chip in which a regulator circuit for controlling power supply to the second circuit block is formed based on a control signal from the first circuit block . 前記レギュレータ回路は、前記制御信号に基づいて前記第２の回路ブロックへの電源供給をオン/オフすることを特徴とする請求項１に記載の半導体集積回路装置。   2. The semiconductor integrated circuit device according to claim 1, wherein the regulator circuit turns on / off power supply to the second circuit block based on the control signal. 前記レギュレータ回路は、前記制御信号に基づいて複数の電源電圧の中から１つを選択し前記第２の回路ブロックへ供給することを特徴とする請求項１に記載の半導体集積回路装置。   2. The semiconductor integrated circuit device according to claim 1, wherein the regulator circuit selects one of a plurality of power supply voltages based on the control signal and supplies the selected one to the second circuit block. 前記第２の半導体チップは、前記第１の半導体チップのデザインルールより緩いデザインルールが用いられていることを特徴とする請求項１に記載の半導体集積回路装置。   2. The semiconductor integrated circuit device according to claim 1, wherein a design rule that is looser than a design rule of the first semiconductor chip is used for the second semiconductor chip. 前記第１および第２の半導体チップがモールド樹脂に封入されていることを特徴とする請求項１に記載の半導体集積回路装置。   2. The semiconductor integrated circuit device according to claim 1, wherein the first and second semiconductor chips are sealed in a mold resin.
JP2009094532A 2009-04-09 2009-04-09 Semiconductor integrated circuit device Pending JP2010245413A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023228811A1 (en) * 2022-05-25 2023-11-30 ヌヴォトンテクノロジージャパン株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023228811A1 (en) * 2022-05-25 2023-11-30 ヌヴォトンテクノロジージャパン株式会社 Semiconductor device

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