JP2010239126A5 - Package substrate and method for manufacturing semiconductor device - Google Patents
Package substrate and method for manufacturing semiconductor device Download PDFInfo
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- JP2010239126A5 JP2010239126A5 JP2010050962A JP2010050962A JP2010239126A5 JP 2010239126 A5 JP2010239126 A5 JP 2010239126A5 JP 2010050962 A JP2010050962 A JP 2010050962A JP 2010050962 A JP2010050962 A JP 2010050962A JP 2010239126 A5 JP2010239126 A5 JP 2010239126A5
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- interposer
- layer
- wiring pattern
- insulating resin
- resin layer
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- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 title claims description 6
- 239000010410 layer Substances 0.000 claims description 44
- 229920005989 resin Polymers 0.000 claims description 21
- 239000011347 resin Substances 0.000 claims description 21
- 239000012790 adhesive layer Substances 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000000945 filler Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 238000010030 laminating Methods 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Description
本発明は、パッケージ基板および半導体装置の製造技術に適用して有効な技術に関するものである。 The present invention relates to a technique effective when applied to a manufacturing technique of a package substrate and a semiconductor device .
本発明の目的は、微細化に対応した半導体チップが実装されるパッケージ基板に関する技術を提供することにある。 An object of the present invention is to provide a technique relating to a package substrate on which the semiconductor chip is Ru are mounted corresponding to the miniaturization.
本発明の一実施形態におけるパッケージ基板は、第１面と前記第１面は反対側の第２面とを有し、前記第１面で半導体チップが実装されるパッケージ基板であって、前記第１面側に設けられた絶縁接着層と、前記絶縁接着層の前記第２面側の面内で接着されたインターポーザと、前記インターポーザの前記第２面側の面および前記絶縁接着層の前記第２面側の面上に、前記インターポーザを埋め込むように形成された絶縁樹脂層と、前記絶縁樹脂層の前記第２面側の面上に、層間絶縁樹脂層および配線層が複数積層して形成されたビルドアップ層と、前記ビルドアップ層の前記第２面側の面上に形成されたソルダレジストと、を備え、前記インターポーザの前記第１面側の面上には保護膜が形成され、前記インターポーザの前記第２面側の面上には配線パターンが形成され、前記保護膜上で接着している前記絶縁接着層が、前記インターポーザよりも大きく延在し、前記絶縁樹脂層には、前記インターポーザの配線パターンおよび前記ビルドアップ層と電気的に接続された配線層が形成され、前記絶縁樹脂層には、フィラーが含有されていることを特徴とする。A package substrate according to an embodiment of the present invention is a package substrate having a first surface and a second surface opposite to the first surface, and a semiconductor chip is mounted on the first surface. An insulating adhesive layer provided on one surface side, an interposer bonded within a surface on the second surface side of the insulating adhesive layer, a surface on the second surface side of the interposer, and the first of the insulating adhesive layer. An insulating resin layer formed so as to embed the interposer on the second surface side, and a plurality of interlayer insulating resin layers and wiring layers are stacked on the second surface side surface of the insulating resin layer. A build-up layer, and a solder resist formed on the second surface side surface of the build-up layer, a protective film is formed on the first surface side surface of the interposer, Surface on the second surface side of the interposer A wiring pattern is formed, and the insulating adhesive layer adhered on the protective film extends larger than the interposer, and the insulating resin layer includes the wiring pattern of the interposer and the build-up layer. An electrically connected wiring layer is formed, and the insulating resin layer contains a filler.
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、微細化に対応した半導体チップが実装されるパッケージ基板に関する技術を提供することができる。 Among the inventions disclosed in the present application will be briefly described effects obtained by typical, it is possible to provide a technique relating to a package substrate on which the semiconductor chip is Ru are mounted corresponding to the miniaturization.
具体的には、絶縁層４４上に例えばポリイミドフィルム、エポキシ樹脂フィルムなどの絶縁性の樹脂フィルムを貼り付け、熱圧着することによって、絶縁層４８を形成する。次いで、例えばレーザ加工などによって、配線パターン４７の一部を露出する貫通孔５３ａ、５３ｂを絶縁層４８に形成する。次いで、絶縁層４８の表面および貫通孔５３ａ、５３ｂの内面にシード層（図示せず）を形成し、そのシード層を給電層としてめっきを行い、絶縁層４８の表面および貫通孔５３ａ、５３ｂの内面に例えば銅からなる導電層を形成する。 Specifically, the insulating layer 48 is formed by attaching an insulating resin film such as a polyimide film or an epoxy resin film on the insulating layer 44 and thermocompression bonding. Next, through holes 53a and 53b exposing part of the wiring pattern 47 are formed in the insulating layer 48 by, for example, laser processing. Then, the surface and the through hole 53a of the insulating layer 48, a seed layer on the inner surface of 53b (not shown) is formed, plating is performed to the seed layer as a power feeding layer, the surface and the through hole 53a of the insulating layer 48, 53b of the A conductive layer made of, for example, copper is formed on the inner surface.
Claims (10)
前記第１面側に設けられた絶縁接着層と、An insulating adhesive layer provided on the first surface side;
前記絶縁接着層の前記第２面側の面内で接着されたインターポーザと、An interposer bonded within the surface on the second surface side of the insulating adhesive layer;
前記インターポーザの前記第２面側の面および前記絶縁接着層の前記第２面側の面上に、前記インターポーザを埋め込むように形成された絶縁樹脂層と、An insulating resin layer formed to embed the interposer on the second surface side surface of the interposer and the second surface side surface of the insulating adhesive layer;
前記絶縁樹脂層の前記第２面側の面上に、層間絶縁樹脂層および配線層が複数積層して形成されたビルドアップ層と、A build-up layer formed by laminating a plurality of interlayer insulating resin layers and wiring layers on the surface on the second surface side of the insulating resin layer;
前記ビルドアップ層の前記第２面側の面上に形成されたソルダレジストと、A solder resist formed on the second surface side of the buildup layer;
を備え、With
前記インターポーザの前記第１面側の面上には保護膜が形成され、A protective film is formed on the surface of the interposer on the first surface side,
前記インターポーザの前記第２面側の面上には配線パターンが形成され、A wiring pattern is formed on the surface on the second surface side of the interposer,
前記保護膜上で接着している前記絶縁接着層が、前記インターポーザよりも大きく延在し、The insulating adhesive layer adhered on the protective film extends larger than the interposer,
前記絶縁樹脂層には、前記インターポーザの配線パターンおよび前記ビルドアップ層と電気的に接続された配線層が形成され、In the insulating resin layer, a wiring layer electrically connected to the wiring pattern of the interposer and the buildup layer is formed,
前記絶縁樹脂層には、フィラーが含有されていることを特徴とするパッケージ基板。A package substrate, wherein the insulating resin layer contains a filler.
前記絶縁樹脂層はその熱膨張係数が、前記層間絶縁樹脂層の熱膨張係数より前記半導体チップの熱膨張係数に近いことを特徴とする。The insulating resin layer has a thermal expansion coefficient closer to that of the semiconductor chip than that of the interlayer insulating resin layer.
前記インターポーザは、シリコン基板から構成されることを特徴とする。The interposer is composed of a silicon substrate.
（ａ）第１面と前記第１面は反対側の第２面とを有し、前記第１面上に第１配線パターンおよび前記第１配線パターンを覆う保護膜が形成され、前記第２面上に第２配線パターンが形成されたインターポーザを準備する工程；
（ｂ）平坦面を有し、前記インターポーザよりも大きく延在する絶縁接着層が前記平坦面上に貼り付けられた支持体を準備する工程；
（ｃ）前記インターポーザの第１面を前記支持体の平坦面に合わせて、前記絶縁接着層と前記保護膜とを接着させて前記支持体上に前記インターポーザを載置する工程；
（ｄ）前記インターポーザを埋め込むように前記支持板の平坦面上にフィラーを含有させた絶縁樹脂層を形成し、前記第２配線パターンと電気的に接続される配線層を前記絶縁樹脂層に形成する工程；
（ｅ）前記絶縁樹脂層に形成された配線層と電気的に接続され、前記絶縁樹脂層上に層間絶縁樹脂層および配線層を複数積層してビルドアップ層を形成する工程；
（ｆ）前記ビルドアップ層上にソルダレジストを形成する工程；
（ｇ）前記（ｆ）工程の後、前記支持板を除去する工程；
（ｈ）前記（ｇ）工程の後、前記第１配線パターンを露出する開口部を前記絶縁接着層および前記保護膜に形成する工程；
（ｉ）前記（ｈ）工程の後、前記第１面上に、露出した前記第１配線パターンと電気的に接続して半導体チップを実装する工程。 A method for manufacturing a semiconductor device comprising the following steps:
(A) The first surface has a second surface opposite to the first surface, a first wiring pattern and a protective film covering the first wiring pattern are formed on the first surface, and the second surface Preparing an interposer having a second wiring pattern formed on the surface ;
(B) have a flat surface, greatly extending the insulating adhesive layer than the interposer is prepared a support attached on the flat surface step;
(C) placing the interposer on the support by aligning the first surface of the interposer with the flat surface of the support, bonding the insulating adhesive layer and the protective film ;
(D) forming an insulating resin layer containing a filler on the flat surface of the support plate so as to embed the interposer, and forming a wiring layer electrically connected to the second wiring pattern on the insulating resin layer ; The step of:
(E) a step of forming a build-up layer by electrically connecting a wiring layer formed on the insulating resin layer and laminating a plurality of interlayer insulating resin layers and wiring layers on the insulating resin layer;
(F) forming a solder resist on the build-up layer;
(G) A step of removing the support plate after the step (f);
(H) After the step (g), a step of forming an opening exposing the first wiring pattern in the insulating adhesive layer and the protective film;
(I) A step of mounting a semiconductor chip electrically connected to the exposed first wiring pattern on the first surface after the step (h) .
前記（ｉ）工程では、前記第１面上に複数の半導体チップを実装し、
前記（ａ）工程では、前記第１配線パターンのうち、前記複数の半導体チップ間の配線を他の配線よりもファインピッチで形成することを特徴とする。 In the manufacturing method of the semiconductor device according to claim 4 ,
In the step (i) , a plurality of semiconductor chips are mounted on the first surface,
In the step (a), the wiring between the plurality of semiconductor chips in the first wiring pattern is formed with a finer pitch than other wirings.
前記（ｄ）工程では、前記層間絶縁樹脂層より前記半導体チップに近い熱膨張係数の前記絶縁樹脂層を形成することを特徴とする。 In the manufacturing method of the semiconductor device according to claim 4 or 5 ,
In step (d), and forming the insulating resin layer of the thermal expansion coefficient close to the semiconductor chip than the previous SL layer insulating resin layer.
前記（ａ）工程では、シリコンウエハの第１面およびそれとは反対側の第２面のそれぞれに前記第１配線パターンおよび前記第２配線パターンを形成した前記インターポーザを準備することを特徴とする。 In the manufacturing method of the semiconductor device of Claim 4, 5 or 6 ,
In the step (a), the interposer in which the first wiring pattern and the second wiring pattern are formed on each of the first surface of the silicon wafer and the second surface opposite to the first surface is prepared.
前記（ａ）工程では、セラミック材を含む基板の第１面およびそれとは反対側の第２面のそれぞれに前記第１配線パターンおよび前記第２配線パターンを形成した前記インターポーザを準備することを特徴とする。 In the manufacturing method of the semiconductor device of Claim 4, 5 or 6 ,
In the step (a), the interposer in which the first wiring pattern and the second wiring pattern are formed on each of the first surface of the substrate containing the ceramic material and the second surface opposite to the first surface is prepared. And
前記（ａ）工程では、樹脂からなる基板の第１面およびそれとは反対側の第２面のそれぞれに前記第１配線パターンおよび前記第２配線パターンを形成した前記インターポーザを準備することを特徴とする。 In the manufacturing method of the semiconductor device of Claim 4, 5 or 6 ,
In the step (a), the interposer in which the first wiring pattern and the second wiring pattern are formed on each of the first surface of the substrate made of resin and the second surface opposite to the first surface is prepared. To do.
前記（ｂ）工程では、銅板からなる前記支持体を準備し、
前記（ｇ）工程では、エッチングにより前記銅板を除去することを特徴とする。 In the manufacturing method of the semiconductor device according to any one of claims 4 to 9 ,
In the step (b), the support made of a copper plate is prepared,
In the step (g) , the copper plate is removed by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010050962A JP5577760B2 (en) | 2009-03-09 | 2010-03-08 | Package substrate and method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009054756 | 2009-03-09 | ||
| JP2009054756 | 2009-03-09 | ||
| JP2010050962A JP5577760B2 (en) | 2009-03-09 | 2010-03-08 | Package substrate and method for manufacturing semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2010239126A JP2010239126A (en) | 2010-10-21 |
| JP2010239126A5 true JP2010239126A5 (en) | 2013-02-14 |
| JP5577760B2 JP5577760B2 (en) | 2014-08-27 |
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Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101789765B1 (en) | 2010-12-16 | 2017-11-21 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
| JP5649490B2 (en) * | 2011-03-16 | 2015-01-07 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
| TWI492680B (en) | 2011-08-05 | 2015-07-11 | Unimicron Technology Corp | Package substrate having embedded interposer and fabrication method thereof |
| TWI476888B (en) * | 2011-10-31 | 2015-03-11 | Unimicron Technology Corp | Package substrate having embedded via hole medium layer and fabrication method thereof |
| JP5536748B2 (en) * | 2011-12-16 | 2014-07-02 | 聯致科技股▲フン▼有限公司 | Manufacturing method of package substrate |
| TWI543307B (en) | 2012-09-27 | 2016-07-21 | 欣興電子股份有限公司 | Package carrier and chip package structure |
| JP6000297B2 (en) * | 2014-03-17 | 2016-09-28 | 聯致科技股▲フン▼有限公司 | Package substrate |
| WO2016043779A1 (en) | 2014-09-19 | 2016-03-24 | Intel Corporation | Semiconductor packages with embedded bridge interconnects |
| KR101731700B1 (en) | 2015-03-18 | 2017-04-28 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
| JP2017228647A (en) * | 2016-06-22 | 2017-12-28 | 富士通株式会社 | Resin interposer, semiconductor device using the same, and method of manufacturing resin interposer |
| KR101815785B1 (en) | 2016-08-31 | 2018-01-05 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
| KR101815784B1 (en) | 2016-08-31 | 2018-01-05 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
| US10410999B2 (en) | 2017-12-19 | 2019-09-10 | Amkor Technology, Inc. | Semiconductor device with integrated heat distribution and manufacturing method thereof |
| KR102556703B1 (en) * | 2018-05-30 | 2023-07-18 | 삼성전기주식회사 | Package board and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0837205A (en) * | 1994-07-22 | 1996-02-06 | Hitachi Ltd | TAB package |
| JP4890959B2 (en) * | 2005-06-17 | 2012-03-07 | 日本電気株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE |
| US7462784B2 (en) * | 2006-05-02 | 2008-12-09 | Ibiden Co., Ltd. | Heat resistant substrate incorporated circuit wiring board |
| JP5174355B2 (en) * | 2007-02-02 | 2013-04-03 | 新光電気工業株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE |
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