JP2010230888A - Electro-optical device and electronic apparatus - Google Patents

Abstract

A dead space caused by a first intermediate conductive layer and a second intermediate conductive layer is reduced.
A first switching element Q1 and a second switching element Q2 operate with a scanning line 22 as a gate. The first switching element Q1 is interposed between the first data line 24A and the first intermediate conductive layer 541, and the second switching element Q2 is interposed between the second data line 24B and the second intermediate conductive layer 542. The first intermediate conductive layer 541 is electrically connected to the first switching element Q1 via the conduction hole HB1 of the first insulating layer L1, and the second intermediate conductive layer 542 is first connected via the conduction hole HB2 of the first insulating layer L2. 2 Conducts to switching element Q2. The first electrode 31 is conducted to the first intermediate conductive layer 541 through the conduction hole HC1 of the second insulating layer L2, and the second electrode 32 is conducted to the conduction hole HC2 between the second insulating layer L2 and the third insulating layer L3. Conduction to the second intermediate conductive layer 542 is performed. The conduction hole HB1, the conduction hole HB2, the conduction hole HC1, and the conduction hole HC2 are arranged along the scanning line 22.
[Selection] Figure 3

Description

  The present invention relates to a technique for controlling an electro-optical material (for example, liquid crystal) whose optical characteristics change according to an electrical action.

  Conventionally proposed is a technique for controlling the gradation (transmittance and reflectance) of an electro-optic material by alternately supplying a predetermined reference potential and a gradation potential corresponding to a designated gradation to two data lines. (For example, Patent Document 1). Patent Document 1 discloses a pixel circuit having a structure as shown in FIG.

  As shown in FIG. 13, the first data line 921 and the second data line 922 are formed so as to intersect the scanning line 91. A first switching element 941 is interposed between the first data line 921 and the first intermediate conductive layer 931, and a second switching element 942 is interposed between the second data line 922 and the second intermediate conductive layer 932. The first intermediate conductive layer 931 is electrically connected to the first switching element 941 via a conduction hole H1 formed in the insulating layer, and the second intermediate conductive layer 932 is a second switching element via the conduction hole H2 of the insulating layer. Conducted to 942. The electro-optic material is driven in accordance with the potential difference (fringe electric field) between the first electrode 951 and the second electrode 952 in FIG. The first electrode 951 is electrically connected to the first intermediate conductive layer 931 through the conductive hole H3 of the insulating layer covering the first intermediate conductive layer 931 and the second intermediate conductive layer 932, and the second electrode 952 is connected to the insulating layer. Conduction is conducted to the second intermediate conductive layer 932 through the conduction hole H4.

JP 2008-65308 A

  However, in the configuration of FIG. 13, the conduction holes H1 and H3 are arranged in the direction perpendicular to the scanning line 91, and the conduction holes H2 and H4 extend in the direction perpendicular to the scanning line 91. There is a problem in that the dead space in the pixel circuit (for example, the region 96 in FIG. 13) increases, and as a result, high definition of the pixel circuit is restricted. In consideration of the above circumstances, an object of the present invention is to reduce dead space caused by the first intermediate conductive layer and the second intermediate conductive layer.

  In order to solve the above problems, an electro-optical device according to a first aspect of the present invention is an electro-optical device in which an electro-optical material is disposed between a first substrate and a second substrate facing each other. The scanning line formed on the surface of the first substrate facing the second substrate, the first switching element and the second switching element having the scanning line as a gate, the scanning line, the first switching element, and the first switching element A first insulating layer covering the two switching elements, and a first conduction hole (for example, as shown in FIGS. 3 and 7) formed on the surface of the first insulating layer so as not to overlap the scanning line in plan view. A first intermediate conductive layer conducting to the first switching element via the conduction hole HB1) and a second conduction of the first insulating layer formed on the surface of the first insulating layer so as not to overlap the scanning line in plan view. The second switching element through a hole (for example, the conduction hole HB2 in FIGS. 3 and 7) A second intermediate conductive layer conducting to the first data line, a first data line and a second data line extending in a direction intersecting the scanning line, a second insulating layer covering the first intermediate conductive layer and the second intermediate conductive layer, A first electrode formed on the surface of the second insulating layer and electrically connected to the first intermediate conductive layer via a third conductive hole (for example, the conductive hole HC1 in FIGS. 3 and 7) of the second insulating layer; A third insulating layer covering one electrode and a fourth conductive hole (for example, the conductive hole HC2 in FIGS. 3 and 7) formed on the surface of the third insulating layer and the third insulating layer and the second insulating layer. A second electrode conducting to the second intermediate conductive layer, wherein the first switching element is electrically interposed between the first data line and the first intermediate conductive layer, and the second switching element is 2 electrically connected between the data line and the second intermediate conductive layer, and the first conduction hole, the second conduction hole, the third conduction hole, and the fourth conduction hole The scanning lines are arranged along the extending direction. Both the first embodiment and the second embodiment described later are included in the first aspect.

  The electro-optical device according to the second aspect of the invention includes an electro-optical material disposed between the first substrate and the second substrate facing each other, and a facing surface of the first substrate facing the second substrate. A first scanning line and a second scanning line formed on the surface, a first data line extending in a direction intersecting the first scanning line and the second scanning line (for example, the data line 241 in FIG. 7), Two data lines (for example, the data line 242 in FIG. 7) and a third data line (for example, the data line 243 in FIG. 7), a first pixel circuit (for example, the pixel circuit PA in FIG. 7), and a second pixel circuit (for example, in FIG. 7). Pixel circuit PB), and each of the first pixel circuit and the second pixel circuit includes a first switching element, a second switching element, a first scanning line, a second scanning line, a first switching element, and a first switching element. A first insulating layer covering the two switching elements, and in plan view The first switching element is formed on the surface of the first insulating layer so as not to overlap the one scanning line and the second scanning line, and through the first conduction hole (for example, conduction hole HB1 in FIG. 7) of the first insulation layer. And a second conductive hole (for example, formed on the surface of the first insulating layer so as not to overlap the first scanning line and the second scanning line in plan view). A second intermediate conductive layer conducting to the second switching element via the conduction hole HB2) of FIG. 7, a second insulating layer covering the first intermediate conductive layer and the second intermediate conductive layer, and a surface of the second insulating layer A first electrode that is formed on the second intermediate layer and is electrically connected to the first intermediate conductive layer via a third conductive hole (for example, the conductive hole HC1 in FIG. 7) of the second insulating layer; a third insulating layer that covers the first electrode; Formed on the surface of the third insulating layer and via a fourth conduction hole (for example, conduction hole HC2 in FIG. 7) of the third and second insulation layers. And a second electrode conducting to the second intermediate conductive layer. In the first pixel circuit, the first switching element and the second switching element operate using the first scanning line as a gate, and the first switching element is The second switching element is electrically interposed between the second data line and the second intermediate conductive layer, and the second pixel is electrically interposed between the first data line and the first intermediate conductive layer. In the circuit, the first switching element and the second switching element operate using the second scanning line as a gate, and the first switching element is electrically interposed between the second data line and the first intermediate conductive layer. The second switching element is electrically interposed between the third data line and the second intermediate conductive layer, and the first conduction hole and the second conduction hole in each of the first pixel circuit and the second pixel circuit. And the third conduction hole and the fourth conduction hole The first scan line and the second scanning line are arranged along a direction extending. A specific example of the second aspect will be described later as a second embodiment.

  In the first aspect and the second aspect, since the first conduction hole, the second conduction hole, the third conduction hole, and the fourth conduction hole are arranged along the scanning line, the first conduction hole and the third conduction hole are arranged. Compared to a configuration in which the holes are arranged in a direction perpendicular to the scanning line and a configuration in which the second conduction holes and the fourth conduction holes are arranged in a direction perpendicular to the scanning line, the first intermediate conductive layer and the second intermediate conductive layer Dead space due to layers is reduced. Therefore, it is possible to achieve higher definition and an improved aperture ratio of the pixel circuit. The electro-optical device according to the present invention (the first aspect and the second aspect) is used in various electronic apparatuses as an apparatus for displaying an image. Typical examples of the electronic apparatus according to the present invention are a personal computer and a mobile phone.

  In the present invention (the first and second aspects), “the element B is formed on the surface of the element A” means that the element B is formed so as to contact the surface of the element A. In addition to the above, it is a concept including a case where another element is interposed between the element A and the element B (for example, when the element B is formed on the surface of another element covering the element A). In other words, the element B is formed above. Further, the first conduction hole, the second conduction hole, the third conduction hole, and the fourth conduction hole extend along the direction in which the scanning lines (in the second mode, the first scanning line and the second scanning line) extend. In addition to the configuration in which each conduction hole is formed only in one region across the scanning line (for example, FIG. 3), the arrangement is arranged in each region between the one region and the other region across the scanning line. A configuration (for example, FIG. 9) formed by separating the holes is also included.

  In each of the first pixel circuit and the second pixel circuit according to the second aspect of the present invention, the first conduction hole, the second conduction hole, the third conduction hole, and the fourth conduction hole are first scanned in plan view. It is located in the gap between the line and the second scan line. In the above aspect, the region in the gap between the first scan line and the second scan line can be effectively used for forming each conduction hole (dead space between the first scan line and the second scan line). Can be reduced).

  In the present invention (first and second embodiments), the first intermediate conductive layer and the second intermediate conductive layer are formed in a congruent or symmetrical shape, or the first intermediate conductive layer and the scanning line A configuration in which the distance between them is equal to the distance between the second intermediate conductive layer and the scanning line is preferable. In each of the above aspects, the capacitance value of the capacitance associated between the first intermediate conductive layer and the scan line approaches the capacitance value of the capacitance associated between the second intermediate conductive layer and the scan line. The amount of change in potential of the first intermediate conductive layer when the potential of the scanning line changes can be made substantially equal to the amount of change in potential of the second intermediate conductive layer.

  The “joint” between the shape of the first intermediate conductive layer and the shape of the second intermediate conductive layer is that both the planar shape and the dimension (size) of the first intermediate conductive layer and the second intermediate conductive layer are the same. It means to substantially match. Further, the “symmetry” between the shape of the first intermediate conductive layer and the shape of the second intermediate conductive layer is the first intermediate with respect to a predetermined target axis (typically an axis in a direction perpendicular to the scanning line or the data line). It means that the shape obtained by inverting one of the conductive layer and the second intermediate conductive layer is congruent with the other shape. “Congruent” and “symmetric” are interpreted in view of substance. That is, even when there is a manufacturing error (processing error or alignment error) in the shape of the first intermediate conductive layer or the second intermediate conductive layer, it is included in the concept of “congruent” or “symmetric” in the above definition.

  Further, the distance between the first intermediate conductive layer and the scan line and the distance between the second intermediate conductive layer and the scan line are “equal”, in addition to the case where both distances completely match, The case where both distances substantially coincide is also included. In the case of “substantially coincides”, for example, the difference between the fluctuation amount of the potential of the first intermediate conductive layer and the fluctuation amount of the potential of the second intermediate conductive layer when the potential of the scanning line fluctuates is the electro-optical device. To the extent that it is not recognized by the user under the main use of (for example, when the electro-optical device is used for displaying an image, the difference in the gradation of the image cannot be recognized by the user). This includes the case where the distance between the conductive layer and the scanning line is different from the distance between the second intermediate conductive layer and the scanning line.

1 is a block diagram of an electro-optical device according to a first embodiment of the invention. FIG. FIG. 3 is a circuit diagram of a pixel circuit in the first embodiment. It is a top view of the pixel circuit in a 1st embodiment. It is sectional drawing of the IV-IV line in FIG. It is a schematic diagram which shows the positional relationship of a 1st intermediate | middle conductive layer and a 2nd intermediate | middle conductive layer, and a scanning line. FIG. 6 is a circuit diagram of a pixel unit of an electro-optical device according to a second embodiment of the invention. It is a top view of the pixel circuit in a 2nd embodiment. It is sectional drawing of the VIII-VIII line in FIG. It is a top view of the pixel circuit which concerns on a modification. It is a perspective view which shows the form (personal computer) of an electronic device. It is a perspective view which shows the form (cellular phone) of an electronic device. It is a perspective view which shows the form (mobile information terminal) of an electronic device. It is a top view of the conventional pixel circuit.

<A: First Embodiment>
FIG. 1 is a block diagram showing an electrical configuration of an electro-optical device 100 according to the first embodiment of the present invention. As shown in FIG. 1, the electro-optical device 100 includes a pixel portion (display region) 14 in which a plurality of pixel circuits P are arranged, and a drive circuit 40 that drives each pixel circuit P. The plurality of pixel circuits P are disposed in the gap between the first substrate 11 and the second substrate 12 that face each other.

  In the pixel portion 14, m scanning lines 22 extending in the X direction and n sets of wiring pairs 240 extending in the Y direction intersecting (orthogonal) with the X direction are formed. The plurality of pixel circuits P are arranged at positions corresponding to the intersections between the scanning lines 22 and the wiring pairs 240. Accordingly, a plurality of pixel circuits P are arranged in a matrix of m rows × n columns.

  FIG. 2 is a circuit diagram of the pixel circuit P. In FIG. 2, one pixel circuit P located in the j-th column (j = 1 to n) of the i-th row (i = 1 to m) is representatively shown. As shown in FIG. 2, the pixel circuit P includes an electro-optic element E, a first switching element Q1, and a second switching element Q2.

  The electro-optic element E includes a first electrode 31 and a second electrode 32, and an electro-optic material 26 whose optical characteristics change according to the voltage (electric field) between the two electrodes. A typical example of the electro-optic material 26 is a liquid crystal whose transmittance (reflectance) changes according to the voltage between the first electrode 31 and the second electrode 32. The electro-optic material 26 is sealed in the gap between the first substrate 11 and the second substrate 12.

  The wiring pair 240 shown in FIG. 1 includes a first data line 24A and a second data line 24B as shown in FIG. The first switching element Q1 of the pixel circuit P is electrically interposed between the first data line 24A of the wiring pair 240 in the j-th column and the first electrode 31, and is electrically connected (conductive / nonconductive). ) To control. On the other hand, the second switching element Q2 of the pixel circuit P is electrically interposed between the second data line 24B and the second electrode 32 of the wiring pair 240 in the j-th column to control the electrical connection between them. . The gate of the first switching element Q1 and the gate of the second switching element Q2 are connected to the scanning line 22 in the i-th row. The conductivity types of switching element Q1 and switching element Q2 are arbitrary.

  A capacitance C 0 is interposed between the first electrode 31 and the second electrode 32 of the electro-optic element E. Further, a capacitor C1 is interposed between the first electrode 31 and a constant potential line (for example, ground line) 16, and a capacitor C2 is interposed between the second electrode 32 and the constant potential line 16. Each capacitor (C 0, C 1, C 2) holds a voltage between the first electrode 31 and the second electrode 32 of the electro-optic element E. A configuration in which the parasitic capacitance of each part of the pixel circuit P is used as the capacitance (C0, C1, C2) or a configuration in which the capacitance (C0, C1, C2) is omitted is also employed.

  The drive circuit 40 of FIG. 1 includes a scanning line drive circuit 42 and a data line drive circuit 44. The scanning line driving circuit 42 sequentially selects the scanning lines 22 in each horizontal scanning period within the vertical scanning period. When the i-th scanning line 22 is selected in the i-th horizontal scanning period, the switching elements Q1 and Q2 of the pixel circuits P belonging to the i-th row are controlled to be in an ON state. Accordingly, the first data line 24A is conducted to the first electrode 31 and the second data line 24B is conducted to the second electrode 32.

  The data line driving circuit 44 outputs data signals XA [1] to XA [n] to the n first data lines 24A in synchronization with the selection of the scanning line 22 by the scanning line driving circuit 42 and n data lines. Data signals XB [1] to XB [n] are output to the second data line 24B. In the horizontal scanning period in which the i-th scanning line 22 is selected, the data signal XA [j] output to the first data line 24A in the j-th column is the pixel circuit P positioned in the j-th column in the i-th row. The data signal XB [j] set to one of the gradation potential VX corresponding to the designated gradation and the predetermined reference potential (common potential) VCOM and output to the second data line 24B in the j-th column It is set to the other of the potential VX and the reference potential VCOM. Therefore, the electro-optical element E has a state in which the gradation potential VX is supplied to the first electrode 31 and the reference potential VCOM is supplied to the second electrode 32 (hereinafter referred to as “first state”), and the gradation potential VX. Is supplied to the second electrode 32 and the reference potential VCOM is driven to one of the states in which it is supplied to the first electrode 31 (hereinafter referred to as “second state”).

  In the data line driving circuit 44, the electro-optical element E in the first state and the electro-optical element E in the second state are mixedly dispersed in the pixel unit 14, and the state of each electro-optical element E is in the first state. The data signals XA [1] to XA [n] and the data signals XB [1] to XB [n] are generated so as to sequentially change from one of the second states to the other. For example, the electro-optical element E in the first state and the electro-optical element E in the second state are adjacent to each other along at least one of the X direction and the Y direction, and the state of the electro-optical element E is changed every vertical scanning period. A combination of the data signal XA [j] and the data signal XB [j], the gradation potential VX, and the reference potential VCOM is set so as to sequentially change from one of the first state and the second state to the other. The electrical configuration of the electro-optical device 100 has been described above.

  3 is a plan view showing a structure of a portion of the pixel circuit P where the scanning line 22 and the wiring pair 240 (the first data line 24A and the second data line 24B) intersect. FIG. It is sectional drawing of the IV-IV line. Since the structure of each pixel circuit P is common, the structure will be described below with a focus on one pixel circuit P. 3 and 4 are hatched in the same manner for the sake of convenience. In FIGS. 3 and 4, the capacitances (C0, C1, C2) are not shown for convenience.

  As shown in FIGS. 3 and 4, on the surface of the first substrate 11 facing the second substrate 12, the semiconductor layer 521 of the first switching element Q1 and the semiconductor layer 522 of the second switching element Q2 are provided. Is formed of a semiconductor material (eg, polysilicon). The semiconductor layer 521 and the semiconductor layer 522 are covered with the gate insulating layer L0. The scanning line 22 is formed on the surface of the gate insulating layer L0 so as to extend in the X direction. The portion of the scanning line 22 that overlaps the semiconductor layer 521 (channel region) functions as the gate of the first switching element Q1, and the portion of the scanning line 22 that overlaps the semiconductor layer 522 (channel region) is the gate of the second switching element Q2. Function as.

  As shown in FIG. 4, the first insulating layer L1 is formed so as to cover the surface of the gate insulating layer L0 where the scanning line 22 is formed (that is, to cover the scanning line 22, the semiconductor layer 521, and the semiconductor layer 522). The The first insulating layer L1 is formed of an insulating material such as silicon oxide or silicon nitride, for example. On the surface of the first insulating layer L1, as shown in FIGS. 3 and 4, first data lines 24A and second data lines 24B extending in the Y direction are formed with an interval in the X direction. Is done. The first data line 24A is electrically connected to the semiconductor layer 521 (source region or drain region) through a conduction hole (contact hole) HA1 penetrating the first insulating layer L1 and the gate insulating layer L0. Similarly, the second data line 24B is electrically connected to the semiconductor layer 522 (source region or drain region) through a conduction hole HA2 penetrating the first insulating layer L1 and the gate insulating layer L0.

  A first intermediate conductive layer 541 and a second intermediate conductive layer 542 are formed on the surface of the first insulating layer L1. The first intermediate conductive layer 541 and the second intermediate conductive layer 542 are formed from the same layer as the first data line 24A and the second data line 24B. That is, in the step of selectively removing the conductive film formed on the surface of the first insulating layer L1, the first intermediate conductive layer 541 and the second intermediate conductive layer 542, the first data line 24A, and the second data line 24B. Are collectively formed. For the formation of the first intermediate conductive layer 541 and the second intermediate conductive layer 542 (and the first data line 24A and the second data line 24B), a low-resistance metal such as aluminum or chromium is preferably employed.

  As shown in FIGS. 3 and 4, the first intermediate conductive layer 541 is electrically connected to the semiconductor layer 521 (source region or drain region) through a conductive hole HB1 that penetrates the first insulating layer L1 and the gate insulating layer L0. To do. Similarly, the second intermediate conductive layer 542 is electrically connected to the semiconductor layer 522 (source region or drain region) through a conduction hole HB2 penetrating the first insulating layer L1 and the gate insulating layer L0.

  As shown in FIG. 3, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are formed in a region between the first data line 24A and the second data line 24B and X along the scanning line 22 Arrange in the direction. The first intermediate conductive layer 541 and the second intermediate conductive layer 542 are formed in an aspect (shape and size) and position that do not overlap the scanning line 22 when viewed from the direction perpendicular to the surface of the first substrate 11 (that is, in plan view). Is done. The first intermediate conductive layer 541 and the second intermediate conductive layer 542 have the same position in the Y direction. Since the scanning line 22 extends in the X direction perpendicular to the Y direction, the distance d1 between the first intermediate conductive layer 541 and the scanning line 22 and the second intermediate conductive layer 542 are scanned as shown in FIG. The distance d2 to the line 22 is equal. The first intermediate conductive layer 541 and the second intermediate conductive layer 542 have a planar shape that is line-symmetric with respect to the axis line in the Y direction.

  As shown in FIG. 4, the second insulating layer L2 covering the first intermediate conductive layer 541 and the second intermediate conductive layer 542, the first data line 24A and the second data line 24B is on the surface of the first insulating layer L1. It is formed. The second insulating layer L2 is a stacked body of a protective insulating layer L2A and a planarizing insulating layer L2B. The protective insulating layer L2A is an insulating film for protecting the first intermediate conductive layer 541 and the second intermediate conductive layer 542, the first data line 24A and the second data line 24B, and the planarizing insulating layer L2B is This is an insulating film for flattening a step on the surface of the first insulating layer L1 (for example, a step caused by each element located below the first insulating layer L1). However, a configuration in which the second insulating layer L2 is a single layer is also employed.

  On the surface of the second insulating layer L2 (planarizing insulating layer L2B), the first electrodes 31 are formed so as to be separated from each other for each pixel circuit P. In FIG. 3, the outer shape of the first electrode 31 is indicated by a chain line for convenience. The first electrode 31 is electrically connected to the first intermediate conductive layer 541 through a conduction hole HC1 penetrating the second insulating layer L2. That is, the first switching element Q1 (semiconductor layer 521) is electrically interposed between the first data line 24A and the first electrode 31. The first intermediate conductive layer 541 corresponds to a node N1 (FIG. 2) between the first switching element Q1 and the first electrode 31.

  As shown in FIG. 4, a third insulating layer L3 covering the first electrode 31 is formed of an insulating material (for example, silicon oxide or silicon nitride) on the surface of the second insulating layer L2. On the surface of the third insulating layer L3, the second electrodes 32 are formed spaced apart from each other for each pixel circuit P. In FIG. 3, the outer shape of the second electrode 32 is shown by a broken line for convenience. For the material of the first electrode 31 and the second electrode 32, a light-transmitting conductive material such as ITO (Indium Tin Oxide) is preferably employed. An alignment film (not shown) is formed so as to cover the third insulating layer L3 on which the second electrode 32 is formed.

  As shown in FIGS. 3 and 4, the second electrode 32 is electrically connected to the second intermediate conductive layer 542 through a conduction hole HC2 penetrating the third insulating layer L3 and the second insulating layer L2. That is, the second switching element Q2 (semiconductor layer 522) is electrically interposed between the second data line 24B and the second electrode 32. The second intermediate conductive layer 542 corresponds to a node N2 (FIG. 2) between the second switching element Q2 and the second electrode 32.

  As shown in FIG. 3, the conduction hole HB1, the conduction hole HB2, the conduction hole HC1, and the conduction hole HC2 are arranged along the X direction in which the scanning line 22 extends in a plan view. That is, there is a straight line extending in the X direction so as to pass through a region inside each conduction hole (HB1, HB2, HC1, HC2). Specifically, the conduction hole HC1 and the conduction hole HC2 are located between the conduction hole HB1 and the conduction hole HB2. That is, the conduction hole HC1 is located on the opposite side of the first data line 24A across the conduction hole HB1, and the conduction hole HC2 is located on the opposite side of the second data line 24B across the conduction hole HB2.

  The first electrode 31 and the second electrode 32 overlap with the third insulating layer L3 interposed therebetween. The second electrode 32 is formed with a plurality of slits 321 for generating an electric field between the second electrode 32 and the first electrode 31. In the above configuration, the data signal XA [j] (one of the gradation potential VX and the reference potential VCOM) is supplied to the first electrode via the first data line 24A, the first switching element Q1, and the first intermediate conductive layer 541. 31 and the data signal XB [j] (the other of the gradation potential VX and the reference potential VCOM) is supplied to the second electrode via the second data line 24B, the second switching element Q2, and the second intermediate conductive layer 542. 32. Then, the level of the electro-optic material 26 is generated by the action of an electric field (fringe field) generated between both electrodes in accordance with the potential difference between the first electrode 31 and the second electrode 32 (difference between the gradation potential VX and the reference potential VCOM). Tone changes.

  In the above embodiment, the conductive hole HB1 and conductive hole HC1 for connection of the first intermediate conductive layer 541 and the conductive hole HB2 and conductive hole HC2 for connection of the second intermediate conductive layer 542 are arranged in the X direction. Compared with the configuration of FIG. 13, the conduction hole H 1 and the conduction hole H 3 are arranged in the direction perpendicular to the scanning line 91 and the conduction hole H 2 and the conduction hole H 4 are arranged in the direction perpendicular to the scanning line 91. Dead space due to the first intermediate conductive layer 541 and the second intermediate conductive layer 542 is reduced. Accordingly, it is possible to realize high definition and an improvement in aperture ratio of the pixel circuit P.

  Further, since the first intermediate conductive layer 541 and the second intermediate conductive layer 542 do not overlap the scanning line 22 in plan view, the parasitic capacitance between the first intermediate conductive layer 541 and the scanning line 22 and the second intermediate conductive layer The parasitic capacitance between 542 and the scan line 22 is reduced. Therefore, compared with the configuration in which the first intermediate conductive layer 541 and the second intermediate conductive layer 542 overlap the scan line 22 (hereinafter referred to as “comparative 1”), the scan line 22, the first intermediate conductive layer 541, and the second intermediate conductive layer 542 are combined. There is an advantage that the dullness of the signal (potential) supplied to the conductive layer 542 is suppressed, and as a result, high definition and high speed operation of the pixel circuit P are realized.

  In contrast 1, there is a problem that the scanning line 22 is short-circuited to the first intermediate conductive layer 541 and the second intermediate conductive layer 542 when a defect occurs in the first insulating layer L1. In the first embodiment in which the first intermediate conductive layer 541 and the second intermediate conductive layer 542 do not overlap the scanning line 22, even if a defect occurs in the first insulating layer L1, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 There is also an advantage that a short circuit between the intermediate conductive layer 542 and the scanning line 22 is prevented (as a result, yield and reliability are improved).

  Furthermore, since the first intermediate conductive layer 541 and the second intermediate conductive layer 542 do not overlap the scanning line 22, the step difference on the surface of the second insulating layer L2 is reduced compared to the comparative 1 (second insulating layer). The surface of the layer L2 is flattened). Therefore, for example, there is an advantage that display quality deterioration due to a step on the surface of the alignment film (specifically, poor alignment of the electro-optic material 26 due to uneven rubbing treatment at the step of the alignment film) can be suppressed.

  For example, in the configuration in which the reference potential VCOM is fixedly supplied to the second electrode 32, there is no need to interpose the second switching element Q2 between the second electrode 32 and the second data line 24B. It is not necessary to form the conductive layer 542 in the pixel circuit P. On the other hand, as shown in FIG. 2, the gradation potential VX and the reference potential VCOM are alternately supplied to the first electrode 31 and the second electrode 32 (that is, the first switching element Q1 and the second switching element Q2). In the configuration in which the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are required for one pixel circuit P, each of the above effects is particularly effective.

  Note that although the first intermediate conductive layer 541 and the second intermediate conductive layer 542 do not overlap the scan line 22, the first intermediate conductive layer 541 or the second intermediate conductive layer 542 and the scan line 22 are not connected. Capacitance can be parasitic. Therefore, the potentials of the first intermediate conductive layer 541 and the second intermediate conductive layer 542 can change in conjunction with the fluctuation (selection / non-selection) of the potential of the scanning line 22. Now, a configuration in which the parasitic capacitance between the first intermediate conductive layer 541 and the scanning line 22 and the parasitic capacitance between the second intermediate conductive layer 542 and the scanning line 22 are different is assumed as the comparative 2. Under the comparative 2, since the capacitance value of the capacitance accompanying the scanning line 22 is different between the first intermediate conductive layer 541 and the second intermediate conductive layer 542, when the potential of the scanning line 22 fluctuates. The amount of change in potential of the first intermediate conductive layer 541 is different from the amount of change in potential of the second intermediate conductive layer 542. Therefore, even when the designated gradation is the same, the actual gradation is different between the case where the electro-optic element E is in the first state and the case where it is in the second state. There is a problem of occurrence of patching.

  On the other hand, in the first embodiment, the distance d1 between the first intermediate conductive layer 541 and the scanning line 22 is equal to the distance d2 between the second intermediate conductive layer 542 and the scanning line 22, and the first intermediate conductive layer 541 and the second Since the shape of the intermediate conductive layer 542 is axisymmetric with respect to the axis in the Y direction, the parasitic capacitance between the first intermediate conductive layer 541 and the scan line 22 and the second intermediate conductive layer 542 and the scan line 22 are The capacitance values are approximately the same as the parasitic capacitance. Therefore, the fluctuation amount of the potential of the first intermediate conductive layer 541 and the fluctuation amount of the potential of the second intermediate conductive layer 542 when the potential of the scanning line 22 fluctuates are approximated (ideally coincident), and the proportional 2 There is also an advantage that flicker and crosstalk, which are problems, are suppressed.

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described. In addition, about the element in which an effect | action and a function are equivalent to 1st Embodiment in each following form, the same code | symbol as the above is attached | subjected and each detailed description is abbreviate | omitted suitably.

  FIG. 6 is a schematic diagram of the pixel unit 14 in the second embodiment. As shown in FIG. 6, m sets of wiring pairs 220 extending in the X direction and (n + 1) data lines 24 extending in the Y direction are formed in the pixel portion 14. M pixel circuits P for one column are arranged between two data lines 24 adjacent in the X direction. That is, one data line 24 is interposed between the pixel circuits P adjacent in the X direction. The electrical configuration of the pixel circuit P is the same as in the first embodiment. In FIG. 6, the illustration of the capacitors (C0, C1, C2) in the pixel circuit P is omitted.

  Each of the m sets of wiring pairs 220 includes a first scanning line 22A and a second scanning line 22B. The first switching element Q 1 and the second switching element Q 2 in the pixel circuit PA (for example, the pixel circuit P in the odd-numbered column) among the n pixel circuits P in the i-th row are the first of the wiring pair 220 in the i-th row. A gate is connected to the scanning line 22A. On the other hand, the first switching element Q1 and the second switching element Q2 in the pixel circuit PB (for example, the pixel circuit P in the even-numbered column) among the n pixel circuits P in the i-th row are connected to the wiring pair 220 in the i-th row. A gate is connected to the second scanning line 22B.

  The drive circuit 40 drives the pixel circuit PA and the pixel circuit PB in each row in a time division manner. Specifically, the scanning line driving circuit 42 selects the first scanning line 22A and the second scanning line 22B of the i-th wiring pair 220 in a time division manner in the i-th horizontal scanning period in the vertical scanning period. To do. For example, the scanning line driving circuit 42 selects the first scanning line 22A of the wiring pair 220 in the i-th row in the first period (for example, the first half period) in the i-th horizontal scanning period, and the i-th horizontal scanning period. The second scanning line 22B of the i-th line pair 220 is selected in a second period (for example, the latter half period) within the horizontal scanning period.

  The data line driving circuit 44 supplies the data signal XA [j] and the data signal XB [j] to each pixel circuit PA in the first period in each horizontal scanning period, and each data in the second period in each horizontal scanning period. A data signal XA [j] and a data signal XB [j] are supplied to the pixel circuit PB. The data signal XA [j] is supplied to the pixel circuit P in the j-th column via the data line 24 in the j-th column and the data signal XB [j] is transmitted through the (j + 1) th data line 24. Is supplied. That is, the (j + 1) th column data line 24 supplies the data signal XB [j] to the jth column pixel circuit P (for example, the pixel circuit PA) and the (j + 1) th column pixel circuit P ( For example, it is shared with the supply of the data signal XA [j] to the pixel circuit PB). Therefore, compared with the first embodiment in which two data lines 24 (first data line 24A and second data line 24B) are formed for each column of the pixel circuits P, the number of data lines 24 is approximately halved. It is possible to reduce. As in the first embodiment, the electro-optic element E in the first state and the electro-optic element E in the second state are dispersedly mixed in the pixel unit 14, and the state of each electro-optic element E is The data line driving circuit 44 sets the data signal XA [j] and the data signal XB [j] to the gradation potential VX and the reference potential VCOM so as to sequentially change from one of the first state and the second state to the other. To do.

  7 is a plan view showing the structure of the pixel circuit P, and FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. In FIG. 7, three data lines 24 (241 to 243), a pixel circuit PA located between the data lines 241 and 242 and a pixel circuit located between the data lines 242 and 243. PB is representatively shown.

  As in the first embodiment, the semiconductor layer 521 (first switching element Q1) and the semiconductor layer 522 (second switching element Q2) are formed on the surface of the first substrate 11 facing the second substrate 12. Is formed for each pixel circuit P. Further, on the surface of the gate insulating layer L0 covering the semiconductor layer 521 and the semiconductor layer 522, the first scanning line 22A and the second scanning line 22B extending in the X direction are formed with a space therebetween in the Y direction. Is done. The first scanning line 22A is formed so as to overlap with the semiconductor layers 521 and 522 of the pixel circuit PA and functions as a gate, and the second scanning line 22B overlaps with the semiconductor layers 521 and 522 of the pixel circuit PB. Thus formed, it functions as a gate.

  As shown in FIG. 8, a first insulating layer L1 covering the semiconductor layer 521 and the semiconductor layer 522, the first scanning line 22A and the second scanning line 22B is formed on the surface of the gate insulating layer L0. (N + 1) data lines 24 are formed on the surface of the first insulating layer L1. In the data line 24 of the (j + 1) th column, the semiconductor layer 521 (first switching element Q1) of the pixel circuit P of the (j + 1) th column is connected to the conduction hole of the first insulating layer L1 and the gate insulating layer L0. The semiconductor layer 522 (second switching element Q2) of the pixel circuit P in the j-th column is connected through HA1, and is connected through the conduction hole HA2 of the first insulating layer L1 and the gate insulating layer L0.

  A first intermediate conductive layer 541 and a second intermediate conductive layer 542 are formed in the same layer as the data line 24 for each pixel circuit P on the surface of the first insulating layer L1. The first intermediate conductive layer 541 is electrically connected to the semiconductor layer 521 through a conduction hole HB1 penetrating the first insulating layer L1 and the gate insulating layer L0, and the second intermediate conductive layer 542 is connected to the first insulating layer L1 and the gate. Conduction to the semiconductor layer 522 through a conduction hole HB2 penetrating the insulating layer L0.

  In both the pixel circuit PA and the pixel circuit PB, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are formed so as not to overlap the scanning line 22 in plan view. Specifically, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are formed in a region between the first scanning line 22A and the second scanning line 22B, and the first scanning line 22A and the second scanning line. They are arranged in the X direction along the line 22B. Further, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are located at an equal distance from each of the first scanning line 22A and the second scanning line 22B (that is, the position in the Y direction is common), and It is formed in a line-symmetric shape with respect to the axis in the Y direction. Therefore, the parasitic capacitance between the first intermediate conductive layer 541 and the first scan line 22A or the second scan line 22B, and between the second intermediate conductive layer 542 and the first scan line 22A or the second scan line 22B. The parasitic capacitance substantially coincides with the capacitance value.

  The structures of the first electrode 31 and the second electrode 32 are the same as in the first embodiment. That is, the first electrode 31 is formed on the surface of the second insulating layer L2 (protective insulating layer L2A, planarizing insulating layer L2B) that covers the first intermediate conductive layer 541, the second intermediate conductive layer 542, and the data lines 24. It is formed and conducted to the first intermediate conductive layer 541 through the conduction hole HC1 of the second insulating layer L2. Further, the second electrode 32 is formed on the surface of the third insulating layer L3 covering the first electrode 31, and the second intermediate layer is formed through the conduction hole HC2 penetrating the third insulating layer L3 and the second insulating layer L2. It is electrically connected to the conductive layer 542.

  Therefore, in the pixel circuit PA in FIG. 7, the first switching element Q1 is electrically interposed between the first intermediate conductive layer 541 (first electrode 31) and the data line 241 and the second intermediate conductive layer 542 ( A second switching element Q2 is electrically interposed between the second electrode 32) and the data line 242. On the other hand, in the pixel circuit PB of FIG. 7, the first switching element Q1 is electrically interposed between the first intermediate conductive layer 541 (first electrode 31) and the data line 242, and the second intermediate conductive layer 542 ( A second switching element Q2 is electrically interposed between the second electrode 32) and the data line 243.

  As shown in FIG. 7, in each of the pixel circuit PA and the pixel circuit PB, the conduction hole HB1, the conduction hole HB2, the conduction hole HC1, and the conduction hole HC2 are viewed in plan from the first scanning line 22A and the second scanning line. The lines 22B are arranged along the extending X direction. Further, the conduction hole HB1, the conduction hole HB2, the conduction hole HC1, and the conduction hole HC2 are located in a region between the first scanning line 22A and the second scanning line 22B.

  In the second embodiment, the conduction hole HB1, the conduction hole HB2, the conduction hole HC1, and the conduction hole HC2 are formed along the first scanning line 22A and the second scanning line 22B, and the first intermediate conductive layer 541 is formed. Since the second intermediate conductive layer 542 is formed so as not to overlap the first scanning line 22A or the second scanning line 22B, the same effect as in the first embodiment is realized. Further, the conduction hole HB1, the conduction hole HB2, the conduction hole HC1, and the conduction hole HC2 are formed between the first scanning line 22A and the second scanning line 22B. That is, the region between the first scanning line 22A and the second scanning line 22B is effectively used (does not become a dead space). Therefore, the effect that the dead space caused by the first intermediate conductive layer 541 and the second intermediate conductive layer 542 can be reduced is particularly remarkable.

<C: Modification>
Various modifications are added to the above embodiments. An example of a specific modification is as follows. Two or more aspects may be arbitrarily selected from the following examples and combined.

(1) Modification 1
In each of the above embodiments, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 have a line-symmetric shape, but the first intermediate conductive layer 541 and the second intermediate conductive layer 542 have a congruent shape. Is also adopted. Further, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 may be formed from layers different from the data line 24.

(2) Modification 2
The configuration in which the distance from the scanning line 22 in plan view is the same in the first intermediate conductive layer 541 and the second intermediate conductive layer 542, and the shapes of the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are the same or The symmetrical configuration approximates the amount of fluctuation in the potential of the first intermediate conductive layer 541 and the amount of fluctuation in the potential of the second intermediate conductive layer 542 when the potential of the scanning line 22 fluctuates (further, flicker or crossover). It is a configuration for realizing a special effect of suppressing talk), and is essential for solving the intended problem of reducing dead space caused by the first intermediate conductive layer 541 and the second intermediate conductive layer 542 It is not a requirement. Accordingly, the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are different in shape (not congruent or symmetric), and the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are positioned in the Y direction. However, different configurations may be included in the scope of the present invention.

(3) Modification 3
In the first embodiment (FIG. 3), both the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are arranged in the region on one side (the negative side in the Y direction) across the scanning line 22. As shown in FIG. 9, a configuration in which the first intermediate conductive layer 541 and the second intermediate conductive layer 542 are arranged in each region on the opposite side across the scanning line 22 is also employed. Specifically, a first intermediate conductive layer 541 is formed in a negative region in the Y direction across the scanning line 22, and a second intermediate conductive layer is formed in a positive region in the Y direction across the scanning line 22. 542 is formed. Therefore, the shape and positional relationship between the second intermediate conductive layer 542 and the semiconductor layer 522 and the conduction holes (HA2, HB2, HC2) associated with both extend in the X direction in the configuration of FIG. 3 and the configuration of FIG. Symmetric (line symmetry) with respect to the symmetry axis. Also in the configuration of FIG. 9, as in the first embodiment, the conduction hole HB1 and conduction hole HC1 for connection of the first intermediate conductive layer 541 and the conduction hole HB2 and conduction hole for connection of the second intermediate conductive layer 542 are provided. It can be said that HC2 is arranged in the X direction in which the scanning line 22 extends.

(4) Modification 4
The electro-optic material 26 is not limited to liquid crystal. That is, various substances (for example, electrophoretic elements) having characteristics in which optical characteristics (transmittance and luminance) change according to the voltage (electric field) between the first electrode 31 and the second electrode 32 are described above. Adopted as electro-optic material 26 in form.

<D: Application example>
Next, electronic equipment using the electro-optical device according to the invention will be described. FIGS. 10 to 12 show a form of an electronic apparatus that employs the electro-optical device 100 according to any one of the forms exemplified above as a display device.

  FIG. 10 is a perspective view illustrating a configuration of a mobile personal computer that employs the electro-optical device 100. The personal computer 2000 includes an electro-optical device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed.

  FIG. 11 is a perspective view illustrating a configuration of a mobile phone to which the electro-optical device 100 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the electro-optical device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled.

  FIG. 12 is a perspective view illustrating a configuration of a personal digital assistant (PDA) to which the electro-optical device 100 is applied. The portable information terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 that displays various images. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the electro-optical device 100.

  The electronic apparatus to which the electro-optical device according to the present invention is applied includes the digital still camera, the television, the video camera, the car navigation device, the pager, the electronic notebook, and the electronic paper in addition to the apparatuses illustrated in FIGS. Calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices with touch panels, and the like.

DESCRIPTION OF SYMBOLS 100 ... Electro-optical apparatus, 11 ... 1st board | substrate, 12 ... 2nd board | substrate, 14 ... Pixel part, P ... Pixel circuit, 22 ... Scanning line, 220 ... Wiring pair, 22A ... 1st Scanning line, 22B ... second scanning line, 24 ... data line, 240 ... wiring pair, 24A ... first data line, 24B ... second data line, 26 ... electro-optic material, 31 ... first 1 electrode, 32... Second electrode, E... Electrooptic element, Q1... First switching element, Q2... Second switching element, L0... Gate insulating layer, L1. ... 2nd insulating layer, L3 ... 3rd insulating layer, 521 ... Semiconductor layer, 522 ... Semiconductor layer, 541 ... 1st intermediate conductive layer, 542 ... 2nd intermediate conductive layer, HA1, HA2, HB1, HB2, HC1, HC2: Conduction hole.

Claims (5)

An electro-optical device in which an electro-optical material is disposed between a first substrate and a second substrate facing each other,
A scanning line formed on a surface of the first substrate facing the second substrate;
A first switching element and a second switching element having the scanning line as a gate;
A first insulating layer covering the scanning line and the first switching element and the second switching element;
A first intermediate conductive layer formed on a surface of the first insulating layer so as not to overlap the scanning line in a plan view and conducting to the first switching element through a first conduction hole of the first insulating layer; ,
A second intermediate conductive layer formed on a surface of the first insulating layer so as not to overlap the scanning line in a plan view and conducting to the second switching element through a second conduction hole of the first insulating layer; ,
A first data line and a second data line extending in a direction crossing the scan line;
A second insulating layer covering the first intermediate conductive layer and the second intermediate conductive layer;
A first electrode formed on the surface of the second insulating layer and conducting to the first intermediate conductive layer through a third conduction hole of the second insulating layer;
A third insulating layer covering the first electrode;
A second electrode formed on a surface of the third insulating layer and electrically connected to the second intermediate conductive layer through a fourth conductive hole of the third insulating layer and the second insulating layer;
The first switching element is electrically interposed between the first data line and the first intermediate conductive layer,
The second switching element is electrically interposed between the second data line and the second intermediate conductive layer,
The electro-optical device, wherein the first conduction hole, the second conduction hole, the third conduction hole, and the fourth conduction hole are arranged along a direction in which the scanning line extends. An electro-optic material disposed between the first substrate and the second substrate facing each other;
A first scanning line and a second scanning line formed on a surface of the first substrate facing the second substrate;
A first data line, a second data line, and a third data line extending in a direction intersecting the first scanning line and the second scanning line;
A first pixel circuit and a second pixel circuit;
Each of the first pixel circuit and the second pixel circuit includes:
A first switching element and a second switching element;
A first insulating layer covering the first scanning line and the second scanning line, the first switching element and the second switching element;
The first switching element is formed on a surface of the first insulating layer so as not to overlap the first scanning line and the second scanning line in a plan view, and through the first conduction hole of the first insulating layer. A first intermediate conductive layer conducting to
The second switching element is formed on the surface of the first insulating layer so as not to overlap the first scanning line and the second scanning line in a plan view, and through the second conduction hole of the first insulating layer. A second intermediate conductive layer conducting to
A second insulating layer covering the first intermediate conductive layer and the second intermediate conductive layer;
A first electrode formed on the surface of the second insulating layer and conducting to the first intermediate conductive layer through a third conduction hole of the second insulating layer;
A third insulating layer covering the first electrode;
A second electrode formed on the surface of the third insulating layer and conducting to the second intermediate conductive layer through a fourth conduction hole of the third insulating layer and the second insulating layer;
In the first pixel circuit, the first switching element and the second switching element operate using the first scanning line as a gate, and the first switching element is connected to the first data line and the first intermediate line. The second switching element is electrically interposed between the second data line and the second intermediate conductive layer, and is electrically interposed between the conductive layer and the second switching element.
In the second pixel circuit, the first switching element and the second switching element operate using the second scanning line as a gate, and the first switching element is connected to the second data line and the first intermediate line. The second switching element is electrically interposed between the third data line and the second intermediate conductive layer, and is electrically interposed between the conductive layer and the second switching element.
In each of the first pixel circuit and the second pixel circuit, the first conduction hole, the second conduction hole, the third conduction hole, and the fourth conduction hole correspond to the first scanning line and the second conduction hole. An electro-optical device arranged along a direction in which scanning lines extend. In each of the first pixel circuit and the second pixel circuit, the first conduction hole, the second conduction hole, the third conduction hole, and the fourth conduction hole are the first scanning line in a plan view. The electro-optical device according to claim 2, wherein the electro-optical device is located in a gap with the second scanning line. The electro-optical device according to claim 1, wherein the first intermediate conductive layer and the second intermediate conductive layer are congruent or symmetrical in shape. 5. The electro-optical device according to claim 1, wherein a distance between the first intermediate conductive layer and the scanning line is equal to a distance between the second intermediate conductive layer and the scanning line.

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