JP2010225878A - Semiconductor device provided with Schottky barrier diode and manufacturing method thereof - Google Patents

Abstract

A semiconductor device including an SBD having a structure capable of improving a surge withstand capability and reducing a resistance value in a forward direction.
A By along the side surface portion of the p ⁺ -type impurity layer 3 to form an n-type impurity layer 6, the side surface portion of the p ⁺ -type impurity layer 3 n ^- of the depletion layer extending type drift layer 2 spread Make it smaller. Thereby, the width of the depletion layer formed by the PN junction can be narrowed, and the resistance value in the forward direction can be reduced. Since the resistance value in the forward direction can be reduced, the area of the p ⁺ -type impurity layer 3 per unit area of the SiC semiconductor device can be increased, and the surge resistance can be improved and the resistance value in the forward direction can be reduced. It is possible to achieve both.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including a Schottky barrier diode (hereinafter referred to as SBD) and a method for manufacturing the same, and particularly to a semiconductor device using a wide band gap semiconductor such as silicon carbide (hereinafter referred to as SiC). It is preferable.

Conventionally, in Patent Document 1, a p ⁺ -type impurity layer is disposed in an n-type drift layer for the purpose of improving the trade-off relationship between forward ON voltage and reverse leakage current in SBD. A structure in which a PN junction is provided has been proposed. This structure is called a junction barrier Schottky (hereinafter referred to as JBS) structure.

Since the JBS structure is provided with a PN junction, it has a feature that it is highly resistant to avalanche breakdown that occurs when a high voltage such as a surge voltage is applied. This is because hole carriers generated during breakdown are extracted to the anode electrode through the p ⁺ -type impurity layer having a low resistance value. Therefore, the larger the area occupied by the p ⁺ -type impurity layer per unit area of the SiC semiconductor device, the surge current can flow over a wider area, and the surge resistance can be improved.

Japanese Patent Laid-Open No. 05-136015

However, the larger the area of the p ⁺ -type impurity layer, the smaller the contact area between the portion functioning as the SBD, that is, the Schottky electrode serving as the forward current path and the drift layer, and the resistance value in the forward direction increases. There is a problem of increasing the on-voltage of the SBD. For this reason, it is desired to improve both the surge resistance and to reduce the resistance value in the forward direction.

  In view of the above points, the present invention has an object to provide a semiconductor device including an SBD having a structure capable of improving surge withstand capability and reducing the resistance value in the forward direction, and a method for manufacturing the same. To do.

The problem of increasing the resistance value in the forward direction is not only the area ratio between the contact area between the Schottky electrode and the drift layer and the area of the p ⁺ -type impurity layer, but also the width of the depletion layer formed by the PN junction is the resistance. Increase factor. In particular, wide bandgap semiconductors such as SiC have a large built-in potential, so the depletion layer grows larger, and the forward current path area is narrower than the contact area between the Schottky electrode and the drift layer. The resistance value in the forward direction is increased. Therefore, narrowing the width of the depletion layer formed by the PN junction reduces the resistance value in the forward direction. Since the resistance value in the forward direction can be reduced in this way, the area of the p ⁺ -type impurity layer per unit area of the SiC semiconductor device can be increased, and the surge resistance can be improved and the resistance value in the forward direction can be increased. It is possible to achieve both reductions.

  In order to achieve the above object, according to the first aspect of the present invention, the second conductivity type impurity formed of the second conductivity type semiconductor so as to be in contact with the Schottky electrode (4) in the surface layer portion of the drift layer (2). A first conductivity type impurity layer (6) having a higher impurity concentration than the drift layer (2) is provided on the substrate horizontal direction side of the layer (3).

  By comprising in this way, the breadth of the depletion layer extended to the 1st conductivity type impurity layer (6) from the side part of the 2nd conductivity type impurity layer (3) can be made small. Thereby, the width of the depletion layer formed by the PN junction can be narrowed, and the resistance value in the forward direction can be reduced. Since the resistance value in the forward direction can be reduced, the area of the second conductivity type impurity layer (3) per unit area of the SiC semiconductor device can be increased, thereby improving the surge resistance and the resistance value in the forward direction. It is possible to achieve both reductions.

  In the invention according to claim 2, the first conductivity type impurity layer (6) is divided into the second conductivity type impurity layer (6b) disposed on the side of the second conductivity type impurity layer (3) in the horizontal direction of the substrate, and the second conductivity type impurity. (3) It has the structure which has the part (6a) arrange | positioned under the bottom part.

  With such a structure, in addition to the side surface portion of the second conductivity type impurity layer (3), the amount of extension of the depletion layer extending from the bottom portion to the drift layer (2) can also be reduced. For this reason, electrons easily spread to the bottom of the second conductivity type impurity layer (3). Therefore, the width of the current path between the anode and the cathode is widened, and the resistance value in the forward direction can be further reduced. As a result, the effect of claim 1 can be obtained.

  In the invention according to claim 3, the first conductivity type impurity layer (6) has the second conductivity type impurity more than the portion (6b) disposed on the side in the substrate horizontal direction of the second conductivity type impurity layer (3). The portion (6a) disposed below the bottom of (3) is characterized by a higher impurity concentration.

  As described above, if the n-type impurity concentration of the portion (6a) disposed below the bottom of the second conductivity type impurity layer (3) in the first conductivity type impurity layer (6) is increased, the first conductivity type impurity layer (6) is further increased. The spread of the depletion layer extending from the bottom of the two-conductivity type impurity layer (3) to the drift layer (2) can be reduced, and the width of the current path can be further increased. Therefore, the effect of claim 1 can be further obtained.

  The invention according to claim 4 is characterized in that the first conductivity type impurity layer (6) is spaced apart from the Schottky electrode (4) and is formed at a position deeper than the surface of the drift layer (2). Yes.

  With such a structure, the distribution of the depletion layer can be distributed, and the width of the current path can be gradually increased from the Schottky electrode (4), that is, from the anode side to the cathode side. As a result, the width of the current path can be further widened, and the effect of claim 1 can be obtained.

  According to a fifth aspect of the present invention, in a method of manufacturing a semiconductor device including a Schottky barrier diode, a step of forming a drift layer (2) on a substrate (1) and a step of forming a drift layer (2) on a surface of the drift layer (2) One mask (11) is arranged, a region where the second conductivity type impurity layer (3) is to be formed is opened in the first mask (11), and the second conductivity type is formed using the first mask (11). A step of forming a second conductivity type impurity layer (3) by ion implantation of impurities, a second mask (11, 13) is disposed on the surface of the drift layer (2), and the second mask (11, 13) is formed. ) Of the first conductivity type impurity layer (6) is opened, and the second conductivity type impurity layer (by ion implantation of the first conductivity type impurity using the second mask (11, 13). 3) Impurity of the first conductivity type at the horizontal position on the substrate side Is characterized in that it includes a step of forming a layer (6), the. With such a manufacturing method, the semiconductor device according to claim 1 can be manufactured.

  In the invention according to claim 6, the first mask and the second mask used in the step of forming the second conductivity type impurity layer (3) and the step of forming the first conductivity type impurity layer (6) are the same mask ( 11), and the first conductivity type impurity used for forming the first conductivity type impurity layer (6) has a larger diffusion due to heat treatment than the second conductivity type impurity used for forming the second conductivity type impurity layer (3) It is characterized by using.

  As described above, the first conductivity type impurity for forming the first conductivity type impurity layer (6) has a larger diffusion due to the heat treatment than the second conductivity type impurity for forming the second conductivity type impurity layer (3). If one is used, both the second conductivity type impurity layer (3) and the first conductivity type impurity layer (6) can be formed by only one mask (11), and the manufacturing process is simplified. Can be achieved.

  According to a seventh aspect of the present invention, in a method of manufacturing a SiC semiconductor device having a Schottky barrier diode, a substrate (1) made of SiC having a main surface (1a) as a C-plane is used. Forming a drift layer (2) on the surface, and disposing a mask (11) on the surface of the drift layer (2), the second conductivity type impurity layer (3) and the first conductivity of the mask (11). A step of forming a recess (2a) by etching the drift layer (2) using the mask (11), and opening the region where the type impurity layer (6) is to be formed, and selecting in the recess (2a) Epitaxially growing the first conductive type impurity layer (6), and selectively performing epitaxial growth on the surface of the first conductive type impurity layer (6) in the recess (2a). Second conductivity type Is characterized in that it includes a step of forming an object layer (3), the.

  Thus, if the main surface (1a) having a C plane is used as the substrate (1), the surface of the drift layer (2) and the bottom surface of the recess (2a) also become the C plane, and the first conductivity type impurity layer In (6), the first conductivity type impurity concentration can be made higher in the portion epitaxially grown on the bottom surface of the recess (2a) than in the portion epitaxially grown on the side surface of the recess (2a). Thus, the structure of claim 3 can be achieved. When planarization is required, it is preferable to perform planarization by polishing the surface after forming the second conductivity type impurity layer (3).

  According to an eighth aspect of the present invention, in a method of manufacturing a SiC semiconductor device including a Schottky barrier diode, a substrate (1) made of SiC having a main surface (1a) as a Si surface is used. Forming a drift layer (2) on the surface, and disposing a mask (11) on the surface of the drift layer (2), the second conductivity type impurity layer (3) and the first conductivity of the mask (11). A step of forming a recess (2a) by etching the drift layer (2) using the mask (11), and opening the region where the type impurity layer (6) is to be formed, and selecting in the recess (2a) Epitaxially growing the first conductive type impurity layer (6), and selectively performing epitaxial growth on the surface of the first conductive type impurity layer (6) in the recess (2a). Second conductivity type It is characterized in that it contains a step of forming a pure object layer (3).

  Thus, the substrate (1) having a main surface (1a) with an Si surface can also be used. In this case, the surface of the drift layer (2) and the bottom surface of the recess (2a) are also Si surfaces, and the portion of the first conductivity type impurity layer (6) epitaxially grown on the side surface of the recess (2a) is the recess (2a ), The second conductivity type impurity concentration can be made higher than the portion epitaxially grown on the bottom surface. Therefore, in this case, as shown in claim 9, if the epitaxial growth is performed under the same conditions as the deposition conditions of the drift layer (2), the impurity concentration is higher in the side surface of the recess (2a) than in the drift layer (2). The first conductivity type impurity layer (6) can be formed at that portion. When planarization is required, it is preferable to perform planarization by polishing the surface after forming the second conductivity type impurity layer (3).

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing of the SiC semiconductor device provided with SBD concerning 1st Embodiment of this invention. It is sectional drawing of the SiC semiconductor device provided with SBD of the conventional structure. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 1. It is sectional drawing of the SiC semiconductor device provided with SBD concerning 2nd Embodiment of this invention. It is sectional drawing which showed the other manufacturing method of the SiC semiconductor device provided with SBD of the structure shown in FIG. It is sectional drawing of the SiC semiconductor device provided with SBD concerning 3rd Embodiment of this invention. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device provided with SBD concerning 4th Embodiment of this invention. It is sectional drawing of the SiC semiconductor device provided with SBD concerning 5th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of the SiC semiconductor device according to the present embodiment. Hereinafter, the SiC semiconductor device of the present embodiment will be described with reference to this drawing.

As shown in FIG. 1, the SiC semiconductor device uses an n ⁺ type substrate 1 made of SiC having an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ , for example, 5 × 10 ¹⁸ cm ^−3. Is formed. If the upper surface of the n ⁺ -type substrate 1 is the main surface 1a and the lower surface opposite to the main surface 1a is the back surface 1b, 5 × 10 ¹⁵ to 2 × 10 is formed on the main surface 1a with a dopant concentration lower than that of the substrate 1. ^An n ⁻ type drift layer 2 made of SiC having an impurity concentration of about ¹⁶ cm ⁻³ , for example, about 5 × 10 ¹⁵ cm ⁻³ is laminated. SBDs 10 are formed in the cell portions of the n ⁺ type substrate 1 and the n ⁻ type drift layer 2. Although not shown in FIG. 1, a SiC semiconductor device is configured by forming a termination structure or the like in the outer peripheral region of the SBD 10.

Specifically, ap ⁺ -type impurity layer 3 is formed on the surface layer portion of the n ⁻ -type drift layer 2. The p ⁺ -type impurity layer 3 forms a PN junction with the n ⁻ -type drift layer 2 to improve surge resistance.

The p ⁺ -type impurity layer 3 has an impurity concentration of, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ , for example, 5 × 10 ¹⁸ cm ⁻³ , and a depth of about 0.7 μm. This p ⁺ -type impurity layer 3 is for forming a JBS structure, and has various shapes. For example, the p ⁺ -type impurity layer 3 has a stripe shape extending in a direction perpendicular to the paper surface, a dot shape such as a circle, a quadrangle, or a hexagon dotted in the cell portion, and a plurality of ring shapes arranged concentrically. Etc. As described above, the p ⁺ -type impurity layer 3 can be formed in various shapes. In the present embodiment, a case where the p ⁺ -type impurity layer 3 is formed in a stripe shape is described as an example.

Further, Schottky electrode 4 is formed so as to be in contact with n ⁻ type drift layer 2 and p ⁺ type impurity layer 3. Since the Schottky electrode 4 has an opening formed in an insulating film (not shown) formed on the surface of the n ⁻ type drift layer 2 in the cell portion, the n ⁻ type drift layer 2 and the p ⁺ are formed through the opening. It is in contact with the type impurity layer 3. The portion of the Schottky electrode 4 in contact with the n ⁻ type drift layer 2 functions as an SBD 10 by being brought into Schottky contact, and the portion in contact with the p ⁺ type impurity layer 3 is made ohmic contact. It functions as a puller for the hole carrier.

An ohmic electrode 5 made of, for example, nickel, titanium, molybdenum, tungsten, or the like is formed so as to be in contact with the back surface of the n ⁺ type substrate 1. Thus, a JBS structure is formed in which the p ⁺ type impurity layer 3 is formed together with the SBD 10.

Further, in the present embodiment, the n-type impurity layer 6 is formed along the side surface portion of the p ⁺ -type impurity layer 3 in the n ⁻ -type drift layer 2 with respect to the SBD 10 configured as described above. If p ⁺ -type impurity layers 3 are arranged in stripes, n-type impurity layer 6 is formed between adjacent p ⁺ -type impurity layers 3 on the side of substrate horizontal direction of p ⁺ -type impurity layer 3. It is. The n-type impurity layer 6 has a higher concentration than the n ⁻ -type drift layer 2 and is about 6 × 10 ¹⁵ to 4 × 10 ¹⁷ cm ⁻³ , for example, about 1 × 10 ¹⁶ cm ⁻³ . The depth of the n-type impurity layer 6 is optional, it may be equivalent to the p ⁺ -type impurity layer 3 may be shallower or deeper than the p ⁺ -type impurity layer 3. The width of the n-type impurity layer 6, that is, the dimension from the side surface portion of the p ⁺ -type impurity layer 3 (dimension in the horizontal direction on the paper) extends from the p ⁺ -type impurity layer 3 toward the n ⁻ -type drift layer 2 side. It is set corresponding to the width of the depletion layer, for example, 1 μm.

In the SiC semiconductor device including the SBD 10 configured as described above, the Schottky electrode 4 is used as an anode, the ohmic electrode 5 is used as a cathode, and the Schottky electrode 4 brought into Schottky contact with the Schottky electrode 4 is n ^- type. When a voltage exceeding the barrier height of the contact portion with the drift layer 2 is applied, a current flows between the Schottky electrode 4 and the ohmic electrode 5. Specifically, a current flows in a contact portion between the Schottky electrode 4 and the n ⁻ -type drift layer 2 through a region that is not blocked by the depletion layer indicated by a broken line in FIG.

At this time, since the n-type impurity layer 6 is formed in the SiC semiconductor device of the present embodiment, the extension amount of the depletion layer extending from the p ⁺ -type impurity layer 3 toward the n ⁻ -type drift layer 2 side is the conventional structure. Smaller than That is, in comparison with the SiC semiconductor device having the conventional structure shown in FIG. 2, when the n-type impurity layer 6 is formed as in the present embodiment, the depletion layer is thereby reduced. Compared with the depletion layer indicated by the broken line in FIG. 2, the depletion layer shown has a smaller amount of extension at the portion extending from the side surface portion of the p ⁺ -type impurity layer 3 toward the n ⁻ -type drift layer 2. For this reason, the width of the current path is wider in this embodiment than in the conventional structure, and the resistance value in the forward direction per unit area can be reduced accordingly.

By thus along the side surface portion of the p ⁺ -type impurity layer 3 to form an n-type impurity layer 6, the side surface portion of the p ⁺ -type impurity layer 3 n ^- the spread of the depletion layer extending to the type drift layer 2 Can be small. Thereby, the width of the depletion layer formed by the PN junction can be narrowed, and the resistance value in the forward direction can be reduced. Since the resistance value in the forward direction can be reduced, the area of the p ⁺ -type impurity layer 3 per unit area of the SiC semiconductor device can be increased, and the surge resistance can be improved and the resistance value in the forward direction can be reduced. It is possible to achieve both.

In particular, in a wide band gap semiconductor such as SiC, since the built-in potential is large, the spread of the depletion layer increases, and accordingly, the forward current path is larger than the contact area between the Schottky electrode 4 and the n ⁻ -type drift layer 2. This reduces the area and increases the resistance value in the forward direction. However, according to the present embodiment, since the width of the depletion layer formed by the PN junction can be reduced, the above effect can be effectively obtained even in a wide band gap semiconductor.

When the depletion layer extending from the side surface of the p ⁺ -type impurity layer 3 to the n ⁻ -type drift layer 2 is reduced in size, the depletion layer completely depletes the adjacent p ⁺ -type impurity layers 3 during reverse bias. It may be impossible to generate reverse leakage current easily. However, with respect to the reverse leakage current, adjustment of the barrier height at the contact portion between the Schottky electrode 4 and the n ⁻ type drift layer 2, adjustment of the distance between the adjacent p ⁺ type impurity layer 3 and the n type impurity layer 6, Since the design can be made as appropriate by adjusting the concentration of the n-type impurity layer 6, it is possible to suppress the occurrence of reverse leakage current by adjusting them.

  Next, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG.

First, in the step shown in FIG. 3A, the n ⁻ type drift layer 2 is epitaxially grown on the main surface 1a of the n ⁺ type substrate 1. Subsequently, a mask 11 made of LTO (low-temperature oxide) or the like having a thickness of about 2 μm is disposed on the n ⁻ -type drift layer 2, and then a resist 12 is disposed on the mask 11, and photolithography etching is performed. In the process, a region where the p ⁺ type impurity layer 3 is to be formed in the mask 11 is opened.

Then, in the step shown in FIG. 3B, by performing multi-stage implantation with different ranges using the mask 11, p-type impurities such as aluminum and boron are ion-implanted and activated by heat treatment or the like. The p ⁺ type impurity layer 3 is formed by the above.

  Next, in the step shown in FIG. 3C, after removing the mask 11, a mask 13 having a film thickness of about 2 μm and made of LTO or the like is disposed again. Further, a resist 14 is arranged on the mask 13 and a region where the n-type impurity layer 6 is to be formed in the mask 13 is opened in the photolithography etching process.

  In the step shown in FIG. 3D, the n-type impurity such as nitrogen or phosphorus is removed by changing the ion implantation energy at a multi-stage implantation using this mask 13 and changing the range, for example, 30 to 700 keV. The n-type impurity layer 6 is formed by ion implantation and activation by heat treatment or the like.

Although the subsequent steps are not shown, after removing the mask 13, for example, a silicon oxide film is formed by plasma CVD, and then an insulating film is formed by performing a reflow process to perform a photolithography etching process. Then, an opening is formed in the insulating film. Then, a metal layer made of molybdenum, titanium, nickel or the like is formed on the insulating film including the inside of the opening and patterned. As a result, the portion in contact with the n ⁻ type drift layer 2 functions as an SBD 10 by being brought into Schottky contact, and the portion in contact with the p ⁺ type impurity layer 3 is brought into ohmic contact to extract hole carriers. A Schottky electrode 4 is formed that functions as a performer. Further, an ohmic electrode 5 is formed by forming a metal layer made of nickel, titanium, molybdenum, tungsten or the like on the back surface 1b side of the n ⁺ type substrate 1. Thereby, the SiC semiconductor device provided with SBD 10 shown in FIG. 1 is completed.

Although the case where the n-type impurity layer 6 is formed after forming the p ⁺ -type impurity layer 3 has been described here, the order may be reversed.

As described above, in the present embodiment, by along the side surface portion of the p ⁺ -type impurity layer 3 to form an n-type impurity layer 6, n from the side surface of the p ⁺ -type impurity layer 3 ^- type drift layer 2 The extent of the depletion layer extending to Thereby, the width of the depletion layer formed by the PN junction can be narrowed, and the resistance value in the forward direction can be reduced. Since the resistance value in the forward direction can be reduced, the area of the p ⁺ -type impurity layer 3 per unit area of the SiC semiconductor device can be increased, and the surge resistance can be improved and the resistance value in the forward direction can be reduced. It is possible to achieve both.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the configuration of the n-type impurity layer 6 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described. .

FIG. 4 is a cross-sectional view of an SiC semiconductor device including the SBD 10 according to the present embodiment. As shown in this figure, in this embodiment, in addition to the side surface portion of the p ⁺ -type impurity layer 3 to form an n-type impurity layer 6 and further along the bottom of the p ⁺ -type impurity layer 3.

With such a structure, in addition to the side surface of the p ⁺ -type impurity layer 3, the amount of depletion layer extending from the bottom to the n ⁻ -type drift layer 2 can be reduced. For this reason, as compared with the first embodiment, the position where the width of the current path becomes wider can be brought closer to the Schottky electrode 4, that is, the anode side. Therefore, the width of the current path between the anode and the cathode is expanded as compared with the first embodiment, and the resistance value in the forward direction can be further reduced. As a result, the effects shown in the first embodiment can be obtained.

In the SiC semiconductor device having such a structure, the method of forming the opening of the mask 13 in the first embodiment is changed, the portion corresponding to the p ⁺ -type impurity layer 3 is also formed as an opening, and ions of the n-type impurity are formed. It can be manufactured by increasing the injection range, but can also be manufactured by the following method. FIG. 5 is a cross-sectional view showing another method for manufacturing the SiC semiconductor device including the SBD 10 according to the present embodiment.

As shown in this figure, in the step shown in FIG. 5A, a mask 11 is formed as in the first embodiment, and in the step shown in FIG. For example, nitrogen is ion-implanted. Then, in the step shown in FIG. 5C, the mask 11 is used again to ion-implant a p-type impurity such as aluminum. Then, in the step shown in FIG. 5D, when ions implanted by heat treatment or the like are activated, aluminum hardly diffuses but nitrogen diffuses, so that the n type is formed so as to surround the p ⁺ type impurity layer 3. Impurity layer 6 is formed.

As described above, if the n-type impurity for forming the n-type impurity layer 6 has a larger diffusion due to heat treatment than the p-type impurity for forming the p ⁺ -type impurity layer 3, one mask is used. It becomes possible to form both the p ⁺ -type impurity layer 3 and the n-type impurity layer 6 only by 11, so that the manufacturing process can be simplified. Further, when the same mask 11 is used, the n-type impurity layer 6 and the p ⁺ -type impurity layer 3 can be formed at different positions even when oblique ion implantation is performed. The structure of the embodiment can be formed.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the configuration of the n-type impurity layer 6 is changed with respect to the second embodiment, and the other parts are the same as those of the second embodiment. Therefore, only the parts different from the second embodiment will be described. .

FIG. 6 is a cross-sectional view of an SiC semiconductor device including the SBD 10 according to the present embodiment. As shown in this figure, also in this embodiment, in addition to the side surface portion of the p ⁺ -type impurity layer 3, although an n-type impurity layer 6 and further along the bottom of the p ⁺ -type impurity layer 3, in the p ⁺ -type impurity layer 3 of the bottom portion 6a which is disposed below the n-type impurity layer 6, than the p ⁺ -type impurity layer 3 of the side surface portion which is formed in part 6b, n-type impurity concentration is darker Yes. In this way, if the n-type impurity concentration of the portion 6a disposed below the bottom of the p ⁺ -type impurity layer 3 in the n-type impurity layer 6 is made higher, the n-type impurity layer 6 is further removed from the bottom of the p ⁺ -type impurity layer 3 by n. The spread of the depletion layer extending to the ⁻ type drift layer 2 can be reduced, and the width of the current path can be further increased. Therefore, the effect shown in the first embodiment can be further obtained.

  The SiC semiconductor device having such a structure is basically manufactured by the same manufacturing method as in the second embodiment. However, when ion implantation is performed by multi-stage implantation, the dose amount of n-type impurities at a deep position. Should be larger than other positions.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. The present embodiment is a modification of the method of manufacturing the n-type impurity layer 6 with respect to the second embodiment. The other aspects are the same as those of the second embodiment, and therefore only the parts different from the second embodiment will be described. To do.

  FIG. 7 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device including the SBD 10 according to the present embodiment.

First, in the process shown in FIG. 7A, the same process as in FIG. 5A of the second embodiment is performed, and the mask 11 is arranged. At this time, a portion of the mask 11 corresponding to the planned formation positions of the p ⁺ -type impurity layer 3 and the n-type impurity layer 6 is opened. Then, in the step shown in FIG. 7 (b), using a mask 11 n ^- -type drift layer 2 is selectively etched, n in the formation planned location of the p ⁺ -type impurity layer 3 and the n-type impurity layer 6 ^- -type A recess 2 a is formed in the drift layer 2. Thereafter, the n-type impurity layer 6 is selectively epitaxially grown in the recess 2a formed in the n ⁻ -type drift layer 2 in the step shown in FIG. At this time, if the n ⁺ type substrate 1 having a C-plane main surface 1a is used, the surface of the n ⁻ -type drift layer 2 and the bottom surface of the recess 2a also become the C-plane, and the recess 2a of the n-type impurity layer 6 The n-type impurity concentration can be made higher in the portion epitaxially grown on the bottom surface than in the portion epitaxially grown on the side surface of the recess 2a, and the structure of the third embodiment can be obtained. Then, in the step shown in FIG. 7D, the SiC semiconductor device having the structure of the second embodiment can be manufactured by selectively epitaxially growing the p ⁺ -type impurity layer 3 in the remaining portion of the recess 2a. .

In this way, the p ⁺ -type impurity layer 3 and the n-type impurity layer 6 can be formed by epitaxial growth.

If the main surface 1a of the n ⁺ type substrate 1 is Si surface, the surface of the n ⁻ type drift layer 2 and the bottom surface of the recess 2a are also Si surfaces. In this case, the portion of the n-type impurity layer 6 epitaxially grown on the side surface of the recess 2a can have a higher n-type impurity concentration than the portion epitaxially grown on the bottom surface of the recess 2a. Therefore, in this case, n ^- -type Invite ask the same conditions as the film formation conditions of the drift layer 2 is epitaxially grown, n at the side surface of the recess 2a ^- higher impurity concentration than type drift layer 2, n at that portion It is also possible to constitute the type impurity layer 6. Of course, in this case, n ^- not under the same conditions as type drift layer 2, n ^- if so is n-type impurity concentration than the type drift layer 2 becomes thicker, the bottom surface in the portion which is formed on the side face of the recess 2a The n-type impurity layer 6 having an impurity concentration higher than that of the formed portion is formed. Even in this case, the same effect as in the first and second embodiments can be obtained.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In the present embodiment, the configuration of the n-type impurity layer 6 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described. .

FIG. 8 is a cross-sectional view of an SiC semiconductor device including the SBD 10 according to the present embodiment. As shown in this figure, also in this embodiment, the n-type impurity layer 6 is formed on the side surface portion of the p ⁺ -type impurity layer 3, but the n-type impurity layer 6 is located deep in the p ⁺ -type impurity layer 3. In other words, it is formed only at a position spaced apart from the Schottky electrode 4 and deeper than the surface of the n ⁻ type drift layer 2.

  With such a structure, the distribution of the depletion layer can be distributed, and the width of the current path can be gradually increased from the Schottky electrode 4, that is, from the anode side to the cathode side. As a result, the width of the current path can be further increased, and the effects shown in the first embodiment can be obtained.

  In the present embodiment, the case where the n-type impurity layer 6 is formed deeply with respect to the structure of the first embodiment has been described. However, the n-type impurity layer 6 is also applied to the second and third embodiments. The formation position of can be deepened.

(Other embodiments)
In the above embodiment, the SiC semiconductor device in which the first conductivity type is n-type and the second conductivity type is p-type has been described, but a structure in which each conductivity type is inverted may be used.

In the above embodiment, the n-type impurity layer 6 during each p ⁺ -type impurity layer 3 arranged in a stripe shape, but are disposed in contact with the p ⁺ -type impurity layer 3, have some distance May be good or they may overlap. Even when the p ⁺ -type impurity layer 3 is formed in a shape other than the stripe shape, if the n-type impurity layer 6 is disposed on the side of the substrate horizontal direction with respect to the p ⁺ -type impurity layer 3, p ⁺ The same effect as when the type impurity layer 3 is arranged in a stripe shape can be obtained.

Moreover, although the case where SiC was used as a wide band gap semiconductor was demonstrated in the said embodiment, this invention is applicable also to the semiconductor device using another wide band gap semiconductor and general Si. However, since Si has a small built-in potential, leakage current is likely to occur when a high concentration p ⁺ -type impurity layer 3 is provided. However, in the case of a wide band gap semiconductor, the built-in potential is large and a high concentration p ⁺ -type impurity layer is formed. 3 is particularly effective when the present invention is applied because leak current hardly occurs.

1 n ⁺ type substrate 1a main surface 1b back surface 2 n ⁻ type drift layer 2a recess 3 p ⁺ type impurity layer 4 Schottky electrode 5 ohmic electrode 6 n type layer 10 SBD

Claims (9)

A substrate (1) having a main surface (1a) and a back surface (1b) and made of a first conductivity type semiconductor;
A drift layer (2) made of a first conductivity type semiconductor formed on the main surface (1a) of the substrate (1) and having a lower impurity concentration than the substrate (1);
A Schottky electrode (4) disposed on the drift layer (2) and formed in Schottky contact with the surface of the drift layer (2) in the cell portion of the drift layer (2);
An ohmic electrode (5) formed on the back surface (1b) of the substrate (1);
A second conductivity type impurity layer (3) provided in a surface layer portion of the drift layer (2) and configured by a second conductivity type semiconductor so as to be in contact with the Schottky electrode (4);
A first conductivity type impurity layer (6) formed laterally in the substrate horizontal direction of the second conductivity type impurity layer (3) and having a higher impurity concentration than the drift layer (2); A semiconductor device comprising a Schottky barrier diode.   The first conductivity type impurity layer (6) includes a portion (6b) disposed laterally in the substrate horizontal direction of the second conductivity type impurity layer (3) and a bottom portion of the second conductivity type impurity (3). The semiconductor device having a Schottky barrier diode according to claim 1, wherein the semiconductor device has a portion (6 a) disposed below.   The first conductivity type impurity layer (6) is located closer to the bottom of the second conductivity type impurity (3) than the portion (6b) of the second conductivity type impurity layer (3) disposed on the lateral side of the substrate. 3. The semiconductor device having a Schottky barrier diode according to claim 2, wherein the lower portion (6a) has a higher impurity concentration.   The first conductivity type impurity layer (6) is spaced apart from the Schottky electrode (4) and formed at a position deeper than the surface of the drift layer (2). A semiconductor device comprising the Schottky barrier diode according to any one of the above. A substrate (1) having a main surface (1a) and a back surface (1b) and made of a first conductivity type semiconductor;
A drift layer (2) made of a first conductivity type semiconductor formed on the main surface (1a) of the substrate (1) and having a lower impurity concentration than the substrate (1);
A Schottky electrode (4) disposed on the drift layer (2) and formed in Schottky contact with the surface of the drift layer (2) in the cell portion of the drift layer (2);
An ohmic electrode (5) formed on the back surface (1b) of the substrate (1);
A second conductivity type impurity layer (3) provided in a surface layer portion of the drift layer (2) and configured by a second conductivity type semiconductor so as to be in contact with the Schottky electrode (4);
A first conductivity type impurity layer (6) formed laterally in the substrate horizontal direction of the second conductivity type impurity layer (3) and having a higher impurity concentration than the drift layer (2); In a method for manufacturing a semiconductor device including a Schottky barrier diode,
Forming the drift layer (2) on the substrate (1);
A first mask (11) is disposed on the surface of the drift layer (2), a region where the second conductivity type impurity layer (3) is to be formed is opened in the first mask (11), and the first mask is formed. Forming a second conductivity type impurity layer (3) by ion-implanting a second conductivity type impurity using a mask (11);
A second mask (11, 13) is disposed on the surface of the drift layer (2), and the formation region of the first conductivity type impurity layer (6) of the second mask (11, 13) is opened. By ion-implanting the first conductivity type impurity using the second mask (11, 13), the first conductivity type impurity layer (6) is formed at a position lateral to the substrate horizontal direction of the second conductivity type impurity layer (3). And a step of forming a semiconductor device including a Schottky barrier diode.   The first mask and the second mask used in the step of forming the second conductivity type impurity layer (3) and the step of forming the first conductivity type impurity layer (6) are the same mask (11), and As the first conductivity type impurity used for forming the first conductivity type impurity layer (6), a material having a larger diffusion due to heat treatment than the second conductivity type impurity used for forming the second conductivity type impurity layer (3). A method for manufacturing a semiconductor device comprising a Schottky barrier diode according to claim 5. A substrate (1) having a main surface (1a) and a back surface (1b), made of silicon carbide of the first conductivity type, and wherein the main surface (1a) is a C-plane;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the main surface (1a) of the substrate (1) and having a lower impurity concentration than the substrate (1);
A Schottky electrode (4) disposed on the drift layer (2) and formed in Schottky contact with the surface of the drift layer (2) in the cell portion of the drift layer (2);
An ohmic electrode (5) formed on the back surface (1b) of the substrate (1);
A second conductivity type impurity layer (3) provided in a surface layer portion of the drift layer (2) and configured by a second conductivity type semiconductor so as to be in contact with the Schottky electrode (4);
A first conductivity type impurity layer (6) formed on the side of the substrate in the horizontal direction and below the bottom of the second conductivity type impurity layer (3) and having a higher impurity concentration than the drift layer (2); In a method for manufacturing a silicon carbide semiconductor device provided with a Schottky barrier diode,
Forming the drift layer (2) on the substrate (1);
A mask (11) is disposed on the surface of the drift layer (2), and regions where the second conductivity type impurity layer (3) and the first conductivity type impurity layer (6) are to be formed in the mask (11). Forming a recess (2a) by opening the opening and etching the drift layer (2) using the mask (11);
Forming the first conductivity type impurity layer (6) by selectively performing epitaxial growth in the recess (2a);
Forming a second conductivity type impurity layer (3) by selectively performing epitaxial growth on the surface of the first conductivity type impurity layer (6) in the recess (2a). A method of manufacturing a silicon carbide semiconductor device including a Schottky barrier diode. A substrate (1) having a main surface (1a) and a back surface (1b), made of silicon carbide of the first conductivity type, and wherein the main surface (1a) is an Si surface;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the main surface (1a) of the substrate (1) and having a lower impurity concentration than the substrate (1);
A Schottky electrode (4) disposed on the drift layer (2) and formed in Schottky contact with the surface of the drift layer (2) in the cell portion of the drift layer (2);
An ohmic electrode (5) formed on the back surface (1b) of the substrate (1);
A second conductivity type impurity layer (3) provided in a surface layer portion of the drift layer (2) and configured by a second conductivity type semiconductor so as to be in contact with the Schottky electrode (4);
A first conductivity type impurity layer (6) formed on the side of the substrate in the horizontal direction and below the bottom of the second conductivity type impurity layer (3) and having a higher impurity concentration than the drift layer (2); In a method for manufacturing a silicon carbide semiconductor device provided with a Schottky barrier diode,
Forming the drift layer (2) on the substrate (1);
A mask (11) is disposed on the surface of the drift layer (2), and regions where the second conductivity type impurity layer (3) and the first conductivity type impurity layer (6) are to be formed in the mask (11). Forming a recess (2a) by opening the opening and etching the drift layer (2) using the mask (11);
Forming the first conductivity type impurity layer (6) by selectively performing epitaxial growth in the recess (2a);
Forming a second conductivity type impurity layer (3) by selectively performing epitaxial growth on the surface of the first conductivity type impurity layer (6) in the recess (2a). A method of manufacturing a silicon carbide semiconductor device including a Schottky barrier diode.   The carbonization with a Schottky barrier diode according to claim 8, wherein in the step of forming the first conductivity type impurity layer (6), epitaxial growth is performed under the same conditions as the formation of the drift layer (2). A method for manufacturing a silicon semiconductor device.

Images