JP2010212763A - Data reproduction device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data reproduction device capable of performing high-precision phase adjustment on a regenerated clock and holding phase precision after the phase adjustment without making a circuit scale large nor complicated and, for example, even when a frequency difference between a transmission clock and a reception clock is large, when a reception frame period is long, etc. <P>SOLUTION: A regenerated clock generating circuit 5 of the data reproduction device 2 is equipped with: a frequency difference detecting circuit 14 which generates frequency difference information by detecting the frequency difference between the frequency of a data clock signal of received data and the frequency of a reference clock signal as a clock signal associated with reproduction processing on the data; and a clock generating circuit 17 which generates the regenerated clock for sampling the data based upon the reference clock signal, and performs the phase adjustment on the regenerated clock signal at a point of time of phase adjustment implementation based upon the frequency difference information, phase information, and elapsed time information. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data reproducing apparatus that receives and processes a data signal having jitter and reproduces data, and more particularly to a data reproducing apparatus that generates a reproduction clock signal used for reproducing data.

  A receiving apparatus that receives a data signal normally starts a frequency sweep when the frequency of the target signal is not in the intermediate frequency IF (Intermediate Frequency) band, and when the target signal is captured by this sweep, the frequency sweep is stopped. At the same time, the function is switched from the frequency sweep function to the AFC function so that an AFC (Automatic Frequency Control) circuit becomes effective.

  In most cases, since the frequency error remains at the time when the switching described above is performed, the residual frequency error is eliminated by the function of the AFC circuit. Since the time required to complete the correction process related to the residual frequency error is determined by the response characteristic of the AFC circuit itself, the length of the synchronization signal placed at the head of the packet is the response time of the AFC circuit. It is set in consideration.

  Note that when the frequency adjustment method using the AFC circuit as described above is employed, an increase in scale and complexity of the circuit is inevitable.

  By the way, as a frequency adjustment method other than the frequency adjustment method by the AFC circuit, for example, Patent Literature 1 discloses the following technique.

  That is, Patent Document 1 discloses a data reception device that asynchronously receives serial data for each frame including synchronous data and valid data transmitted from a transmission side, and receives reception at substantially the same frequency as the transmission side clock signal. A reception clock signal generation means for generating a clock signal asynchronously with the transmission side clock signal, and a delay clock signal generation for generating a plurality of delay clock signals having the same frequency as the reception clock signal and different phases based on the reception clock signal A delayed clock signal is selected from each delayed clock signal for each frame based on the means and synchronization data, and a delayed clock signal whose phase substantially matches that of the transmitting clock signal at the beginning bit time of valid data is selected. And the frequency difference of the received clock signal with respect to the transmitting clock signal, A phase adjustment amount acquisition means for acquiring a phase adjustment amount in each frame with respect to a selection result of the extended clock signal selection means; and a delay clock signal having a phase different from the delay clock signal selected by the delay clock signal selection means by a phase adjustment amount, A data receiving device is disclosed that includes selection means for selecting as a synchronous clock signal for reading valid data in the frame based on the selection result and the phase adjustment amount.

  That is, in the data receiving apparatus disclosed in Patent Document 1, a plurality of clock signal groups having different phases from the received clock are generated for the phase adjustment of the recovered clock, and then transmitted at the head of the received frame. The phase information of the clock is detected, and phase adjustment amount information in the reception frame is created based on the frequency difference between the transmission clock and the reception clock. Then, using the phase information and the phase amount adjustment information, the recovered clock signal used in the received frame is selected from the clock signal group to adjust the phase of the recovered clock.

  According to the technique disclosed in this Patent Document 1, it is possible to avoid an increase in the scale and complexity of the circuit that occurs when the frequency adjustment method using the AFC circuit as described above is employed.

Japanese Patent No. 3988291

  However, the technique disclosed in Patent Document 1 is merely a technique on how to select the phase of the recovered clock used in the received frame. Therefore, in the technique disclosed in Patent Document 1, for example, when the frequency difference between the transmission clock and the reception clock is large or when the reception frame period is long, there is a possibility that the phase of the reproduction clock is shifted. high.

  The present invention has been made in view of the above circumstances, and does not cause an increase in circuit scale and complexity, and for example, when the frequency difference between the transmission clock and the reception clock is large or when the reception frame period is long. It is an object of the present invention to provide a data recovery device that enables highly accurate phase adjustment of a recovered clock and retention of phase accuracy after phase adjustment even in cases.

In order to achieve the above object, a data reproducing apparatus according to the first aspect of the present invention provides:
A data reproduction device that receives data transmitted from a transmitter and reproduces the received data according to a reproduction clock signal,
A frequency difference detection unit that detects a frequency difference between a frequency of a data clock signal in the data and a frequency of a reference clock signal that is a clock signal related to the data reproduction process, and creates frequency difference information;
A phase information detector that detects phase information of a data clock signal in the data and creates phase information;
An elapsed time information creation unit for creating elapsed time information indicating a time from a phase information detection time point by the phase information detection unit to a phase adjustment execution time point for performing phase adjustment of the recovered clock signal;
A reproduction clock signal for sampling the data is generated based on the reference clock signal, and the reproduction is performed based on the frequency difference information, the phase information, and the elapsed time information at the time of the phase adjustment. A regenerated clock generator for performing phase adjustment of the clock signal;
It is characterized by comprising.

In order to achieve the above object, a data reproducing apparatus according to the second aspect of the present invention provides:
A data reproduction device that receives data transmitted from a transmitter and reproduces the received data according to a reproduction clock signal,
A clock frequency information acquisition unit that acquires data clock frequency information indicating a frequency of a data clock signal included in the data;
A reference clock frequency information storage unit that stores reference clock frequency information indicating a frequency of a reference clock signal related to the data reproduction process;
A frequency difference information creating unit that creates frequency difference information indicating a frequency difference between the data clock signal and the reference clock signal based on the data clock frequency information and the reference clock frequency information;
A phase information detector for detecting phase information of a data clock signal in the data, and an elapsed time indicating a time from a phase information detection time by the phase information detector to a phase adjustment execution time for performing phase adjustment of the recovered clock signal An elapsed time information creation unit for creating information;
Based on the reference clock signal, a recovered clock signal for sampling the data is created, and at the time of the phase adjustment, the recovered clock is based on the frequency difference information, the phase information, and the elapsed time information. A regenerated clock generator for performing phase adjustment of the signal;
It is characterized by comprising.

In order to achieve the above object, a data reproducing apparatus according to the third aspect of the present invention provides:
A data reproduction device that receives data transmitted from a transmitter and reproduces the received data according to a reproduction clock signal,
Data clock frequency for storing transmitter ID information for identifying the transmitter included in the data and data clock frequency information indicating the frequency of the data clock signal of the data in association with each transmitter An information storage unit;
A reference clock frequency information storage unit that stores reference clock frequency information indicating a frequency of a reference clock signal related to the data reproduction process;
A frequency difference information creating unit that creates frequency difference information indicating a frequency difference between the data clock signal and the reference clock signal based on the data clock frequency information and the reference clock frequency information;
A phase information detector for detecting phase information of a data clock signal in the data;
An elapsed time information creation unit that creates elapsed time information indicating a time from a phase information detection time point by the phase information detection unit to a phase adjustment execution time point for performing phase adjustment of the recovered clock signal;
Based on the reference clock signal, a recovered clock signal for sampling the data is created, and at the time of the phase adjustment, the recovered clock is based on the frequency difference information, the phase information, and the elapsed time information. A regenerated clock generator for performing phase adjustment of the signal;
It is characterized by comprising.

  According to the present invention, the circuit scale is not increased and complicated, and even when the frequency difference between the transmission clock and the reception clock is large, or when the reception frame period is long, etc. It is possible to provide a data reproducing apparatus that can maintain accurate phase adjustment and phase accuracy after phase adjustment.

The figure which shows the example of 1 structure of the data reproducing device which concerns on 1st Embodiment of this invention The figure which shows the example of 1 structure of the reception data produced | generated in RF circuit. The figure which shows the example of 1 structure of a reproduction | regeneration clock generation circuit. The figure which shows the example of 1 structure of a UW detection circuit. The figure which shows the example of 1 structure of a frequency difference detection circuit. The figure which shows the example of 1 structure of a phase information detection circuit. The figure which shows the operation example of a phase information detection circuit. The figure which shows the operation example of a phase information detection circuit. The figure which shows the example of 1 structure of a clock generation circuit. The figure which shows an example of the method of correct | amending the phase of a reproduction | regeneration clock based on a frequency difference signal and an elapsed time signal. The figure which shows the example of 1 structure of the 2nd reproduction | regeneration clock generation circuit with which the data reproduction apparatus which concerns on 2nd Embodiment of this invention comprises. The figure which shows the example of 1 structure of a 2nd phase information detection circuit. The figure explaining the histogram creation process by a phase information detection circuit. The figure explaining the creation processing of the elapsed time signal when the phase adjustment of the reproduction clock is performed only immediately after the synchronization pattern (UW2) of the next data block. Elapsed time signal when the phase of the recovered clock is adjusted immediately after the synchronization pattern (UW2) of the next data block (at (19)) and at the center of the data block (at (20)) The figure explaining 25 preparation processing. After adjusting the phase of the recovered clock immediately after the synchronization pattern (UW2) of the next data block (at time (19)), the subsequent steps are performed in accordance with the frequency difference in the same manner as in the data recovery device according to the first embodiment. The figure explaining the creation process of the elapsed time signal 25 in the case of performing phase adjustment at an adjustment interval. The figure which shows the example of 1 structure of the data reproduction apparatus which concerns on 3rd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram illustrating a configuration example of a data reproducing apparatus according to the first embodiment.

  In the first embodiment, the data reproduction device 2 according to the first embodiment is used as a receiver in an image communication system that intermittently communicates image data acquired by photographing on the transmitter 1 side in units of frames. The case where it is applied will be described as an example.

  As shown in FIG. 1, the data reproduction device 2 includes an RF circuit 3, a sampling circuit 4, a reproduction clock generation circuit a5, and a data processing circuit 6.

  In the data reproduction device 2, the communication data is demodulated and binarized by the RF circuit 3 and converted into received data 7. The reception data 7 is supplied to the sampling circuit 4 and the reproduction clock generation circuit a5.

  The reproduction clock generation circuit a5 creates a reproduction clock 8 for sampling the reception data 7, and supplies it to the sampling circuit 4 and the data processing circuit 6. Further, the reproduction clock generation circuit a5 creates a UW1_2 detection signal 10 that is a detection signal of a synchronization pattern (UW: unique word) and supplies it to the data processing circuit 6.

  In the sampling circuit 4, the reception data 7 is sampled by the reproduction clock 8 to generate reproduction data 9, which is output to the data processing circuit 6. In the data processing circuit 6, the reconstructed data 9, the regenerated clock 8, and the UW1_2 detection signal 10 are used to reconstruct an image and create a file.

  FIG. 2 is a configuration example of received data 7 used in the data reproducing device according to the first embodiment.

  In the first embodiment, the received data 7 is communicated collectively in units of frames, and communication is performed intermittently after a pause period.

  The received data 7 is composed of a plurality of data blocks, and the types of data blocks used in this embodiment are two types, that is, a transmitter information block and an image data block as shown in the figure. A synchronization pattern (UW: unique word) is added to the head of each data block.

  The transmitter information block is a block at the head of the frame, and is composed of a synchronization pattern (UW_1) indicating that it is a transmitter information block, and frame information data such as a transmitter identification number and a time stamp.

  The image data block is a block transmitted subsequent to the transmitter information block, and is composed of a synchronization pattern (UW_2) indicating that it is an image block and image data divided in predetermined units.

  The synchronization pattern is data composed of a pattern that does not occur in the image data. In the first embodiment, a case where the configuration is 1 frame = 500 data blocks, 1 data block = 10000 bits (UW: 100 bits, transmitter information / image data: 9900 bits) will be described as an example. Further, the description will be made assuming that the data rate of the reception data 7 is 10 Mbps.

  FIG. 3 is a configuration diagram of the reproduction clock generation circuit a5.

  The reproduction clock generation circuit a5 includes an oscillator 11, a frequency multiplication circuit 12, a UW detection circuit 13, a frequency difference detection circuit 14, a phase information detection circuit a15, an elapsed time signal generation circuit 16, and a clock generation circuit 17. Have.

  The oscillator 11 is an oscillator that oscillates at the same frequency (10 MHz) as the data rate (10 Mbps) of the reception data 7, and creates a reference clock 18. The reference clock 18 is supplied to the frequency multiplication circuit 12 and the elapsed time signal generation circuit 16.

  The frequency multiplication circuit 12 is a PLL circuit that creates an output obtained by multiplying an input signal by 20 times the frequency. In this embodiment, the frequency multiplication circuit 12 outputs a 200 MHz clock signal that is 20 times the frequency as the operation clock 19.

  The reception data 7 is added to the UW detection circuit 13 and the phase information detection circuit a15.

  The UW detection circuit 13 is a circuit that detects a synchronization pattern in the reception data 7 by correlation calculation.

  In the correlation calculation, the received data 7 is sampled using the calculation clock 19, and the sampling result is compared with the synchronization pattern. In the correlation calculation, the synchronization pattern detection timing signal is set to “1” (HI) when the received data 7 completely matches the synchronization pattern. For this reason, the reception timing of the last 1 bit of the synchronization pattern is the synchronization pattern detection timing.

  From the UW detection circuit 13, the UW1_2 detection signal 10 (two in the first embodiment) for outputting the detection timing of UW1 and UW2 through separate signal lines and the detection timing of UW1 and UW2 are combined into one signal line. The UW detection signal 20 that is output at is output.

  The UW detection signal 20 is supplied to the frequency difference detection circuit 14 and the phase information detection circuit a15.

  The frequency difference detection circuit 14 is a circuit for measuring the frequency difference between the reference clock 18 and the data clock of the reception data 7 by measuring the UW detection interval using the arithmetic clock 19. The frequency difference information 21 indicating the frequency difference is output to the clock generation circuit 17.

  The phase information detection circuit a15 is a circuit that creates a signal for determining the phase of the recovered clock 6 from the detection timing and detection width of UW. The signals generated by the phase information detection circuit a15 are the phase counter signal a22, the phase detection signal a23, and the generation timing signal a24. The phase counter signal a22 and the phase detection signal a23 are output to the clock generation circuit 17. The creation timing signal a24 is output to the elapsed time signal creation circuit 16.

  The elapsed time signal creation circuit 16 creates an elapsed time signal 25 indicating the elapsed time from the time when the phase information indicated by the phase counter signal a22 and the phase detection signal a23 output from the phase information detection circuit a15 is created. It is. The elapsed time signal 25 is output to the clock generation circuit 17.

  The clock generation circuit 17 uses the frequency difference information 21 and the elapsed time signal 25 to create phase shift information generated according to the frequency difference and the elapsed time. Further, using the phase detection signal a23 indicating the detection phase at the time of phase detection and the phase shift information, reproduced clock phase information whose value is adjusted according to the elapsed time is created.

  The clock generation circuit 17 compares the value of the phase counter signal a22 with the value of the reproduction clock phase information to determine the phase of the reproduction clock 8. Details of the operation of the clock generation circuit 17 will be described later with reference to FIGS.

  FIG. 4 is a configuration diagram of the UW detection circuit 13 having a function of detecting a synchronization pattern (UW: unique word) from the received data 7. The UW detection circuit 13 includes a UW register 26 and a correlation detection circuit 27.

  Specifically, the UW detection circuit 13 is a circuit that detects a synchronization pattern (UW: unique word) from the received data 7. Specifically, the UW detection circuit 13 performs a correlation operation between the received data 7 and the synchronization pattern, and sets the detection signal to “HI” when they match.

  The correlation detection circuit 27 receives the received data 7 and the synchronization pattern from the UW register 26, and performs correlation detection at the timing of the operation clock 19. As described above, since the arithmetic clock 19 is set to a frequency 20 times the data rate of the received data 7, the correlation detection is performed 20 times in a 1-bit period. Therefore, the detection signal has a signal width of 1/20 to 1 bit according to the jitter amount in the reception data 7. As described above, the correlation detection circuit 27 outputs the UW1_2 detection signals 10 (two) for individually outputting the detection timings of UW1 and UW2, and the UW detection signal 20 for outputting the detection timings of UW1 and UW2 collectively.

  FIG. 5 is a configuration diagram of the frequency difference detection circuit 14. The frequency difference detection circuit 14 is a circuit that measures the frequency difference between the reference clock 18 and the data clock of the received data 7.

  The frequency difference detection circuit 14 includes a counter control circuit 28, an interval measurement counter 29, a reference value buffer 30, and a difference detection circuit 31. The UW detection signal 20 supplied from the correlation detection circuit 27 is input to the counter control circuit 28.

  The frequency difference detection circuit 14 measures the frequency difference between the data clock of the reception data 7 and the reference clock 18 by measuring the elapsed time of the UW at a predetermined interval using the arithmetic clock 19.

  Hereinafter, a case where the frequency difference between the data clock of the received data 7 and the reference clock 18 is 40 ppm (data clock: 10 MHz, reference clock: 10.0004 MHz) will be described as an example.

  The counter control circuit 28 outputs a counter control signal for performing control (reset, start, stop) of the interval measurement counter 29 based on the UW detection signal 20. An operation clock 19 is added to the counter control circuit 28 as a count clock signal.

  In the first embodiment, the interval measurement counter 29 counts the time when 100 UWs have elapsed with reference to the operation clock 19.

  When the frequency difference is 40ppm, the output of the interval measurement counter 29 is 100 * 10000 * 20 * 1.00004 = 2000800 from the above conditions, and the difference 800 from the output "2000000" of the reference value buffer 30 is converted into one data block equivalent The value (+8) obtained by (1/100) is output as the value of the frequency difference signal 21 that is the output of the difference detection circuit 31.

  In the above description, an example is shown in which the frequency difference is measured using the UW detection interval in one frame, but it is also possible to obtain the frequency difference by measuring the frame interval using UW1 at the head of the frame. In this case, as in the above method, the interval at which UW1 is detected is measured by the interval measurement counter 29, the amount corresponding to the frame interval is set in the reference value buffer 30, and the difference is obtained to determine the frequency difference. become. Details are the same as in the case of counting UW by 100, and the description is omitted.

  FIG. 6 is a configuration diagram of the phase information detection circuit a15.

  The phase information detection circuit a15 includes an edge detection circuit a32, a phase counter a33, a UW period measurement circuit 34, and a phase setting circuit 35.

  The UW detection signal 20 is applied to the edge detection circuit a32, and the rising edge pulse signal indicating the position of the rising edge of the UW detection signal 20 is applied to the phase counter a33 and the UW period measurement circuit 34 and output as the creation timing signal a24. The

  Further, a falling edge pulse signal indicating the position of the falling edge is applied to the UW period measurement circuit 34.

  In the phase counter a33, the counter value is reset by the rising edge pulse signal, and thereafter, the counter value is counted up at the timing of the operation clock 19, and when the count value reaches “19”, it returns to “0” at the next timing. The count value is output as the phase counter signal a22.

  The UW period measurement circuit 34 measures the width of the UW detection signal 20 by counting the interval from the rising edge pulse signal to the falling edge pulse signal using the arithmetic clock 19, and the measurement result is obtained as a UW width signal. To the phase setting circuit 35.

  The phase setting circuit 35 creates and outputs a phase detection signal a23 from the UW width signal.

  7 and 8 are diagrams for explaining the operation of the phase information detection circuit a15.

  FIG. 7 shows the operation of the phase information detection circuit a15 when the reception data 7 is less deteriorated and the detection width of the UW detection signal 20 is wide.

  For example, when the detection width of the UW detection signal 20 is 19 counts, the phase counter a33 reset at the rising edge position ((1)) of the UW detection signal 20 repeats the count operation at the timing shown in the figure. In this case, the optimum position as the rising edge position of the reproduction clock 8 is a position where the count value of the phase counter a33 is “9” as shown in the figure.

  The UW period measurement circuit 34 outputs “19” as the count value. The phase setting circuit 35 sets the value of the phase detection signal a23 to “9” (19/2: remainder is rounded down) according to the UW width signal = 19. In the case of the above setting, the clock generation circuit 17 sets the phase of the recovered clock 8 for the first bit to a phase in which the values of the phase counter signal a22 and the phase detection signal a23 that are the outputs of the phase counter a33 match. Regenerated clock 8 is output.

  FIG. 8 shows the operation of the phase information detection circuit a15 when the reception data 7 is greatly deteriorated and the detection width of the UW detection signal 20 is narrow.

  For example, when the detection width of the UW detection signal 20 is 7 counts, the phase counter a33 reset at the rising edge position ((1)) of the UW detection signal 20 repeats the counting operation at the timing shown in the figure. In this case, the optimum position as the rising edge position of the reproduction clock 8 is a position where the count value of the phase counter a33 is “3” as shown in the figure.

  The UW period measurement circuit 34 outputs “7” as the count value. The phase setting circuit 35 sets the value of the phase detection signal a23 to “3” (7/2: remainder is rounded down) according to the UW width signal = 7. In the case of the above setting, the clock generation circuit 17 sets the phase of the recovered clock 8 for the first bit to a phase in which the values of the phase counter signal a22 and the phase detection signal a23 that are the outputs of the phase counter a33 match. Regenerated clock 8 is output.

  FIG. 9 is a configuration diagram of the clock generation circuit 17.

  The clock generation circuit 17 includes a correction phase amount creation circuit 36, a phase correction circuit 37, and a comparison circuit 38.

  The comparison circuit 38 compares the phase counter signal a22 supplied from the phase information detection circuit a15 with the reproduction clock phase information from the phase correction circuit 37, and if they match, the reproduction clock 8 is set to “1”. The phase of the recovered clock 8 is determined by outputting as (HI).

  The phase correction circuit 37 is added with the phase detection signal a23 supplied from the phase information detection circuit a15 and the phase shift information from the corrected phase amount generation circuit 36, and the phase shift information is added to the value indicated by the phase detection signal a23. The reproduced clock phase information created by adding the indicated values is output to the comparison circuit 38.

  The correction phase amount generation circuit 36 receives the frequency difference signal 21 output from the frequency difference detection circuit 14 and the elapsed time signal 25 output from the elapsed time signal generation circuit 16, and uses both signals to generate a frequency. Phase shift information generated according to the difference and the elapsed time is created.

  A method of adjusting the phase of the recovered clock 8 using the frequency difference signal 21 and the elapsed time signal 25 will be described with reference to FIG.

  For example, as described above, when the frequency difference between the data clock of the reception data 7 and the reference clock 18 is 40 ppm, the value of the frequency difference signal 21 is output as “+8”. This indicates that a phase shift of +8 clocks occurs in the operation clock 19 during the data block period (because the frequency of the recovered clock 8 is higher, the count value becomes larger at the same time. If the phase of the recovered clock 8 is shifted to the larger value of the phase counter a33, the phase of the data clock can be matched).

  The elapsed time signal 25 indicates the time elapsed from the rising edge position of the UW detection signal 20 (calculation clock count value). As described above, since one data block is 10000 bits and 20 counts are performed in one bit period, when the elapsed time is one data block period, the value of the elapsed time signal 25 is 20000.

  The correction phase amount generation circuit 36 calculates (the value of the frequency difference signal 21 * the elapsed time signal 25/2000000) and outputs the result (the remainder is rounded down).

  As shown in FIG. 10, the phase detection signal a23 is set immediately after UW2 detection ((7)). At this time, in the above example, the elapsed time signal 25 is set to “1” and the frequency difference signal 21 is set to “+8”. The output of the correction phase amount creating circuit 36 from the time point (7) to the period after 250,000 counts (1250 bits) ((8)) is “0”. The output of the correction phase amount generation circuit 36 during the period from 250,000 counts (1250 bits) ((8)) to 500000 counts ((9)) becomes “+1”. At this time, the output of the phase correction circuit 37 becomes a value obtained by adding “+1” to the value of the phase detection signal a23, and accordingly, the phase of the recovered clock 8 is corrected and output.

  Thereafter, the correction process is performed in the same manner, and “+7” is the output of the correction phase amount generation circuit 36 during the period from (14) to (15) in the figure.

  When the detection of UW2 is performed again at the time (15), and the detection is performed, the phase detection signal a23 and the elapsed time signal 25 are set as described above. If the received data 7 deteriorates and jitter becomes large and UW2 cannot be detected, the phase adjustment starting from (7) is continued, and the correction phase amount creation circuit 36 in the period (15) to (16) The output is “+8”. This process is continued until a new UW2 is detected.

  Through the above processing, the recovered clock 8 is phase-adjusted based on the recovered clock phase information set using the phase counter signal a22 and the phase detection signal a23 set immediately after UW2 detection, and then the frequency difference signal 21 and the elapsed time The phase is appropriately adjusted based on the recovered clock phase information corrected by the phase shift information created from the time signal 25.

  Further, for example, when the frequency difference is 20 ppm, which is half, the frequency difference signal 21 is also “+4”, which is half, and the cycle in which the output of the correction phase amount generation circuit 36 changes is doubled. That is, the output during the period from (7) to (9) is “0”, and the output during the period from (9) to (12) is “+1”.

  As described above, according to the first embodiment, the circuit scale is not increased and complicated, and for example, when the frequency difference between the transmission clock and the reception clock is large, or when the reception frame period is long, etc. Even so, it is possible to provide a data recovery device that enables highly accurate phase adjustment of the recovered clock and retention of phase accuracy after phase adjustment.

  That is, according to the data recovery device of the first embodiment, after performing phase adjustment on the recovered clock, phase correction is performed according to the frequency difference between the transmission data clock and the reference clock that is the source of the recovered clock. This makes it possible to maintain the phase accuracy of the recovered clock after phase adjustment without synchronizing the frequency of the reference clock to the transmission data clock.

[Second Embodiment]
A data reproducing apparatus according to the second embodiment of the present invention will be described with reference to FIGS.

  The second embodiment is different from the data reproducing apparatus according to the first embodiment in the phase information detection method and the phase correction information update timing for performing phase correction.

  In the second embodiment, the phase correction of the recovered clock 8 for the transmitter information block that is the first data block of the frame is performed in the same manner as in the first embodiment, and the phase correction for the second and subsequent image data blocks is performed. This is done by measuring the phase distribution (histogram) of the data phase change point (edge) in the previous data block, finding the center of the distribution, and adjusting the phase of the recovered clock to a phase that is a predetermined amount away from the center. .

  FIG. 11 is a configuration diagram of the reproduction clock generation circuit b39.

  The reproduction clock generation circuit b39 includes a phase information detection circuit b40 that creates information for phase adjustment of the second and subsequent blocks in the reproduction clock generation circuit 5 in the first embodiment, and the first block and the second and subsequent blocks. A switching circuit 41 for switching information for phase adjustment is added.

The switching circuit 41 includes a phase counter signal a22, a phase detection signal a23, a creation timing signal a24 output from the phase information detection circuit a15, and a phase counter signal b42 output from the phase information detection circuit b40. A signal b43 and a creation timing signal b44 are added.

  The configuration of the clock generation circuit 17 is the same as that of the first embodiment, but the phase counter signal a22 / phase counter signal b42 is selected by the switching circuit 41 and added as the selected phase counter signal 46. Detection signal a23 / phase detection signal b43 is selected and added as phase detection signal 47 after selection.

  In the elapsed time signal creation circuit 16, the creation timing signal a24 / creation timing signal b44 is selected by the switching circuit 41 and added as the creation timing signal 48 after selection. Further, switching timing information 45 is output to the switching circuit 41 from the phase information detection circuit b40.

  In the switching circuit 41, the output of the reproduction clock generation circuit 5 is selected in the first block, and the output from the reproduction clock generation circuit b39 is selected in the second and subsequent blocks, and is output to the clock generation circuit 17 and the elapsed time signal generation circuit 16. The

  Since the operation of the first block is the same as that of the first embodiment, the operation after the second block will be described here.

  FIG. 12 is a configuration diagram of the phase information detection circuit_b40.

  The phase information detection circuit_b40 is different from the phase information detection circuit a15 in that the edge phase in the reception data 7 is used to detect the phase information. Therefore, the received data 7 is used in place of the UW detection signal 20 as an input to the phase information detection circuit_b40.

  Similarly to the phase information detection circuit a15, the output signals are the phase counter signal b42, the phase detection signal b43, and the creation timing signal b44. Also, switching timing information 45 to the switching circuit 41 is output.

  The edge detection circuit b49 is a circuit that detects both rising / falling edges of the received data 7 and generates an edge signal. The generated edge signal is input to the AND gate block 50.

  The phase gate signal generation circuit 53 divides the 1-bit period into 20 partial phases, and generates 20 gate signals (phase 0_gate signal to phase 19_gate signal) that become HI level for each partial phase. It is.

  The AND gate block 50 uses the edge signal and the gate signal to detect in which gate signal period the edge signal is generated, and counts up an edge count counter (phase 0_count) corresponding to each gate period. This is a circuit for supplying an up signal to a phase 19_count up signal. This circuit has a structure in which 20 AND gates with two inputs are combined. The edge signal from the edge detection circuit b49 is added to one input, and the gate signal from the phase gate signal generation circuit 53 is added to the other input. It has been. The output of each AND gate is supplied to the edge number counter 0 to the edge number counter 19 in the edge number counter block 51.

  The edge number counter block 51 is a circuit composed of 20 edge number counter 0 to edge number counter 19 corresponding to the number of the gate signal periods. By counting the number of edges for each gate period, data is counted. It is a circuit for creating a histogram of signal edge phases.

  The histogram calculation circuit 52 is a circuit that performs calculation processing based on the histogram and creates the phase detection signal b42 used for phase adjustment of the reproduction clock 8. Details of the histogram calculation circuit 52 will be described later.

  The timing control circuit 55 is a circuit that creates a control signal to be supplied to each circuit in the clock generation circuit b40 from the arithmetic clock 19 and the UW detection signal 20, and also creates the creation timing information b44 and the switching timing information 45 To do.

  The phase counter_b54 is a circuit equivalent to the phase counter a33 in the first embodiment, is reset by an instruction from the timing control circuit 55, and continuously performs a count-up operation from 0 to 19 by the operation clock 19 .

  Hereinafter, a method of creating a histogram in the phase information detection circuit_b40 will be described with reference to FIG.

  In the phase information detection circuit _b40, the histogram is created by dividing the 1-bit period into 20 phases, detecting which phase the edge of the received data 7 is located, and accumulating the detection results for each phase. .

  In the figure, one section indicated by the phase measurement unit is a 1-bit period, and is set by the timing control circuit 55.

  The range indicated by the expanded data signal is a 1-bit period, which corresponds to the 20 clock period of the operation clock 19.

  In the edge detection circuit b49, when the relationship between the rising edge of the reception data 7 and the operation clock 19 exists at the position shown in the figure, the rising edge of the operation clock 19 immediately after the reception data 7 changes to “HI” until the next rising edge “ HI ”level is output.

  Phase 0_gate signal to phase 19_gate signal are gate signals created by the phase gate signal generation circuit 53, and the HI period of each gate signal is generated in order from the phase 1_gate signal as shown in the figure. Yes.

  As described above, the edge signal and each phase gate signal are input to the AND gate block 50, and as illustrated, the edge signal and the phase 6_gate signal are input to the output of the AND gate (phase 9 count up signal). HI period occurs.

  The phase 9 count up signal is a count up signal to the edge number counter 9 in the edge number counter block 51. The edge number counters 0 to -19 count up at the rising edge of the count up signal.

  When the HI period occurs in the phase 9 count-up signal, the edge number counter 9 is counted up as shown in the figure, and the value of the edge number counter 9 is counted up from M to M + 1.

  By repeating the above operation during the transmitter information block or the image data block period, a histogram corresponding to the edge phase of the reception data 7 in each block period is generated.

  Each edge number counter of the edge number counter block 51 is reset by a counter reset signal from the timing control circuit 55 immediately before the start of the histogram generation period.

  The histogram calculation circuit 52 obtains the phase at the center of the obtained histogram distribution, and outputs a value obtained by adding a phase amount corresponding to 1/2 of the bit width to the value as the phase detection signal b42. For example, when the phase “0” is detected as the median value of the histogram, the phase “10” including the phase amount “10” is output. When phase “15” is detected, phase “5” (phase “20” = phase “0” is added since phase amount “10” is added, so phase “25” = phase “5”) is output. .

  Various methods for obtaining the center of the histogram have been devised. For example, the maximum value may be simply used as the center value, or a weighted average may be used, or a center value greater than or equal to a predetermined value may be used as the center value.

  When there is a frequency difference between the reference clock 18 and the data clock of the received data 7, the phase detection signal b42 obtained by the above method detects the phase of the edge at the center of each block period used for measurement. Become. Therefore, unlike the case of the first embodiment, the value of the elapsed time signal 25 is the elapsed time from the central time point of each block period.

  In the second embodiment, the timing for performing phase correction does not change depending on the value of the elapsed time signal 25 as in the first embodiment (see the description of FIG. 10). Regardless of the phase adjustment is performed at a predetermined timing.

  Hereinafter, a method of creating the elapsed time signal 25 will be described with reference to FIGS.

  FIG. 14 is an explanatory diagram for the case where the phase adjustment of the recovered clock 8 is performed only immediately after the synchronization pattern (UW2) of the next data block.

  In this case, the phase correction process described with reference to FIG. 10 in the first embodiment is not performed, and the phase adjustment including the phase correction is performed by the phase adjustment performed immediately after the synchronization pattern (UW) detection. .

  As described above, the phase indicated by the phase detection signal b42 is a phase suitable for the received data 7 at the central time point ((A)) of the transmitter information period ((17)-(18)).

  When the phase of the recovered clock 8 is adjusted just after the synchronization pattern (UW2), the recovered clock 8 whose phase is adjusted immediately after UW2 ((19)) is used without being readjusted during the next data block period. . Accordingly, the sampling period with the phase-adjusted reproduction clock is the entire image data period in the data block.

  In this case, the phase adjustment is performed so that the central point ((B)) in the data block period becomes an optimum phase. Therefore, in the phase adjustment performed at the time (19), it is necessary to correct the phase shift amount generated in the period (A)-(B) with respect to the phase indicated by the phase detection signal b42.

  Hereinafter, under the same conditions as the description of the data reproducing apparatus according to the first embodiment, when the frequency difference between the data clock of the received data 7 and the reference clock 18 is 40 ppm (data clock: 10 MHz, reference clock: 10.0004 MHz). An example will be described (refer to the description of the first embodiment for details of conditions). The clock generation circuit 17 is different from the first embodiment in the operation of the correction phase amount generation circuit 36.

  Here, since the period (A)-(B) is one data block period, 200000 corresponding to one data block is output as the value of the elapsed time signal 25. For this reason, the correction phase amount creation circuit 36 calculates (value of the frequency difference signal 21 * 200000/200000), and outputs the value of the frequency difference signal 21 as it is.

  For example, as in the first embodiment, when the frequency difference between the data clock of the reception data 7 and the reference clock 18 is 40 ppm, the value of the frequency difference signal 21 is “+8”. This is because, during the data block period, a phase shift of +8 clocks with the operation clock 19 (because the frequency of the recovered clock is higher, the count is faster in the same period, so the phase counter_b54 has a larger phase. If the phase is shifted, the phase will match).

  For example, when the output of the phase detection signal b42 is “10”, the value “+8” of the frequency difference signal 21 is added, and “18” becomes the adjustment value at time (19). Since the subsequent processing is the same as that of the data reproducing apparatus according to the first embodiment, description thereof is omitted.

  Using Fig. 15, we explain how to adjust the phase of the recovered clock at two points in time, immediately after the synchronization pattern (UW2) of the next data block ((19)) and at the center of the data block ((20)) To do.

  When the phase adjustment is performed in two places as described above, it is best to adjust the phase to a phase suitable for the central time point ((C), (D)) of the period in which the adjusted recovered clock is used. Become. Therefore, in the phase adjustment performed in (19), the phase generated in the period (A)-(C), which is the period up to (C), which is the phase adjustment target time, with respect to the phase indicated by the phase detection signal b42. It is necessary to correct the amount of deviation.

As described above, since the phase adjustment is performed at the time of (19), the period (A)-(C) is a period obtained by subtracting 1/4 of the image data period (9900 bits) from one data block period (10000 bits) (7425 bits Therefore, the creation timing information b45 is created so that 148500 corresponding to an output of the elapsed time signal 25 corresponding to 7425 bits is output at the time of calculation in the correction phase amount creation circuit 36.

  In this case, since the value of the frequency difference signal 21 is “+8”, the output of the correction phase amount generation circuit 36 is 6 (+ 8 * 148500/200000 = 5.94 rounded off = 6).

  In the phase adjustment performed in (20), as in the case of (19), the period from the phase indicated by the phase detection signal b42 to (D) which is the phase adjustment target time point (A)-(D) It is necessary to correct the amount of phase shift occurring in the period. The period (A)-(D) is a period (12475 bits) obtained by adding 1/4 of the image data period (9900 bits) to one data block period (10000 bits), so the creation timing information b44 is a correction phase amount creation circuit. At the time of calculation at 36, the output time signal 25 is generated so that a value of 249500 corresponding to 12475 bits is output.

  In this case, since the value of the frequency difference signal 21 is “+8”, the output of the correction phase amount creation circuit 36 is 10 (+ 8 * 249500/200000 = 9.98 rounded off = 10). With the above processing, when the output of the phase detection signal b42 is “10”, the phase of the recovered clock in (19) is “16”, and the phase in (20) is “20”. Subsequent processing is the same as that of the first embodiment, and thus description thereof is omitted.

  Finally, using FIG. 16, after adjusting the phase of the recovered clock immediately after the synchronization pattern (UW2) of the next data block ((19)), the frequency difference thereafter is the same as in the first embodiment. A method of performing phase adjustment at an adjustment interval according to the above will be described.

  Due to the above processing, in the phase adjustment performed in (19), the phase shift that occurs during the period (A)-(19) up to (19), which is the phase adjustment target time, with respect to the phase indicated by the phase detection signal b42. It is necessary to correct the amount.

  The period (A)-(19) is a period (5050 bits) obtained by adding 1/2 of the UW2 period (100 bits) to 1/2 period of 1 data block period (10000 bits). At the time of calculation in the correction phase amount generation circuit 36, the output time signal 25 is generated so that 101000 corresponding to 5050 bits is output.

  In this case, since the value of the frequency difference signal 21 is “+8”, the output of the correction phase amount generation circuit 36 is 4 (+ 8 * 101000/200000 = 4.04 rounded off = 4). After that, since the frequency difference signal 21 is set to “+8”, as shown in the first embodiment, the correction phase amount generation circuit 36 for the period from the time point (19) to 25000 counts (1250 bits) later is provided. Output remains “4”, and the output during the period from 25000 counts (1250 bits) to 50000 counts becomes “5”. At this time, the output of the phase correction circuit 37 becomes a value obtained by adding “+1” to the value of the phase detection signal b42, and accordingly, the phase of the recovered clock 8 is corrected and output.

  Since the subsequent processing is the same as that of the data reproducing apparatus according to the first embodiment, description thereof is omitted.

  As described above, according to the second embodiment, it is possible to provide a data reproduction device that has the same effects as the data reproduction device according to the first embodiment.

[Third embodiment]
The third embodiment will be described with reference to FIG. The third embodiment differs from the first embodiment in the frequency difference detection method. FIG. 17 is a configuration diagram of the receiver c56 in the data reproducing apparatus according to the third embodiment.

  In the third embodiment, the frequency difference detection method includes, as data, information related to the transmission clock frequency in the received data 7, specifies the transmission clock frequency from the received information related to the transmission clock frequency, and further receives the received data. This is a method of detecting a frequency difference using information relating to a reproduction clock frequency held in the apparatus.

  For example, when the transmitter information in the received data 7 includes ID information for each transmitter, the receiver c56 reads the transmission clock frequency information registered in advance from the ID information by the data processing circuit c58. Things will be possible.

  In FIG. 17, reference clock frequency information is stored in the data processing circuit c58, and frequency difference information c62 is created from the transmission clock frequency information and the reference clock frequency information and set in the frequency difference setting buffer 59.

  The frequency difference information c62 set in the frequency difference setting buffer 59 is output to the recovered clock generation circuit c57 as the frequency difference signal c63.

  The reproduction clock generation circuit c57 omits the frequency difference detection circuit 14 from the reproduction clock generation circuit 5 in the data reproduction apparatus according to the first embodiment, and receives the frequency difference signal c63 from the frequency difference setting buffer 59 of the frequency difference detection circuit 14. It is configured to be used in place of the output frequency difference signal 21.

  With the above configuration, the receiver c56 identifies the individual ID of the transmitter from the received data 7, and detects the transmission clock frequency for each transmitter stored for each ID. Further, the frequency difference is obtained by obtaining the difference between the two frequencies using the frequency information of the reference clock stored in the receiver c56.

  As another method for detecting the frequency difference, it is also possible to place the transmission clock frequency information directly on the reception data 7. In this case, the data processing circuit c58 obtains a frequency difference using the received transmission clock frequency information and the stored reference clock frequency information, and sets the frequency difference information in the frequency difference setting buffer 59.

  By these methods, it is possible to create frequency difference information without measuring the transmission clock frequency in the reception data 7 by the receiver c56. Since the created frequency difference information is after receiving the transmitter information, the frequency difference information is obtained at the time of receiving the transmitter information block (first data block) in the first frame immediately after the start of communication with the transmitter 1. However, it is possible to create frequency difference information after receiving information about the transmission clock frequency in the transmitter information block, so by placing information about the transmission clock frequency near the beginning of the transmitter information block The phase adjustment based on the frequency difference with respect to the reproduction clock 8 in the image data block can be made possible.

  Further, with respect to the next frame, by holding and using the frequency difference information obtained in the first frame, the phase adjustment based on the frequency difference with respect to the recovered clock 8 can be performed even in the transmitter information block. Since processing other than the above is the same as in the first embodiment, description thereof is omitted.

  As described above, according to the third embodiment, it is possible to provide a data reproduction device that has the same effects as the data reproduction device according to the first embodiment.

  As described above, the present invention has been described based on the first to third embodiments. However, the present invention is not limited to the above-described embodiments, and within the scope of the present invention, for example, the following Of course, modifications / applications are possible.

  Further, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

    DESCRIPTION OF SYMBOLS 1 ... Transmitter, 2 ... Data reproduction device, 4 ... Sampling circuit, 5 ... Reproduction clock generation circuit a, 6 ... Data processing circuit, 11 ... Oscillator, 12 ... Frequency multiplication circuit, 13 ... UW detection circuit, 14 ... Frequency difference Detection circuit, 15 ... Phase information detection circuit a, 16 ... Elapsed time signal generation circuit, 17 ... Clock generation circuit, 26 ... UW register, 27 ... Correlation detection circuit, 28 ... Counter control circuit, 29 ... Interval measurement counter, 30 ... Reference value buffer, 31 ... Difference detection circuit, 32 ... Edge detection circuit a, 33 ... Phase counter a, 34 ... UW period measurement circuit, 35 ... Phase setting circuit, 36 ... Correction phase amount creation circuit, 37 ... Phase correction circuit, 38 ... Comparison circuit, 39 ... Reproduction clock generation circuit b, 40 ... Phase information detection circuit b, 41 ... Switching circuit, 49 ... Edge detection circuit b, 50 ... Gate block, 51 ... Edge number counter block, 52 ... Histogram calculation times 53, phase gate signal generation circuit, 55 ... timing control circuit, 56 ... receiver c, 57 ... reproduction clock generation circuit c, 58 ... data processing circuit c, 59 ... frequency difference setting buffer.

Claims (6)

A data reproduction device that receives data transmitted from a transmitter and reproduces the received data according to a reproduction clock signal,
A frequency difference detection unit that detects a frequency difference between a frequency of a data clock signal in the data and a frequency of a reference clock signal that is a clock signal related to the data reproduction process, and creates frequency difference information;
A phase information detector that detects phase information of a data clock signal in the data and creates phase information;
An elapsed time information creation unit for creating elapsed time information indicating a time from a phase information detection time point by the phase information detection unit to a phase adjustment execution time point for performing phase adjustment of the recovered clock signal;
A reproduction clock signal for sampling the data is generated based on the reference clock signal, and the reproduction is performed based on the frequency difference information, the phase information, and the elapsed time information at the time of the phase adjustment. A regenerated clock generator for performing phase adjustment of the clock signal;
A data reproducing apparatus comprising: The reproduction clock generation unit
Set the phase adjustment execution time based on the frequency difference information,
Create phase correction information based on the elapsed time information and the frequency difference information at the time of phase adjustment,
The data reproducing apparatus according to claim 1, wherein an adjustment value in the phase adjustment is determined based on the phase correction information and the phase information. The reproduction clock generation unit
Set the phase adjustment execution time based on the frequency difference information,
Create phase correction information based on the elapsed time information and the frequency difference information at the time of phase adjustment,
Determine the adjustment value in the phase adjustment based on the phase correction information and the phase information,
The elapsed time information creation unit adds a value obtained by adding, for each phase adjustment execution time, a time corresponding to a half period of a sampling period that is an execution period of the sampling executed after the phase adjustment is executed. The data reproducing apparatus according to claim 1, wherein time is set. The data is composed of a plurality of data blocks, and each of the data blocks is composed of a synchronization pattern and image data,
The phase adjustment execution time is a time immediately before the reception time of the image data,
The data reproduction apparatus according to claim 3, wherein the sampling period is a reception period of the image data. A data reproduction device that receives data transmitted from a transmitter and reproduces the received data according to a reproduction clock signal,
A clock frequency information acquisition unit that acquires data clock frequency information indicating a frequency of a data clock signal included in the data;
A reference clock frequency information storage unit that stores reference clock frequency information indicating a frequency of a reference clock signal related to the data reproduction process;
A frequency difference information creating unit that creates frequency difference information indicating a frequency difference between the data clock signal and the reference clock signal based on the data clock frequency information and the reference clock frequency information;
A phase information detector for detecting phase information of a data clock signal in the data, and an elapsed time indicating a time from a phase information detection time by the phase information detector to a phase adjustment execution time for performing phase adjustment of the recovered clock signal An elapsed time information creation unit for creating information;
Based on the reference clock signal, a recovered clock signal for sampling the data is generated, and at the time of the phase adjustment, the recovered clock is based on the frequency difference information, the phase information, and the elapsed time information. A regenerated clock generator for performing phase adjustment of the signal;
A data reproducing apparatus comprising: A data reproduction device that receives data transmitted from a transmitter and reproduces the received data according to a reproduction clock signal,
Data clock frequency for storing transmitter ID information for identifying the transmitter included in the data and data clock frequency information indicating the frequency of the data clock signal of the data in association with each transmitter An information storage unit;
A reference clock frequency information storage unit that stores reference clock frequency information indicating a frequency of a reference clock signal related to the data reproduction process;
A frequency difference information creating unit that creates frequency difference information indicating a frequency difference between the data clock signal and the reference clock signal based on the data clock frequency information and the reference clock frequency information;
A phase information detector for detecting phase information of a data clock signal in the data;
An elapsed time information creation unit for creating elapsed time information indicating a time from a phase information detection time point by the phase information detection unit to a phase adjustment execution time point for performing phase adjustment of the recovered clock signal;
Based on the reference clock signal, a recovered clock signal for sampling the data is generated, and at the time of the phase adjustment, the recovered clock is based on the frequency difference information, the phase information, and the elapsed time information. A regenerated clock generator for performing phase adjustment of the signal;
A data reproducing apparatus comprising:

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