JP2010206779A - Switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switch circuit which prevents the malfunction of a peripheral circuit. <P>SOLUTION: When a negative input voltage is input to an internal circuit to a first terminal P1, an NMOS transistor 12 is controlled to be turned off but since the input voltage is negative, on the basis of an inter-gate-source voltages of the NMOS transistor 12 at that time, the NMOS transistor 12 is not completely turned off but operates in e.g., a weak inversion area. Then, a current flows from a ground terminal VSS to the first terminal P1 via NMOS transistors 12, 13. Therefore, since this current flows not from a power supply terminal VCC but from the ground terminal VSS, with the flow of this current, a power supply voltage is not reduced and no malfunction occurs in any peripheral circuit utilizing the power supply voltage. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a switch circuit provided at a first terminal to which a positive or negative input voltage is input.

  A conventional switch circuit will be described. FIG. 2 is a diagram illustrating a conventional switch circuit.

  When an input voltage to an internal circuit (not shown) is input to the terminal IO, the voltage of the terminal VG is controlled to be the ground voltage, and the voltage of the terminal VENB is controlled to be the power supply voltage of the power supply terminal VCC. Therefore, the NMOS transistors 61 and 62 are turned off, the high voltage at the terminal VPP is not output from the terminal IO, the NMOS transistor 63 is turned on, and the voltage at the connection point between the source of the NMOS transistor 61 and the drain of the NMOS transistor 62 is the power supply. Become a voltage.

  When a high voltage is output from the terminal IO, the voltage at the terminal VG is controlled to be the power supply voltage, and the voltage at the terminal VENB is controlled to be the ground voltage. Therefore, the NMOS transistors 61 to 62 are turned on, a high voltage is output from the terminal IO, and the NMOS transistor 63 is turned off (see, for example, Patent Document 1).

Japanese Patent No. 3197161

  However, in the conventional technique, when the input voltage to the internal circuit is input to the terminal IO, the NMOS transistors 61 to 62 are controlled to be turned off. If the input voltage is negative, the NMOS transistor at this time is controlled. Based on the gate-source voltage of the transistor 62, the NMOS transistor 62 does not completely turn off and operates, for example, in the weak inversion region. Then, since a current flows from the power supply terminal VCC to the terminal IO via the NMOS transistors 62 and 63, there is a risk that the power supply voltage is lowered based on the current, and a peripheral circuit using the power supply voltage malfunctions. There is a risk.

  The present invention has been made in view of the above problems, and provides a switch circuit that does not cause a peripheral circuit to malfunction.

  In order to solve the above-mentioned problems, the present invention has first and second terminals, and a positive or negative input voltage to the internal circuit is input at the first input, or the second terminal at the second input In the switch circuit provided at the first terminal from which the input voltage is output, the gate voltage is controlled to be turned off at the time of the first input and turned on at the time of the second input, and the drain is connected to the second terminal. A first transistor, a second transistor whose gate voltage is controlled to be turned off at the time of the first input and turned on at the time of the second input, and whose source is connected to the first terminal; The gate voltage is controlled to be turned off at the time of the second input, the source is connected to the ground terminal, and the drain is connected to the connection point between the source of the first transistor and the drain of the second transistor. Providing a switching circuit, characterized in that it comprises a transistor, a.

  In the present invention, when the first terminal receives a negative input voltage to the internal circuit, the second transistor is controlled to be turned off. However, since the input voltage is negative, the second transistor at this time The second transistor is not completely turned off based on the gate-source voltage. Then, a current flows from the ground terminal to the first terminal via the second and third transistors. Therefore, since this current flows from the ground terminal instead of the power supply terminal, this current flows, so that the power supply voltage is not lowered and the peripheral circuit using the power supply voltage does not malfunction.

It is a circuit diagram which shows the switch circuit of a 1st Example form. It is a figure which shows the conventional switch circuit. It is a circuit diagram which shows the switch circuit of the 2nd Example form.

  Embodiments of the present invention will be described below with reference to the drawings.

<First embodiment>
First, the configuration of a switch circuit provided at a first terminal to which a positive or negative input voltage is input will be described. FIG. 1 is a diagram illustrating a switch circuit.

  The switch circuit includes NMOS transistors 11, 12, 13, an inverter 21, and an internal circuit 31. The switch circuit includes an enable terminal EN, a first terminal P1, a second terminal P2, a power supply terminal VCC, and a ground terminal VSS.

  The gate of the NMOS transistor 11 is connected to the enable terminal EN, and the drain is connected to the second terminal P2. The gate of the NMOS transistor 12 is connected to the enable terminal EN, and the source is connected to the first terminal P1. The inverter 21 is provided between the power supply terminal VCC and the ground terminal VSS. The input terminal of the inverter 21 is connected to the enable terminal EN, and the output terminal is connected to the gate of the NMOS transistor 13. The source of the NMOS transistor 13 is connected to the ground terminal VSS, and the drain is connected to a connection point between the source of the NMOS transistor 11 and the drain of the NMOS transistor 12. Although not shown, the substrates of the NMOS transistors 11, 12, and 13 are connected to the ground terminal VSS.

  The internal circuit 31 is connected to the first terminal P1 via the switch 32.

  The first terminal P1 receives a positive or negative input voltage to the internal circuit 31 at the time of the first input. Alternatively, the first terminal P1 outputs the input voltage of the second terminal P2 during the second input.

  The gate voltage of the NMOS transistor 11 is controlled so as to be turned off at the time of the first input and turned on at the time of the second input and the output. The gate voltage of the NMOS transistor 12 is controlled so as to be turned off at the time of the first input and turned on at the time of the second input and the output. The gate voltage of the NMOS transistor 13 is controlled so that it is turned on at the first input and turned off at the second input and output.

Next, the operation of the switch circuit will be described.
When the first terminal P1 receives a negative input voltage to the internal circuit 31 (first input), the voltage of the enable terminal EN is controlled to be the ground voltage of the ground terminal VSS. Then, the output voltage of the inverter 21 becomes the power supply voltage of the power supply terminal VCC. Therefore, the NMOS transistors 11 and 12 are turned off, the voltage of the second terminal P2 is not output from the first terminal P1, the NMOS transistor 13 is turned on, and the connection point between the source of the NMOS transistor 11 and the drain of the NMOS transistor 12 is reached. The voltage becomes the ground voltage. Further, the switch 32 is turned on, and a negative input voltage is applied to the internal circuit 31.

  At this time, since the gate voltage and the source voltage of the NMOS transistor 11 are the ground voltage, the gate-source voltage of the NMOS transistor 11 is 0 V, and the leakage current of the NMOS transistor 11 is reduced. Therefore, the voltage at the second terminal P2 is difficult to decrease.

  Further, since the input voltage of the first terminal P1 is negative, the NMOS transistor 12 operates in, for example, a weak inversion region without being completely turned off based on the gate-source voltage of the NMOS transistor 12 at this time. Then, a current flows from the ground terminal VSS to the first terminal P1 via the NMOS transistors 12 and 13. Therefore, since this current flows not from the power supply terminal VCC but from the ground terminal VSS, the power supply voltage does not decrease due to this current flowing.

  When a positive input voltage to the internal circuit 31 is input to the first terminal P1 (at the time of the first input), the NMOS transistors 11 and 12 are turned off, and the voltage at the second terminal P2 is the first terminal, as described above. Without outputting from P1, the NMOS transistor 13 is turned on, and the voltage at the connection point between the source of the NMOS transistor 11 and the drain of the NMOS transistor 12 becomes the ground voltage. Further, the switch 32 is turned on, and a positive input voltage is applied to the internal circuit 31.

  At this time, since the gate voltage and the source voltage of the NMOS transistor 11 are the ground voltage, the gate-source voltage of the NMOS transistor 11 is 0 V, and the leakage current of the NMOS transistor 11 is reduced. Therefore, the voltage at the second terminal P2 is difficult to decrease.

  Since the input voltage is positive, the NMOS transistor 12 is completely turned off based on the gate-source voltage of the NMOS transistor 12 at this time, and the leakage current of the NMOS transistor 12 is reduced.

  When the input voltage of the second terminal P2 is input to the first terminal P1 (during the second input), the voltage of the enable terminal EN is controlled to be the power supply voltage. Then, the output voltage of the inverter 21 becomes the ground voltage. Therefore, the NMOS transistors 11 and 12 are turned on, the voltage of the second terminal P2 is output from the first terminal P1, and the NMOS transistor 13 is turned off. Further, the switch 32 is turned off, and the voltage of the second terminal P2 is not applied to the input terminal of the internal circuit 31.

  In this way, the NMOS transistor 12 is controlled to be turned off when a negative input voltage to the internal circuit is input to the first terminal P1, but the NMOS transistor at this time is controlled because the input voltage is negative. Based on the 12 gate-source voltages, the NMOS transistor 12 does not completely turn off, for example, operates in the weak inversion region. Then, a current flows from the ground terminal VSS to the first terminal P1 via the NMOS transistors 12 and 13. Therefore, since this current flows from the ground terminal VSS instead of the power supply terminal VCC, this current flows, so that the power supply voltage is not lowered and the peripheral circuit using the power supply voltage does not malfunction.

  Further, since the gates of the NMOS transistors 11 and 12 and the gate of the NMOS transistor 13 are controlled by one signal (the voltage of the enable terminal EN), the operation control becomes easy.

<Second Embodiment>
FIG. 3 shows a circuit diagram of the switch circuit of the second embodiment. The difference from FIG. 1 is that it is used as a test circuit for nonvolatile memory. As a configuration, an NMOS transistor 301, an NMOS transistor 303, a memory cell transistor 302, a sense amplifier 304, an output driver 306, and a pull-up element 307 are added. Further, the name is changed with the second terminal P2 as the output terminal 313.

  As for connection, the memory cell transistor 302 has a gate connected to the node 312, a drain connected to the source of the NMOS transistor 301, and a source connected to the ground terminal VSS. The NMOS transistor 301 has a gate connected to the node 311 and a drain connected to the source of the NMOS transistor 303 and the source of the NMOS transistor 12. The NMOS transistor 303 has a gate connected to the node 314 and a drain connected to the pull-up element 307 and the non-inverting input terminal of the sense amplifier 304. One of the pull-up elements 307 is connected to the drain of the NMOS transistor 303 and the other is connected to the power supply terminal VCC. The sense amplifier 304 has an inverting input terminal connected to the reference voltage circuit 305 and an output connected to the output buffer circuit 306. One of the reference voltage circuits 305 is connected to the ground terminal VSS, and the other is connected to the inverting input terminal of the sense amplifier 304. The output buffer circuit 306 has an output connected to the output terminal 313.

  Next, the operation of the switch circuit of the second embodiment will be described.

  The NMOS transistor 301 operates as an enable transistor. The memory cell transistor 302 is composed of a nonvolatile element such as EEPROM or OTP. The switch circuit of the second embodiment is used when testing a nonvolatile memory, and can be put into a test state by inputting an “L” signal to the node 314.

  During the test, the enable terminal EN is controlled so that “H” is input. In addition, control is performed so that “H” is input to the nodes 311 and 312. In this state, since the NMOS transistors 11, 12, and 301 are on, the current flowing through the memory cell transistor 302 can be measured by applying a voltage to the output terminal 313.

  During normal operation, an “H” signal is input to the node 314 to turn on the NMOS transistor 306. The enable terminal EN inputs an “L” signal to turn off the NMOSs 11 and 12. In this state, an output signal is output from the output terminal 313. Here, when a negative voltage signal is output from the output terminal 313, the NMOS transistor 11 is weakly turned on and noise is generated at the node 316. However, since the NMOS transistor 12 is off, this noise can be blocked without being transmitted to the node 315. In this way, during normal operation, even if the voltage at the output terminal 313 becomes negative, noise is cut off to prevent malfunction.

  Although not shown, the source of the NMOS transistor 12 may be directly connected to the memory cell transistor 302.

  As described above, the switch circuit according to the second embodiment can normally measure the current of the memory cell transistor during the test by using the switch circuit for the test circuit of the memory cell transistor 302. . Further, even if the voltage at the output terminal 313 becomes negative during normal operation, normal operation can be performed without transmitting noise to the node 315.

EN enable terminal P1 first terminal P2 second terminal VCC power supply terminal VSS ground terminal 11 to 13 NMOS transistor 21 inverter 31 internal circuit 32 switch 304 sense amplifier circuit 305 reference voltage circuit 306 output buffer circuit 307 pull-up element 311 node 311
312 Node 312
313 Output terminal 314 Node 314

Claims (4)

It has first and second terminals, and a positive or negative input voltage from the internal circuit is input at the first input, or a positive or negative input voltage to the second terminal is input at the second input. In the switch circuit provided in the first terminal,
A first transistor whose gate voltage is controlled to be turned off at the time of the first input and turned on at the time of the second input, and whose drain is connected to the second terminal;
A second transistor whose gate voltage is controlled to be turned off at the time of the first input and turned on at the time of the second input, and whose source is connected to the first terminal;
The gate voltage is controlled to turn on at the first input and off at the second input, the source is connected to the ground terminal, and the drain is a connection point between the source of the first transistor and the drain of the second transistor. A third transistor connected;
A switch circuit comprising: An inverter having an input terminal connected to the gates of the first and second transistors and an output terminal connected to the gate of the third transistor;
The switch circuit according to claim 1, further comprising:   2. The switch circuit according to claim 1, wherein the first to third transistors are NMOS transistors.   The switch circuit according to claim 1, wherein the switch circuit connects the first terminal to a nonvolatile element.

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