JP2010199811A - Memory system of controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable memory system of a controller, with an error correcting function, for changing to the parity check matrix of different encoding efficiency in a circuit as it is. <P>SOLUTION: The memory system of the controller includes: a rewritable check matrix memory 2 for storing the matrix data of the parity check matrix; a main memory for storing input data; an encoding circuit for performing a matrix operation in a matrix operation circuit 4 using the parity check matrix to the input data and generating a check code; a check code memory for storing the check code; and a decoding circuit for performing the matrix operation by the matrix operation circuit by using the result of performing the operation using the parity check matrix to the output data from the main memory and the check code, checking the error of the output data and outputting correction information. In this case, the matrix data of the parity check matrix stored in the check matrix memory 2 are rewritten by a rewrite means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an error correction method for automatically correcting an error used in a memory system and improving the reliability of the apparatus / system, and in particular, operates normally in a poor working environment due to temperature, vibration, noise, etc. A system having an error correction code of a parity check matrix that is one of error correction methods used in industrial devices / systems or medical / aerospace / public systems that require reliability such as medical / aerospace / public systems In particular, the present invention relates to a memory system for storing programs and data of industrial devices that are repeatedly referred to at a constant cycle.

There is an error correction code as a method for correcting an error in data. Error correction codes are used in industrial devices, industrial systems, or devices and systems that require reliability, such as medical, aerospace, and public systems. In a semiconductor memory, it is used as a countermeasure against destruction of memory data by α rays or cosmic rays.
Error correction codes have been studied as a code theory, and parity check matrices with various functions such as a parity check matrix specialized for burst errors and a parity check matrix with locally enhanced error correction capabilities are proposed. In order to improve reliability, it is important to use a parity check matrix that matches the installation environment of an industrial device or an industrial system.

  Here, a basic technique of the error correction code of the parity check matrix will be described with reference to FIG. The p-bit input data (see Equation 1) is stored in the memory. “Τ” is a symbol that means transposition.

  At the same time that the p-bit input data I is stored in the memory, the encoding circuit performs a matrix operation on the input data I by a parity check matrix H (see Equation 2) having the number of rows and the number of columns p (see Equation 2) The syndrome S (see Equation 4), which is the calculation result, is stored in the designated area of the memory as a check code C (see Equation 5) having a data width of q bits.

  The decoding circuit detects an error depending on whether or not the check result W that is a comparison result between S ′ and the check code C, which is an operation result of the parity matrix H of the stored data (see Equation 6), is a zero vector (number (See equation 7). However, the addition symbol related to the matrix operation of the parity check matrix means exclusive OR.

Then, in the case of error detection as shown in Equation 8, error correction that column data h _k of the corresponding parity check matrix matches the check result W if only the k-th 1 bit of stored data O is in error Based on the principle of the code, a column matching the comparison result W is searched from the parity check matrix to identify and correct the error location.

  The data in the memory is erroneous due to various physical factors, and the value appearing in the output channel of the memory is not necessarily incorrect with the input data I and may contain an error. It is the role of the decoding circuit to detect and correct this error. In general, the higher the error correction capability, the lower the coding rate (= data length / check code length).

  In a memory system using a conventional general error correction code, output data is checked and corrected in units of words, and stored data and check codes are read from and written to the memory almost simultaneously. In this way, the read / written data can be used immediately, and high-speed processing is possible.

  However, in this method, since the data length of the check data is as short as 32 bits or 64 bits, a high error correction capability is required, and a parity check matrix with low coding efficiency is used. Therefore, a check code memory area larger than the check data is required like the check code data of 16 bits for the check data of 32 bits. In addition, the coding / decoding circuit uses hardware specialized for the parity check matrix adopted for speeding up using a logic circuit such as an AND / OR circuit or an XOR (exclusive OR) circuit. Generally, it is realized and speeded up (see Patent Document 1). Patent Document 2 discloses a technique for reading a parity check matrix stored in a ROM and performing a matrix operation.

JP-A-9-16422 JP-A-7-226687

  Assuming an environment such as a noise level where an industrial device or industrial system controller is installed, design a memory system with error correction function specifications based on a parity check matrix of a level corresponding to the assumed environment. A controller is supplied.

  In the technique described in the background art, the parity check matrix is not rewritable and does not have a function of changing the parity check matrix according to the installation environment of the control device and selecting an optimal parity check matrix depending on the installation environment.

  It is burdensome for companies to design and develop variations of memory systems with specifications corresponding to environmental levels such as noise levels, and to commercialize them as a lineup. In addition, after delivery of the control device to the customer, if it differs from the assumed environmental level (for example, when the assumed noise level is high), change to a specification with a more reliable error correction function using a parity check matrix Therefore, it was necessary to replace the control device.

  By the way, in memory systems that store programs and data of industrial equipment that are repeatedly referenced at a fixed period, it is possible to cope with errors by checking whether there are any errors in the ladder program or data at a fixed period. , It may not require a very high speed process.

  Although the error correction capability applicable in such a case is not so high, a parity check matrix having a high coding efficiency, for example, per 100 bytes of check data, error correction of 1 bit is possible even with a check code length of 16 bits. There is a possible parity check matrix. This can sufficiently cope with a one-bit failure caused by α-rays or cosmic rays generated in a limited memory area. However, such a parity check matrix is a huge matrix such as 16 × 1024, and it is not realistic to realize an encoding / decoding circuit with the above-described logic circuit.

  Even if such an encoding / decoding circuit using a logic circuit can be realized, the actual system is not limited to the case of a one-bit failure that occurs rarely as described above. There are very rare cases where the level of the electrical noise level that enters from the memory is high, and data of a plurality of bits in the memory is inverted due to noise, resulting in an error.

  Such a situation is caused by an environment in which a control device such as an industrial device is installed, and is often difficult to predict in advance. However, selecting a parity check matrix having a high error correction capability that can correct errors of a plurality of bits with a large number of check code bits in advance may cause an extra check code even in other devices that do not have any problem with 1-bit correction capability. Is necessary and wasted. In addition, it is impossible to predict in advance an error occurrence pattern such as a burst error in which an error occurs in consecutive bits, and it is difficult to select an optimal parity check matrix.

  Therefore, in view of the above circumstances, an object of the present invention is to provide a highly reliable control device memory system having an error correction function that can be changed to a parity check matrix having different coding efficiency by a circuit as it is. .

  The invention according to claim 1 of the present application includes a main memory that stores input data, an encoding circuit that performs an operation on the input data using a parity check matrix to generate a check code, and a check that stores the check code The output data based on the result of operation using the parity check matrix on the output data from the main memory storing the input data and the check data stored in the check code memory In the memory system of the control device having a decoding circuit that performs error check and output of correction information, the memory system includes a rewritable check matrix memory that stores matrix data of the parity check matrix, and the check matrix Rewriting means for rewriting the matrix data stored in the memory for use, and the encoding circuit from the check matrix memory A matrix operation circuit that reads out matrix data of a parity check matrix and performs an operation on the input data, and the decoding circuit reads out the matrix data of the parity check matrix from the check matrix memory and outputs the matrix to the output data It is a memory system of a control device characterized by having a matrix operation circuit for performing an operation.

According to a second aspect of the present invention, the matrix operation circuit sequentially reads out the partial matrix data from the parity check matrix memory in which the matrix data of the parity check matrix is divided into partial matrices and stored as partial matrix data Matrix operation between a matrix DMAC (direct memory access controller) and partial matrix data read by the check matrix DMAC using input data to the main memory or output data from the main memory as an input vector A submatrix circuit to perform, a syndrome calculation circuit for sequentially adding outputs of the submatrix circuit, and a sequential execution number specifying means for specifying the number of sequential reads by the check matrix DMAC and the number of sequential additions by the syndrome calculation circuit And change the number of executions commanded to the sequential execution number designation means. And sequential execution frequency changing means is a memory system control apparatus according to claim 1, characterized in that it comprises a.
The invention according to claim 3 is provided with one matrix operation circuit instead of including the matrix operation circuit in each of the encoding circuit and the decoding circuit, and operates one matrix operation circuit in a time division manner. The memory system of the control device according to claim 1, wherein the memory system is configured as described above.

  According to the present invention, it is possible to provide a highly reliable memory system of a control device having an error correction function that can be changed to a parity check matrix having different coding efficiency by a circuit as it is.

  According to the present invention, a large parity check matrix can be applied to a memory system that stores programs and data provided in a control device such as an industrial device, and an error check code having a high code efficiency is used in the memory system with a small circuit. Therefore, it is possible to provide a reliable and high-speed memory system for a control device.

1 is a schematic configuration diagram of a memory system according to the present invention. It is a schematic block diagram of the matrix arithmetic circuit with which the encoding circuit of the memory system based on this invention was equipped. It is a schematic block diagram of the matrix arithmetic circuit with which the decoding circuit of the memory system based on this invention was equipped. It is the schematic of the structural example of the matrix calculating circuit of the memory system which concerns on this invention. It is a schematic block diagram of the encoding circuit of the memory system which concerns on this invention. It is a schematic block diagram of the decoding color of the memory system which concerns on this invention. It is a schematic block diagram of the system using the general error correction code which is a prior art.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a memory system 1 according to the present invention.
Input data is input to the main memory 5 and stored as stored data. The stored data is output from the main memory 5 as output data. The check matrix memory 2 stores matrix data of a parity check matrix. Matrix data of the parity check matrix stored in the check matrix memory 2 can be rewritten by rewrite means (not shown).

  The encoding circuit 3 includes a matrix operation circuit 4. The encoding circuit 3 receives the input data and the parity check matrix output from the check matrix memory 2, performs matrix calculation of both in the matrix calculation circuit 4, and outputs the calculation result to the check code memory 6.

  The check code memory 6 stores the calculation result output from the encoding circuit 3 as a check code. The stored check code is output to the decoding circuit 7. The decoding circuit 7 receives the output data output from the main memory 5, the parity check matrix output from the check matrix memory 2, and the check code output from the check code memory 6. A matrix operation is executed, and the result and the correction information are output based on the operation result and the check code.

FIG. 2 is a schematic configuration diagram of the matrix operation circuit 4 provided in the encoding circuit 3 of the memory system according to the present invention shown in FIG.
The matrix operation circuit 4 includes a submatrix operation circuit 40, a syndrome calculation circuit 41, a sequential execution number designation means 42, and a check matrix DMAC 43. The check matrix DMAC 43 is a controller that performs data transfer at high speed instead of a processor (CPU). As described with reference to FIG. 1, the matrix calculation circuit 4 receives the input data input to the main memory 5 and the partial matrix data of the parity check matrix from the check matrix memory. The input data is subjected to a partial matrix data of a parity check matrix as an input vector and a matrix calculation of the partial matrix of the parity check matrix in the partial matrix operation circuit 40.

  The check matrix DMAC 43 is a controller that instructs to read the check matrix data stored in the check matrix memory 2 into sub-matrix data of a size that can be input to the sub-matrix operation circuit 40. The check matrix DMAC 43 (DMA controller) is a controller that commands data transfer without using a processor and can transfer data at high speed.

  The sequential execution number specifying means 42 is a means for instructing the parity check matrix data to be subdivided into the parity check matrix DMAC 43 and the syndrome calculation circuit 41. The parity check matrix DMAC 43 controls the parity check matrix memory 2 so that the partial matrix data is output to the partial matrix arithmetic circuit 40 by the number of times designated by the sequential execution number designation means 42.

  The syndrome calculation circuit 41 outputs the output of the submatrix operation circuit 40 in the exclusive OR operation circuit 41a by the number of times obtained by subdividing the output data from the submatrix operation circuit 40 into the submatrix specified by the sequential execution number specifying means 42. This is a circuit that executes sequential calculation, stores the calculation result in the sequential addition result storage means 41b, and outputs a syndrome.

  The matrix operation circuit 4 can specify the number of sequential executions, which is the number of times of subdivision in the submatrix, by instructing the sequential execution number specifying unit 42 to any number by the sequential execution number changing unit 9. Thereby, the matrix operation circuit 4 can process the parity check matrix having different numbers of rows and columns.

  Similarly to the matrix operation circuit 4, the matrix operation circuit 8 included in the decoding circuit 7 also includes a submatrix operation circuit 80, a syndrome calculation circuit 81, a sequential execution number specifying means 82, and a check matrix DMAC 83. The matrix operation circuit 80 receives output data output from the main memory 5 and partial matrix data from the check matrix memory. The output data is subjected to partial matrix data as an input vector and a parity check matrix matrix operation in the partial matrix operation circuit 80.

  The check matrix DMAC 83 is a controller that instructs to read the check matrix data stored in the check matrix memory 2 into sub-matrix data of a size that can be input to the sub-matrix operation circuit 80 and to read it. The check matrix DMAC 83 (DMA controller) is a controller that commands data transfer without using a processor and can transfer data at high speed.

  The sequential execution number designation means 82 is a means for instructing the parity check matrix data to be divided into parity check matrix data 83 and the syndrome calculation circuit 81. The parity check matrix DMAC 83 controls the parity check matrix memory 2 so as to output the partial matrix data of the parity check matrix to the partial matrix operation circuit 80 by the number of times specified by the sequential execution count specifying means 82.

  The syndrome calculation circuit 81 sequentially performs an exclusive OR operation on the output of the submatrix operation circuit 80 as many times as the number of times the output data from the submatrix operation circuit 80 is subdivided into submatrices designated by the sequential execution number designating means 82. , A circuit for outputting a syndrome.

  The matrix operation circuit 8 can specify the number of sequential executions, which is the number of times of subdivision in the submatrix, by instructing the sequential execution number designating unit 82 any number of times by the sequential execution number changing unit 9. Thereby, the matrix operation circuit 8 can process the parity check matrix having different numbers of rows and columns.

  As shown in FIG. 3, since the matrix operation circuit 8 provided in the decoding circuit 7 has the same configuration as the matrix operation circuit 4 provided in the encoding circuit 3, the matrix operation is performed in each of the encoding circuit 3 and the decoding circuit 7. Instead of arranging the circuits 4 and 8, the encoding circuit 3 and the decoding circuit 7 may share one matrix operation circuit. When a single matrix operation circuit is shared by the encoding circuit 3 and the decoding circuit 7, the matrix operation circuit may be used in a time division manner.

FIG. 4 is a schematic diagram of a configuration example of the submatrix operation circuit 40 shown in FIG. The submatrix operation circuit 80 has the same configuration as that of the submatrix operation circuit 40, and thus the description thereof is omitted.
The memory system 1 has a circuit configuration in which one word of the main memory 5 is 32 bits and the submatrix operation circuit 40 has 8 rows and 32 columns. The parity check matrix H matrix data having 16 rows and 1024 columns is stored in the parity check matrix memory 2. The number of sequential executions of the submatrix operation circuit 40 is set by software as 2 vertical times × 32 horizontal times = total 64 times. That is, the large parity check matrix H is treated as a partial matrix H _{j, x} matrix (see Equation 9).

The submatrix operation circuit 40 of the matrix operation circuit 4 is a circuit that performs an operation on a parity check matrix having 8 rows and 32 columns. Arbitrary parity check matrix H _{j, x} can be calculated by inputting input data in units of one word input to main memory 5 and partial matrix data from check matrix memory 2.

  Next, matrix operation using the submatrix operation circuit 40 in the present invention will be described using the configuration of FIG. The input data D (see Equation 10) to the submatrix operation circuit 40 is a continuous 32-word (1024 bits) block, and is time-divided into the submatrix operation circuit 40 and input every word.

The check matrix DMAC 43 controls the check matrix memory 2 to sequentially pass the data of the partial matrices H _{0, x} H _{1, x} of the parity check matrix H to the partial matrix calculation circuit 40 according to the number of sequential executions. Partial matrix operation circuit 40 performs the calculation of the parity check matrix H of the partial matrix to the input of the input data D _x one word of which is divided input. As shown in FIG. 4, FF0 of the input vector data is multiplied (ANDed) with the data of each bit of column data No. 0 of the partial matrix. Further, the FF1 of the input vector data is multiplied (AND) with the data of each bit of the column data No. 1 of the submatrix. Then, an exclusive OR (EXOR) of the multiplication results of the two is performed. Other input vector data and other column data of the submatrix are similarly processed as shown in FIG. Thus, ends 16-bit result Sx calculation for divided the input data D _x (see equation (11)).

  Then, the syndrome calculation circuit 41 generates the syndrome S of the parity check matrix for the 32-word input data D by sequentially performing an exclusive OR operation on the calculation result Sx according to the number of executions (see Equation 12).

  By changing the matrix data of the parity check matrix stored in the check matrix memory 2 and the number of sequential executions of the matrix operation circuits 4 and 8, syndromes generated by different parity check matrices having a configuration obtained by multiplying the configuration of the submatrix by a constant number Generation is possible.

The number of sequential executions of the syndrome calculation circuits 41 and 81 and the number of sequential executions of the check matrix DMACs 43 and 43 are designated by the sequential execution number designation means 42 and 82, and the designated number of times is designated by the sequential execution number change means 9. Be changed. There are various changing methods. For example, the sequential execution number is arranged in a part of the parameters input from the data input device 90 such as a keyboard or a USB memory included in the sequential execution number changing unit 9, and the sequential execution number is changed. It is stored in the memory 92 of the execution number changing means 9 and is set in the sequential execution number specifying means 42 and 82 under the control of the CPU 91 of the sequential execution number changing means 9 when the system 1 is started up.
Alternatively, when the parity check matrix is input to the check matrix memory 2, it is loaded from the data input device 90 such as a USB memory together with the parity check matrix matrix data, and the CPU 91 stores the parity check matrix matrix data in the check matrix memory. 2 and the sequential execution count can be set in the sequential execution count designation means 42 and 82. Thus, the matrix data of the parity check matrix stored in the check matrix memory 2 can be rewritten using the rewrite means of the sequential execution number changing means 9.

  FIG. 5 shows an example of the encoding circuit 3 constituting the present invention. A matrix operation circuit 4 for outputting a syndrome which is a result of operation of a parity check matrix by a check matrix stored in the check matrix memory 2 with respect to continuous input data of 32 words to the main memory 5, and a check code for the syndrome And a check code DMAC 43 that performs control to be stored in the check code memory 6, and stores the check code in the check code memory 6 when the input data is written to the main memory 5.

  FIG. 6 shows an example of the decoding circuit 7 constituting the present invention. A matrix calculation circuit 8 that outputs a syndrome that is a calculation result of a parity check matrix stored in the check matrix memory 2 with respect to 32 words of output data from the main memory 5, and the matrix calculation circuit 8 that outputs the syndrome A check code DMAC 87 that performs control to read a check code corresponding to the syndrome from the check code memory 6 and a comparison (EXOR: exclusive OR operation) between the syndrome and the check code are performed by an exclusive logic circuit 84a. A check circuit 84 that performs correction and outputs the result as a check result, and an error search circuit 85 that calculates the check result output from the check circuit 84 and the parity check matrix by an exclusive OR operation circuit 85a and generates correction information. Have The check circuit 84 and the error search circuit 85 are conventionally known, and will be described in brief. The comparison result W by the exclusive OR operation circuit 84a based on the syndrome from the output data and the check code is output as the check result. The exclusive OR operation circuit 85a performs an operation on the result and the column data of the parity check matrix H read by the error search DMAC, the error location is specified by the error search DMAC, and correction information is output.

DESCRIPTION OF SYMBOLS 1 Memory system 2 Memory for check matrix 3 Encoding circuit 4 Matrix operation circuit 40 Submatrix operation circuit 41 Syndrome calculation circuit 41a Exclusive OR operation circuit 41b Sequential addition result storage means 42 Sequential execution count designation means 43 DMAC for check matrix
5 Main memory 6 Check code memory 7 Decoding circuit 8 Matrix operation circuit 80 Submatrix operation circuit 81 Syndrome calculation circuit 81a Exclusive OR operation circuit 81b Sequential addition result storage means 82 Sequential execution count designation means 83 DMAC for check matrix
84 Inspection Circuit 85 Error Search Circuit 86 Error Search DMAC
87 DMAC for check code
9 Sequential execution frequency changing means 90 Data input device 91 Processor 92 Memory

Claims (3)

Main memory for storing input data;
An encoding circuit that performs an operation on the input data using a parity check matrix to generate a check code, a check code memory that stores the check code, and an output from the main memory that stores the input data A control apparatus comprising: a result of performing an operation on data using the parity check matrix; and a decoding circuit that performs error check of the output data and output of correction information by the check code stored in the check code memory In the memory system,
The memory system includes:
A rewritable check matrix memory for storing matrix data of the parity check matrix;
Rewriting means for rewriting the matrix data stored in the check matrix memory;
The encoding circuit has a matrix operation circuit that reads matrix data of the parity check matrix from the check matrix memory and performs an operation on the input data,
The decoding circuit includes a matrix operation circuit that reads matrix data of the parity check matrix from the check matrix memory and performs an operation on the output data.
A memory system for a control device. The matrix operation circuit includes:
A parity check matrix DMAC (direct memory access controller) that sequentially reads out the partial matrix data from the parity check matrix memory that is configured to store the matrix data of the parity check matrix into partial matrices.
A submatrix circuit that performs a matrix operation on the submatrix data read by the check matrix DMAC using the input data to the main memory or the output data from the main memory as an input vector;
A syndrome calculation circuit for sequentially adding the outputs of the submatrix circuit;
Sequential execution number designating means for designating the number of sequential reads by the check matrix DMAC and the number of sequential additions by the syndrome calculation circuit;
Sequential execution number changing means for changing the number of executions commanded to the sequential execution number specifying means;
The memory system of the control device according to claim 1, comprising:   The encoding circuit and the decoding circuit are each provided with one matrix operation circuit instead of including the matrix operation circuit, and one matrix operation circuit is operated in a time division manner. The memory system of the control apparatus as described in any one of Claim 1 or 2.

Images