JP2010192989A - Solid-state imaging device and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of reading a signal at a high speed from a pixel without increasing power consumption. <P>SOLUTION: The solid state imaging device includes a pixel 201 which comprises a PD 202 for generating signal charge corresponding to incident light quantity and a FD 204 for accumulating the signal charge generated from the PD 202. In the pixel 201, the charge accumulated in the FD 204 is removed, the potential of the FD 204 is reset to reset potential VDD2, and the reset potential of the FD 204 is read out to a vertical signal line 208. Then, the potential of the vertical signal line 208 is changed to the potential of power supply VDD3, and then potential corresponding to the signal charge transferred from the PD 202 to the FD 204 and accumulated in the FD 204 is read out to the vertical signal line 208. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus.

  Conventionally, as an imaging apparatus such as a digital camera or a digital video camera, there is an apparatus using a solid-state imaging device composed of a CMOS APS (CMOS Activity Pixel Sensor) (see, for example, Patent Document 1). In such an imaging apparatus, in order to provide high-definition image quality, dark noise of a solid-state imaging device is removed from an output signal.

  Here, the solid-state imaging device will be described with reference to FIGS. FIG. 8 is a configuration diagram of one pixel and a signal readout circuit in a conventional CMOS APS. FIG. 9A is a diagram showing a driving pattern of the solid-state imaging device of FIG. FIG. 9B is a diagram showing the potential of the vertical signal line 208 in FIG.

  In the imaging device, a plurality of pixels 201 shown in FIG. 8 are arranged in a two-dimensional array. Each pixel 201 includes a photodiode (hereinafter referred to as PD) 202, a transfer switch 203, a floating diffusion portion (hereinafter referred to as FD) 204, a reset switch 207, an amplification MOS amplifier 205, and a selection switch 206.

  The PD 202 functions as a photoelectric conversion unit that generates signal charges corresponding to the amount of light incident through the optical system. The anode of the PD 202 is connected to the ground line, and the cathode is connected to the source of the transfer switch 203. The transfer switch 203 is driven by a transfer pulse φTX input to its gate terminal, and transfers the signal charge generated in the PD 202 to the FD 204. The FD 204 functions as a storage unit that temporarily stores signal charges, and also functions as a charge-voltage conversion unit that converts the stored signal charges into voltage signals.

  The amplification MOS amplifier 205 functions as a source follower, and a voltage signal obtained by the charge-voltage conversion function by the FD 204 is input to the gate thereof. The drain of the amplification MOS amplifier 205 is connected to a first power supply VDD1 that provides the first potential, and the drain of the selection switch 206 is connected to the source thereof. The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate. A vertical signal line 208 is connected to the source of the selection switch 206. When the vertical selection pulse φSEL becomes active (high level), the selection switches 206 for the pixels belonging to the corresponding row of the pixel array are turned on, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208.

  The reset switch 207 has a drain connected to a second power supply VDD2 that provides a second potential (reset potential), and a source connected to the FD 204. Further, it is driven by a reset pulse φRES input to its gate, and charges accumulated in the FD 204 are removed.

  The FD 204, the amplification MOS amplifier 205, and the like constitute a floating diffusion amplifier in cooperation with the constant current circuit 209 that supplies a constant current to the vertical signal line 208. In each pixel 201 constituting the row selected by the selection switch 206, the transferred charge is converted into a voltage signal by the FD 204 and output to the corresponding signal readout unit 210 through the floating diffusion amplifier.

  The signal reading unit 210 includes the constant current circuit 209, a plurality of switches 211, 213, 214, 216, a reset level storage capacitor 212, a signal level storage capacitor 215, and a differential amplifier 217.

  The switch 211 is a switch for reading the reset potential of the FD 204 as a reset level signal, and is driven by a reset level read pulse φTN. The reset level storage capacitor 212 stores a reset level signal (a signal having a potential corresponding to the reset level of the FD 204) immediately before the voltage signal is read.

  The switch 214 is a switch for reading a voltage signal corresponding to the signal charge generated in the PD 202, and is driven by a signal read pulse φTS. The signal level storage capacitor 215 stores the voltage signal when reading the voltage signal (a signal having a potential corresponding to the signal charge transferred from the PD 202 to the FD 204).

  The differential amplifier 217 is an amplifier that outputs a difference between the potential of the signal stored in the reset level storage capacitor 212 and the potential of the signal stored in the signal level storage capacitor 215 to the output line 218.

  The switches 213 and 216 are driven by the horizontal signal selection pulse φHi, and transmit the potentials of the reset level storage capacitor 212 and the signal level storage capacitor 215 to the differential amplifier 217, respectively. A value obtained by amplifying the difference between the potential corresponding to the signal charge transferred from the PD 202 to the FD 204 and the reset potential of the FD 204 is output to the output line 218 as a pixel signal.

  Here, common output lines 217a and 217b connected to the input terminals of the differential amplifier 217 have other columns driven by horizontal signal selection pulses φH1 to φH (i−1) and φH (i + 1) to φHn. Switches 213 and 216 are also connected (n indicates the number of columns of the pixel array).

  As shown in FIG. 9A, in the period t401, the reset pulse φRES and the transfer pulse φTX are applied, and the reset switch 207 and the transfer switch 203 are turned on. Then, the potentials of the PD 202 and the FD 204 are reset to the initial potential, and a new exposure period is started upon completion of the reset. Thereafter, the vertical selection pulse φSEL is applied, the selection switch 206 is turned on, and the readout row is selected. When the reading row is selected, as shown in FIG. 9B, the vertical signal line 208 is charged to a potential corresponding to the reset level of the FD 204 during the period t407.

  Next, in a period t402, a reset level read pulse φTN is applied, the switch 211 is turned on, and a value corresponding to the reset potential of the FD 204 is written in the reset level storage capacitor 212. The period t402 needs to be longer than the period t407 necessary for charging the vertical signal line 208.

  Next, in a period t404, the transfer pulse φTX is applied. By applying the transfer pulse φTX, the switch 203 is turned on, and the charge stored in the PD 202 is transferred to the FD 204. At the same time, as shown in FIG. 9B, the vertical signal line 208 is charged to a potential corresponding to the potential of the FD 204 during the period t408.

  Next, in a period t405, the signal read pulse φTS is applied. Then, the switch 214 is turned on and the potential value corresponding to the FD 204 is written in the signal level storage capacitor 215. The period t405 needs to be longer than the period t408 necessary for charging the vertical signal line 208.

  Next, in a period t406, the horizontal signal selection pulse φH is applied, and the switches 213 and 216 are turned on. The difference between the potential of the signal stored in the signal level storage capacitor 215 and the potential of the reset level signal stored in the reset level storage capacitor 212 is amplified by the differential amplifier 217 and output to the output line 218.

  Here, the time for which the vertical signal line 208 is set to the potential corresponding to the voltage signal is determined by the capability of the source follower configured by the MOS amplification up 205 and the constant current circuit 209 working together. That is, the period t407 and the period t408 shown in FIG. 9B are determined by the capabilities of the amplification MOS amplifier 205 and the constant current circuit 209 constituting the source follower.

  As described above, in the conventional solid-state imaging device, the difference between the potential of the signal stored in the signal level storage capacitor 215 and the potential of the reset level signal stored in the reset level storage capacitor 212 is amplified and output. . Thus, fixed pattern noise is reduced, and noise due to variations in the reset switch 207 of the pixel 201 is reduced.

2001-320630

  As the number of pixels of a solid-state image sensor increases, it is necessary to read out signals from the pixels at high speed. Therefore, it is necessary to shorten the charging time of the vertical signal line 208. For this purpose, it is effective to shorten the signal readout period t408 that requires a particularly long charging period. In order to shorten the signal reading period t408, the constant current capability of the constant current circuit 209 may be increased. However, increasing the amount of current in the constant current circuit 209 causes an increase in power consumption.

  An object of the present invention is to provide a solid-state imaging device, a driving method thereof, and an imaging apparatus capable of reading signals from pixels at high speed without causing an increase in power consumption.

  In order to achieve the above object, the present invention includes a pixel including a photoelectric conversion unit that generates a signal charge corresponding to the amount of incident light and a storage unit that stores the signal charge, and resets the potential of the storage unit to a reset potential. And a signal reading unit for reading the potential corresponding to the signal charge stored in the storage unit to a signal line, wherein the signal charge generated by the photoelectric conversion unit is stored in the storage unit. A signal line potential changing unit that changes the potential of the signal line to a predetermined potential different from the reset potential, and the signal reading unit is configured to set the potential of the storage unit reset to the reset potential in the reset period. Read out to the signal line, and in the signal readout period, read out the potential according to the signal charge stored in the storage unit to the signal line, the signal line potential changing means, In the signal line potential change period between the serial reset period and the signal reading period, to provide a solid-state imaging device characterized by changing the potential of the signal line to a predetermined potential.

  Further, in the imaging apparatus including the solid-state imaging device, a photometric unit that measures brightness based on an image captured by the solid-state imaging device, and the predetermined potential based on the brightness measured by the photometric unit. There is provided an imaging apparatus comprising a determining means for determining.

  According to the present invention, it is possible to read a signal from a pixel at high speed without causing an increase in power consumption.

1 is an overall configuration schematic diagram of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a configuration diagram of one pixel and a signal readout unit in the solid-state imaging device 100 of FIG. 1. It is a block diagram of the constant current circuit 209 of FIG. FIG. 3 is a diagram illustrating a driving pattern of a pixel 201 in FIG. 2. FIG. 3 is a diagram showing a state in which the potential of a vertical signal line 208 in FIG. 2 changes. FIG. 3 is a configuration diagram of a circuit using a p-type amplification MOS transistor in the pixel 201 of FIG. 2. FIG. 2 is a configuration block diagram of an imaging apparatus in which the solid-state imaging device of FIG. 1 is used. It is a block diagram of one pixel and a readout circuit in a conventional solid-state imaging device. (A) is a figure which shows the drive pattern of the solid-state image sensor of FIG. FIG. 9B is a diagram showing the potential of the vertical signal line 208 in FIG.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 1 is a schematic diagram of the overall configuration of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a configuration diagram of one pixel and a signal readout unit in the solid-state imaging device 100 of FIG.

  As shown in FIG. 1, the solid-state imaging device 100 includes a pixel array 101, a vertical selection circuit 102, a horizontal selection circuit 104, and a readout circuit 103. The pixel array 101 has a plurality of pixels arranged in a two-dimensional array. The vertical selection circuit 102 is a circuit that sequentially selects a plurality of rows in the pixel array 101. The horizontal selection circuit 104 is a circuit that sequentially selects a plurality of columns of the pixel array so as to sequentially select a plurality of pixels constituting a row selected by the vertical selection circuit 102. The readout circuit 103 is a circuit that reads out signals of pixels selected by the vertical selection circuit 102 and the horizontal selection circuit 104 among the pixels in the pixel array 101.

  The solid-state imaging device 100 includes a timing generator or a control circuit (not shown) that provides timing to the vertical selection circuit 102, the horizontal selection circuit 104, the signal readout circuit 103, and the like in addition to the circuits described above. It is omitted here.

  In the pixel array 101, a plurality of pixels 201 shown in FIG. 2 are arranged in a two-dimensional array. Each pixel 201 includes a photodiode (hereinafter referred to as PD) 202, a transfer switch 203, a floating diffusion portion (hereinafter referred to as FD) 204, a reset switch 207, an amplification MOS amplifier 205, and a selection switch 206.

  The PD 202 functions as a photoelectric conversion unit that generates signal charges corresponding to the amount of light incident through the optical system. The anode of the PD 202 is connected to the ground line, and the cathode is connected to the source of the transfer switch 203. The transfer switch 203 is driven by a transfer pulse φTX input to its gate terminal, and transfers the signal charge generated in the PD 202 to the FD 204. The FD 204 functions as a storage unit that temporarily stores signal charges, and also functions as a charge-voltage conversion unit that converts the stored signal charges into voltage signals.

  The amplification MOS amplifier 205 functions as a source follower, and a voltage signal converted by the charge-voltage conversion function by the FD 204 is input to the gate thereof. The drain of the amplification MOS amplifier 205 is connected to a first power supply VDD1 that provides the first potential, and the drain of the selection switch 206 is connected to the source thereof.

  The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate. A vertical signal line 208 is connected to the source of the selection switch 206. When the vertical selection pulse φSEL becomes active (high level), the selection switches 206 for the pixels belonging to the corresponding row of the pixel array 101 become conductive, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208.

  The reset switch 207 has a drain connected to a second power supply VDD2 that provides a second potential (reset potential), and a source connected to the FD 204. Further, it is driven by a reset pulse φRES input to its gate, and the signal charge accumulated in the FD 204 is removed. As a result, the potential of the FD 204 is reset to the reset potential.

  The FD 204, the amplification MOS amplifier 205, and the like constitute a floating diffusion amplifier in cooperation with a constant current circuit 309 that supplies a constant current to the vertical signal line 208. In each pixel 201 constituting the row selected by the selection switch 206, the transferred charge is converted into a voltage signal in the FD 204 and output to the corresponding signal readout unit 310 through the floating diffusion amplifier. The signal reading unit 310 is included in the reading circuit 103.

  The signal readout unit 310 includes a plurality of switches 211, 213, 214, 216, 219, a reset level storage capacitor 212, a signal level storage capacitor 215, and a differential amplifier 217.

  The switch 211 is a switch for reading the reset potential of the FD 204 as a reset level signal, and is driven by a reset level read pulse φTN. The reset level storage capacitor 212 stores a reset level signal (a signal having a potential corresponding to the reset level of the FD 204) immediately before the voltage signal is read.

  The switch 214 is a switch for reading a voltage signal corresponding to the signal charge generated in the PD 202, and is driven by a signal read pulse φTS. The signal level storage capacitor 215 stores the voltage signal (a signal having a potential corresponding to the signal charge transferred from the PD 202 to the FD 204) when the voltage signal is read.

  The differential amplifier 217 is an amplifier that outputs a difference between the signal potential stored in the reset level storage capacitor 212 and the signal potential stored in the signal level storage capacitor 215 to the output line 218. Specifically, the potentials of the reset level storage capacitor 212 and the signal level storage capacitor 215 are input to the input terminals of the differential amplifier 217 through the common output lines 217a and 217b by the switches 213 and 216, respectively. The The differential amplifier 217 amplifies the difference between the potential corresponding to the signal charge transferred from the PD 202 to the FD 204 and the potential of the FD 204 in the reset state, and outputs the amplified value to the output line 218 as a pixel signal.

  Each of the switches 213 and 216 is driven by a horizontal signal selection pulse φHi. In addition, common output lines 217a and 217b connected to the input terminals of the differential amplifier 217 have switches in other columns driven by horizontal signal selection pulses φH1 to φH (i−1) and φH (i + 1) to φHn. 213 and 216 are also connected. Here, n represents the number of columns of the pixel array 101. The switch 219 is a switch that forcibly changes the potential of the vertical signal line 208 to the potential (predetermined potential) of the third power supply VDD3, and is driven by a pulse φFS.

  Next, the configuration of the constant current circuit 309 will be described with reference to FIG. FIG. 3 is a diagram showing a configuration of the constant current circuit 309 of FIG.

  As shown in FIG. 3, the constant current circuit 309 includes a constant current transistor 301 formed of a MOS transistor, and is a circuit for obtaining constant current characteristics by using the constant current transistor 301 in a saturation characteristic region. A vertical signal line 208 is connected to the drain of the constant current transistor 301 via the constant current circuit cutoff switch 302, and the source is connected to the GND potential (ground potential). A voltage Vi is applied to the gate of the constant current transistor 301, and a drain current corresponding to the voltage Vi is used as a constant current.

  The constant current circuit cutoff switch 302 is driven by a pulse φPS. The constant current circuit cutoff switch 302 connects the constant current transistor 301 to the vertical signal line 208 when the pulse φPS is active (high level), and disconnects the constant current transistor 301 from the vertical signal line 208 when it is inactive.

  Next, driving of the pixel 201 in the solid-state imaging device 100 will be described with reference to FIG. FIG. 4 is a diagram showing a drive pattern of the pixel 201 in FIG.

  In a period t401, the reset pulse φRES and the transfer pulse φTX are applied, and the reset switch 207 and the transfer switch 203 are turned on. As a result, the potentials of the PD 202 and the FD 204 are reset to the initial potential, and a new exposure period is started upon completion of the reset. Thereafter, the vertical selection pulse φSEL is applied, and the selection switch 206 is turned on. As a result, the readout row is selected, and the potential of the FD 204 reset to the reset potential is read out to the vertical signal line 208 (reset period).

  Next, in a period t402, a reset level read pulse φTN is applied, and the switch 211 is turned on. As a result, the potential of the vertical signal line 208 is written to the reset level storage capacitor 212.

  Next, in a period t403 (signal line potential change period), the selection pulse φSEL and the pulse φPS become inactive, and the switch 206 and the constant current circuit cutoff switch 302 are turned off. Further, the operation of the amplification MOS amplifier 205 functioning as the source follower is stopped and the pulse φFS is activated, and the potential of the vertical signal line 208 changes to a potential corresponding to the third power supply VDD3 via the switch 219. . Thereafter, the vertical selection pulse φSEL and the pulse φPS are made active and the pulse φFS is made inactive, and reading of the signal from the pixel 201 is resumed.

  Next, in a period t404 (signal reading period), the transfer pulse φTX is applied. By applying the transfer pulse φTX, the switch 203 is turned on, and the signal charge accumulated in the PD 202 is transferred to the FD 204. At the same time, the vertical signal line 208 is charged to a potential corresponding to the voltage signal of the FD 204 during the period t405. In the period t405, the signal readout pulse φTS is applied to turn on the switch 214, and a potential corresponding to the voltage signal of the FD 204 is written in the signal level storage capacitor 215.

  Next, in a period t406, the vertical signal selection pulse φHi is applied. As a result, the switches 213 and 216 are turned on, and the difference between the potential of the signal level storage capacitor 215 and the potential of the reset level storage capacitor 212 is amplified by the differential amplifier 217 and output to the output line 218 as a pixel signal.

  Here, in the case where the constant current transistor 301 is formed of an nMOS transistor, the potential of the third power supply VDD3 may be equal to or lower than the potential of the vertical signal line 208 corresponding to the FD 204 after reset in the period t402. Thus, the period t404, that is, the signal reading period can be shortened.

  Next, a change in the potential of the vertical signal line 208 will be described with reference to FIG. FIG. 5 is a diagram showing a state in which the potential of the vertical signal line 208 in FIG. 2 changes.

  In the period t402, as described above, the potential of the vertical signal line 208 becomes the potential of the FD 204 reset to the reset potential. Generally, the FD 204 after reset includes reset noise and the like. If the influence of the reset noise is slight, the potential of the FD 204 after reset is substantially equivalent to the potential of the second power supply VDD2 (denoted as reset potential VDD2) as shown in FIG. A potential obtained by subtracting the threshold voltage Vth of the transistor 205 from the reset potential VDD2 is written to the vertical signal line 208 after reset. Here, for convenience, it is assumed that the threshold voltage Vth is extremely small, and the potential of the vertical signal line 208 corresponding to the FD 204 in the reset state is the reset potential VDD2.

  Next, in the period t403, the potential of the vertical signal line 208 becomes the potential of the third power supply VDD3 (denoted as potential VDD3), and in the period t405, the potential corresponds to the potential of the FD 204 after signal charge transfer from the PD 202.

  Here, a case where the potential of the vertical signal line 208 in the period t405 is any one of the potentials VDDa, VDDb, and VDDc is considered.

  The potential VDDc is the potential of the vertical signal line 208 when the signal charge amount transferred from the PD 202 to the FD 204 is maximum, and the potential VDD3 is between the potential VDDa and the potential VDDb for convenience. Further, the amount of charge / discharge of the vertical signal line 208 is correctly described as signal charge, but here, it is described as potential for convenience.

  First, a case where the potential of the vertical signal line 208 is the potential VDDb or VDDc is considered. In this case, the amount of potential movement necessary for discharging the vertical signal line 208 is an amount corresponding to VDD3-VDDb or VDD3-VDDc. The amount of discharge in this case is smaller than the amount of discharge when the potential of the vertical signal line 208 is not set to the potential VDD3 in the period t403. Therefore, the discharge period is shortened, and the period t405 can be shortened.

  Next, consider a case where the potential of the vertical signal line 208 is VDDa. Here, the potential VDDa is an intermediate potential between the potential VDD3 and the potential VDD2. Since the potential VDD3 is lower than the potential VDDa, the vertical signal line 208 is charged via the amplification MOS amplifier 205 functioning as a source follower, and the charge amount is VDD3-VDDa.

  On the other hand, when the potential of the vertical signal line 208 is not set to the potential VDD3 in the period t403, the vertical signal line 208 is discharged through the constant current circuit 309, and the amount of discharge becomes VDD2-VDDa. Here, regarding the charge / discharge capability of the vertical signal line 208, if the constant current circuit 309 sets a small amount of current in order to suppress power consumption, the charge capability of the amplification MOS amplifier 205 is greater than the discharge capability of the constant current circuit 309. Become. Therefore, the charge of the charge amount (VDD3-VDDa) converges in a shorter time than the discharge of the discharge amount (VDD2-VDDa).

  As described above, by making the potential VDD3 lower than the reset potential VDD2, the charge / discharge time of the vertical signal line 208 can be shortened, so that the period t404 (signal readout period) can be shortened. In addition, regarding the period t405, it is necessary to secure a sufficient time according to the amount of signal charge generated in the PD 202. Therefore, considering that the time required for charging the vertical signal line 208 is shorter than the time required for discharging, the potential VDD3 is desirably set to a potential corresponding to the maximum amount of signal charge generated and held in the PD 202. In other words, if the potential VDD3 is made lower than the potential VDDc of the vertical signal line 208 when the amount of signal charge transferred to the FD 204 is the largest, charging / discharging of the vertical signal line 208 takes the longest time. The charging / discharging time of the vertical signal line 208 can be shortened.

  Further, when the exposure amount of the solid-state imaging device 100 is determined by photometry before photographing, the potential VDD3 can be determined according to the photometric amount. This will be described later.

  When the potential VDD3 (the third power supply VDD3) may be the GND potential, the constant current transistor 301 is connected to the GND potential, so that the potential of the vertical signal line 208 is set to the period using the constant current circuit 309. It can be set to the GND potential during t403. In that case, a wiring for connecting the switch 219 and the third power supply VDD3 becomes unnecessary, and the chip area can be reduced.

  In this case, a driving method is used in which the vertical selection pulse φSEL is deactivated and the pulse φPS is activated in the period t403 in FIG. According to this, only the constant current circuit 209 is connected to the vertical signal line 208, and the constant current transistor 301 does not operate as a constant current transistor. That is, the vertical signal line 208 is connected to the GND potential via the constant current transistor 301.

  In the present embodiment, an n-type amplifying MOS transistor 205 constituting the source follower is used. However, a p-type amplifying MOS transistor can be used instead.

  The configuration in this case will be described with reference to FIG. FIG. 6 is a diagram showing a circuit configuration using a p-type amplifying MOS transistor in the pixel 201 of FIG.

  As shown in FIG. 6, the pixel 201 is provided with a p-type amplification MOS amplifier 805 and a selection switch 806 instead of the n-type amplification MOS amplifier 205 and the selection switch 206. In addition, the signal readout unit 310 is provided with a constant current circuit 809 composed of a p-type transistor.

  The configuration of FIG. 6 is a configuration in which the relationship between charging and discharging is reversed with respect to the configuration of FIG. In such a configuration, by setting the potential VDD3 higher than the reset potential VDD2, the charge / discharge time of the vertical signal line 208 can be shortened under the condition that the charge / discharge of the vertical signal line 208 takes the longest time.

  As described above, according to the present embodiment, the constant current circuits 309 and 809 reduce the time of the signal readout period in which the transient response time is determined without increasing the constant current amount of the constant current circuits 309 and 809. be able to. That is, the signal can be read from the pixel 201 at a high speed without increasing the power consumption.

  Next, an imaging apparatus using the solid-state imaging device will be described with reference to FIG. FIG. 7 is a block diagram showing the configuration of an image pickup apparatus using the solid-state image pickup device shown in FIG.

  The imaging apparatus includes an optical system 1, a shutter 2, a solid-state imaging device 100, and a drive circuit 7. The optical system 1 includes a lens and a diaphragm (not shown). The shutter 2 is a focal plane mechanical shutter. The solid-state imaging device 100 has the above-described configuration, converts a light image of a subject formed through the optical system 1 into an electrical signal, and outputs the electrical signal. The drive circuit 7 generates drive signals (drive pulses) for driving the lens and diaphragm of the optical system 1, the shutter 2, and the solid-state imaging device 100 based on the timing signal generated by the timing signal generation circuit 6.

  The electrical signal output from the solid-state imaging device 100 is input to a CDS (Correlated Double Sampling) circuit 4. The CDS circuit 4 performs correlated double sampling processing for removing amplifier noise and the like on the input electric signal based on the sampling signal generated by the timing signal generation circuit 6 and outputs an analog signal. The analog signal is input to the A / D conversion circuit 5.

  The A / D conversion circuit 5 samples the input analog signal based on the sampling signal generated by the timing signal generation circuit 6 and converts it into a digital signal. This digital signal is input to the signal processing circuit 8 as an image signal.

  The timing signal generation circuit 105 generates a timing signal for the drive circuit 7 according to the reference clock, and generates a sampling signal for the CDS circuit 4 and the A / D conversion circuit 5.

  The signal processing circuit 8 performs various processes such as image processing including color conversion, white balance, gamma correction, resolution conversion processing, and compression / decompression processing on the input image signal. The image signal processed by the signal processing circuit 8 is stored in the image memory 9. The image memory 9 temporarily stores the image signal input to the signal processing circuit 8. An image signal (processed image signal) stored in the image memory 9 is input to the recording circuit 11 or the display circuit 13 via the signal processing circuit 8.

  Further, the signal processing circuit 8 includes a photometric circuit (not shown) that measures brightness based on a luminance signal obtained from the input image signal, and the photometric quantity indicating the brightness measured by the photometric circuit. Is output to the system control unit 14.

  The recording circuit 11 compresses the input image data as necessary, and records it on the removable recording medium 10. The recording circuit 11 reads image data recorded on the recording medium 10. The image data read from the recording medium 10 is expanded by the signal processing circuit 8 and then input to the display circuit 11. The display circuit 11 performs display control for displaying input image data on an LCD (liquid crystal display panel) 12.

  The drive circuit 7, the timing signal generation circuit 7, the signal processing circuit 8, the image memory 9, the recording circuit 11, and the display circuit 13 are controlled by the system control unit 14. The system control unit 14 includes a CPU 15, a ROM 16, a RAM 17, and the like. The CPU 15 controls the entire apparatus and performs individual control according to programs and parameters stored in the ROM 16. The RAM 17 provides a work area for the CPU 15.

  In the imaging apparatus having such a configuration, the driving method for the solid-state imaging device 100 is as described above, and the driving of the solid-state imaging device 100 is performed via the driving circuit 7.

  Further, in the individual control performed by the CPU 15, when determining the exposure amount of the solid-state imaging device 100 by measuring the light before photographing, the potential of the power supply VDD3 (potential VDD3) is determined according to the photometric amount obtained by the photometric circuit. Control to determine is included. With this control, an appropriate potential of the power supply VDD3 can be determined and set.

201 pixels 202 photodiode (PD)
203 Transfer switch 204 Floating diffusion part (FD)
205, 805 Amplification MOS amplifier 206, 806 Select switch 207 Reset switch 208 Vertical signal line 309, 809 Constant current circuit 310 Signal readout unit

Claims (6)

A pixel including a photoelectric conversion unit that generates a signal charge corresponding to the amount of incident light and a storage unit that stores the signal charge, and the photoelectric conversion unit generated after the potential of the storage unit is reset to a reset potential A solid-state imaging device that accumulates signal charges in the accumulation unit,
A signal readout means for reading out a potential corresponding to the signal charge stored in the storage unit to a signal line;
Signal line potential changing means for changing the potential of the signal line to a predetermined potential different from the reset potential;
The signal readout means reads out the potential of the storage unit reset to the reset potential in the reset period to the signal line, and outputs a potential corresponding to the signal charge stored in the storage unit in the signal readout period. Read out on the line,
The signal line potential changing unit changes the potential of the signal line to a predetermined potential in a signal line potential changing period between the reset period and the signal readout period.   The solid-state imaging device according to claim 1, wherein the predetermined potential is lower than the reset potential. The signal reading means comprises source follower means including an amplification MOS transistor and a constant current circuit,
2. The solid-state imaging device according to claim 1, wherein the predetermined potential is lower than a potential obtained by subtracting a threshold voltage of the amplification MOS transistor from a potential corresponding to a maximum signal charge amount accumulated in the accumulation unit.   The solid-state imaging device according to claim 1, wherein the predetermined potential is higher than the reset potential. The signal reading means comprises source follower means including an amplification MOS transistor and a constant current circuit,
2. The solid-state imaging device according to claim 1, wherein the predetermined potential is higher than a potential obtained by subtracting a threshold voltage of the amplification MOS transistor from a potential corresponding to a maximum signal charge amount accumulated in the accumulation unit. An imaging apparatus including the solid-state imaging device according to claim 1,
Photometric means for measuring brightness based on an image captured by the solid-state imaging device;
An image pickup apparatus comprising: a determination unit that determines the predetermined potential based on brightness measured by the photometry unit.

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