JP2010182845A - Nonvolatile memory device - Google Patents

Abstract

When performing erasing of a MONOS type nonvolatile memory, it is necessary to use a negative power source even when an erasing method using an FN current is used or an erasing using an interband tunneling hot hole is performed. It becomes. In order to use a negative power supply, it is necessary to design a wiring pattern so that it can be electrically separated separately, and there is a problem that restrictions are imposed on the wiring pattern.
A drain region 203D and a source region 203S are formed so as to have a junction depth of 10 nm or more and 500 nm or less. Since the electric field strength in the drain region 203D and the source region 203S can be increased, an interband tunneling hot hole can be generated by grounding the gate electrode 206 and supplying a potential of about 5 [V] to the drain region 203D. It is possible to perform erasing without using a negative power source.
[Selection] Figure 2

Description

  The present invention relates to a nonvolatile memory device.

  In recent years, non-volatile memory devices using a flat-type MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory element as a memory element have been adopted because of the simplicity of the process. The flat plate type MONOS memory element is roughly divided into two types, one that writes and erases charges by controlling an FN (Fowler-Nordheim) current and one that writes and erases charges using hot carriers. is there. A flat-type MONOS memory element using an FN current is described in Patent Document 1, for example. As shown in Patent Document 1, in order to erase using an FN current, a potential of about −7 [V] is used for the gate electrode and about 8 [V] is used for the substrate.

  On the other hand, in the type in which charge is written / erased using hot carriers, as will be described later, charge can be written / erased with a lower bias voltage than in the type in which the FN current is controlled. Therefore, EOT (Equivalent Oxide Thickness: Equivalent (Thickness of silicon oxide) can be set thinner than that of the type that controls the FN current.

  Therefore, even when a low gate bias is used, the read current value can be set higher than that of the type that controls the FN current, and parasitic capacitance and the like can be charged quickly, which is suitable for high-speed operation. It has characteristics.

  In a flat MONOS memory element, when performing an erase operation, a voltage higher than the drain-source breakdown voltage cannot be applied to the drain, so a positive potential is applied to the drain region and a negative potential is applied to the gate electrode. A method of performing an erasing operation is known. As a specific example, as shown in Patent Document 2, a potential of about 4 to 7 [V] is applied to the drain region, and −4. To the gate electrode (described as a control gate in Patent Document 2). By applying a potential of about 5 [V], an interband tunneling hot hole (Band-To-Band Tunneling Hot-Hole: BTBTHH) is generated, and the erase operation is performed by this charge. This is the same problem even when a P-type non-volatile memory element is used and band-to-band tunneling hot-electron (BTBTHE) is used as an erasing operation.

JP 2007-184380 A (paragraph: 0089) JP 2008-269727 A (paragraph: 0039 (Table 1))

  Even when the erasing method using the FN current is used or when erasing using the BBTTHH is performed, it is necessary to use a negative power source (a positive power source in the case of the P type). In order to use a negative power supply, it is necessary to design a wiring pattern so that it can be electrically separated separately, and there is a problem that restrictions are imposed on the wiring pattern. In Patent Document 2, if the voltage applied to the drain region is about 6.5 [V], a breakdown voltage of 11 [V] is required as the breakdown voltage of the ONO layer of the MONOS memory element. Inevitably, the ONO layer needs to be thickened to increase the withstand voltage, and the current value at the time of data reading decreases as the ONO layer becomes thicker. Therefore, there is a problem that the configuration of the sense amplifier is restricted to detect a small current.

  In addition, it is necessary to incorporate a negative power generation circuit in the non-volatile memory device to supply a negative power, and the memory area of the non-volatile memory device decreases corresponding to this area. There is a problem that the cost increases.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples. Here, the “semiconductor layer” is defined as “semiconductor substrate itself” and “semiconductor layer covering at least part of the insulating layer”. Further, “upper” is defined to indicate the normal direction of the semiconductor layer from the semiconductor layer toward the gate electrode.

Application Example 1 A nonvolatile memory device according to this application example includes a semiconductor layer, a first insulating layer provided on the semiconductor layer, and a charge storage layer provided on the first insulating layer. A gate insulating layer including a second insulating layer provided on the charge storage layer; and a gate electrode disposed on the gate insulating layer, wherein the semiconductor layer has an N-type conductivity type. A source region including an impurity to be generated, a drain region including an impurity to generate an N-type conductivity, and the gate electrode is disposed under the gate electrode, and the source in the plan view of the semiconductor layer And a channel region sandwiched between the drain region, and the drain region is 7 × 10 ²⁰ cm ⁻³ or more at a position where the gate electrode and the drain region overlap in a plan view of the semiconductor layer. , 1 × 10 ²² cm ^-3 or less Characterized in that it comprises a non-volatile memory device including an impurity generating an N type conductivity at a concentration.

According to this, it is possible to generate a strong drain electric field at the end of the gate electrode by including 7 × 10 ²⁰ cm ⁻³ or more of impurities that generate N-type conductivity. For this reason, band-to-band tunneling hot holes (BTTBTHH) are generated even when a small potential difference is used. Specifically, BBTTHH is generated by grounding the source region and the gate electrode and applying a potential of about 5 [V] only to the drain region, and the charges stored in the charge storage layer are canceled and erased. Is possible. In addition, by controlling to 1 × 10 ²² cm ⁻³ or less, the properties of the semiconductor can be maintained.

  Further, since the electric field intensity generated in the drain region can be extremely increased even with a low driving voltage, channel hot electron writing can be performed with high efficiency. For example, a potential of 7 [V] is applied to the gate electrode, Writing can be performed by applying a potential of 5 [V] to.

Application Example 2 A nonvolatile memory device according to this application example includes a semiconductor layer, a first insulating layer provided on the semiconductor layer, a charge storage layer provided on the first insulating layer, A gate insulating layer including a second insulating layer provided on the charge storage layer; and a gate electrode disposed on the gate insulating layer, wherein the semiconductor layer has a P-type conductivity type. A source region containing an impurity to be generated, a drain region containing an impurity generating a P-type conductivity type, and a channel region sandwiched between the source region and the drain region in a plan view of the semiconductor layer on the surface of the semiconductor layer And the gate insulating layer and the gate electrode are disposed on the channel region, and the drain region is located at a position overlapping the gate electrode and the drain region in a plan view of the semiconductor layer. × 10 ²⁰ c ^-3, characterized in that it comprises a non-volatile memory device including an impurity for generating a P-type conductivity at a concentration of 1 × 10 ²² cm ^-3 or less.

According to this, it is possible to generate a strong drain electric field at the end portion of the gate electrode by including 7 × 10 ²⁰ cm ⁻³ or more of impurities that generate the P-type conductivity type. For this reason, band-to-band tunneling hot electrons (BTBTHE) are generated even when a small potential difference is used. By grounding the source region and the gate electrode and applying a potential of about −5 [V] only to the drain region, BTBTHE is generated, and the charge stored in the charge storage layer can be offset and erased. . In addition, by controlling to 1 × 10 ²² cm ⁻³ or less, the properties of the semiconductor can be maintained.

  In addition, since the electric field strength generated in the drain region can be extremely increased, channel hot hole writing can be performed with high efficiency. For example, a potential of −7 [V] is applied to the gate electrode and −5 is applied to the drain region. Writing can be performed by applying a potential of [V]. In this case, a negative power source is used for the operation of the non-volatile memory element. However, in the region where the non-volatile memory element is provided, the positive and negative power sources are electrically separated because no positive power source is required. Since the configuration is unnecessary, there is no restriction on the wiring pattern.

  Application Example 3 In the nonvolatile memory device according to the application example described above, as a writing method to the nonvolatile memory element, charges are injected into the charge storage layer using channel hot carriers.

  According to the application example described above, since the electric field strength generated in the drain region can be extremely increased, channel hot carrier (electron or hole) writing can be performed with high efficiency. Therefore, for example, writing can be performed by applying a potential of 7 [V] to the gate electrode and a potential of 5 [V] to the drain region, and the potential difference applied to the gate insulating layer is determined using an FN (Fowler-Nordheim) current. The potential difference applied to the gate insulating layer can be reduced compared to the case of writing. Further, when charge is injected into the charge storage layer using channel hot carriers, the charge is written near the drain side of the charge storage layer in plan view. On the other hand, when band-to-band tunneling hot carriers are used, the erase efficiency is increased in the vicinity of the drain side of the charge storage layer, so that it is possible to suppress the occurrence of unerased residue.

  Application Example 4 In the nonvolatile memory device according to the application example described above, the gate insulating layer has a thickness of 10 nm or more and 16 nm or less.

According to the application example described above, if the gate insulating layer has a thickness of 10 nm or more, it can withstand a potential difference of, for example, about 7 [V] applied during writing. Further, if the layer thickness is 16 nm or less, an increase in leakage current due to the short channel effect between the drain region and the source region having a concentration of about 7 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less is suppressed. It becomes possible. In addition, by setting the layer thickness to 16 nm or less, it is possible to generate a strong electric field even when the potential difference applied between the gate and the drain is as small as about 5 [V], and the interband tunneling hot carrier is generated. Can be generated efficiently.

  Application Example 5 In the nonvolatile memory device according to the application example described above, the source region and the drain region have a junction depth of 10 nm or more and 500 nm at the gate electrode end in a plan view of the semiconductor layer. It is characterized by the following.

  According to the application example described above, by providing a junction depth of 10 nm or more, an increase in electrical resistance of the source region and the drain region can be suppressed, and reading can be performed at a high speed. Further, by setting the junction depth to 500 nm or less, punch-through between the source region and the drain region can be suppressed, and an electric field can be efficiently supplied when writing or erasing is performed. Note that when a “semiconductor layer covering at least part of the insulating layer” is used as the semiconductor layer, the junction depth is limited by the thickness of the semiconductor layer.

  Application Example 6 A nonvolatile memory device according to the application example described above, wherein the nonvolatile memory device is located in a region that does not contact the gate electrode in the plan view of the semiconductor layer in the source region, and the source region A source contact region that exhibits the same conductivity type and reduces a sheet resistance of the source region; and a region in the drain region that is not in contact with the gate electrode in plan view of the semiconductor layer, and the drain region A drain contact region that reduces the sheet resistance of the drain region, and a region that exhibits a non-depleted reverse conductivity type is provided between the source contact region and the drain contact region. It is characterized by being sandwiched.

  According to the application example described above, since the drain contact region and the source contact region are provided in the region not in contact with the gate electrode, the low resistance region is arranged in parallel on at least one side of the source region or the drain region. The resistance value can be reduced, and the reading operation can be speeded up. Further, since the drain contact region and the source contact region are arranged avoiding the vicinity of the gate electrode in plan view of the semiconductor layer, the influence on the generation of interband tunneling hot carriers can be suppressed to a low level of about 5 [V]. It is possible to perform an erasing operation with a voltage. Furthermore, it is possible to suppress the occurrence of a short channel effect that generates a leakage current.

  Application Example 7 In the nonvolatile memory device according to the application example described above, the concentration of the first impurity constituting the conductivity type opposite to that of the drain region is higher than the concentration of the first impurity included in the channel region. A depletion suppression region that is higher and lower in concentration than the second impurity constituting the same conductivity type as the drain region, and the depletion suppression region is located inside the gate electrode in a plan view of the semiconductor layer. It is characterized by covering the area.

  According to the application example described above, by providing the depletion suppression region, it is possible to suppress the extension of the depletion layer in the drain region. Therefore, when detecting a current that depends on the charge of the charge storage layer of the nonvolatile memory element, it is possible to suppress generation of an error current due to punch-through.

  In addition, when canceling and erasing charges contained in the charge storage layer by interband tunneling hot carrier injection, it is possible to more efficiently perform interband tunneling hot carrier injection because the expansion of the depletion layer is suppressed. Become.

  Application Example 8 In the nonvolatile memory device according to the application example described above, the first insulating layer and the second insulating layer are made of silicon oxide, and the charge storage layer is made of silicon nitride. It is characterized by.

  According to the application example described above, silicon oxide has a low Young's modulus, and stress applied to a region formed of a semiconductor can be suppressed. In addition, the electrical insulation rate of silicon oxide is high, and it becomes possible to stop the outflow of charges from the charge storage layer. In addition, since silicon nitride has an appropriate intermediate level, the injected charge can be efficiently stored and released. Thus, since a gate insulating layer capable of controlling the amount of accumulated charge can be obtained, a nonvolatile memory element can be configured, and a nonvolatile memory device including the nonvolatile memory element can be provided. It becomes.

  Application Example 9 In the nonvolatile memory device according to the application example described above, silicon nitride is used for the second insulating layer.

  According to the application example described above, it is possible to form a layer that also serves as the charge storage layer and the second insulating layer, it is possible to reduce the components of the nonvolatile memory device, and reduce variations and the like. It becomes possible. In addition, it is possible to provide a non-volatile memory device that can shorten the manufacturing process and reduce the cost.

  Application Example 10 In the nonvolatile memory device according to the application example described above, the silicon oxide layer serving as the first insulating layer has a layer thickness of 2 nm or more and 5 nm or less.

  According to the application example described above, by ensuring a layer thickness of 2 nm or more, it is possible to suppress the outflow of charges from the charge storage layer to the region formed of the semiconductor. By using a layer thickness of 5 nm or less, the current control efficiency of the channel region can be increased by the charges accumulated in the charge accumulation layer, and a nonvolatile memory device with few read errors can be provided.

An arrangement example of a circuit equivalent to a nonvolatile memory device in which four nonvolatile memory elements are arranged side by side. Sectional drawing of a non-volatile memory element. FIG. 3 is a cross-sectional view of a structure showing a nonvolatile memory element when an SOI substrate is used. Sectional drawing at the time of forming a non-volatile memory element using the semiconductor layer using the polycrystalline-silicon layer arrange | positioned on the glass substrate.

  Hereinafter, embodiments embodying the present invention will be described with reference to the drawings.

(First Embodiment: Configuration of Nonvolatile Memory Device)
The configuration of the nonvolatile memory device according to this embodiment will be described below with reference to the drawings. FIG. 1 shows an arrangement example of a circuit equivalent to the nonvolatile memory device 100 in which four nonvolatile memory elements MC00, MC01, MC10 and MC11 are arranged side by side. Here, in order to explain the operation, an example in which four elements are arranged is described, but actually, a large number of elements are provided as one block. In addition to this, a booster circuit, a sense amplifier, and the like are mounted on the nonvolatile memory device, but description thereof is omitted. The nonvolatile memory element MC00 includes a drain D00 as a drain region, a source S00 as a source region, and a gate G00 as a gate electrode. The nonvolatile memory element MC01 includes a drain D01 as a drain region, a source S01 as a source region, and a gate G01 as a gate electrode. The nonvolatile memory element MC10 includes a drain D10 as a drain region, a source S10 as a source region, and a gate G10 as a gate electrode. The nonvolatile memory element MC11 includes a drain D11 as a drain region, a source S11 as a source region, and a gate G11 as a gate electrode.

  In the case where charges (hot electrons) are written (injected) into the charge storage layer on the drain D10 side of the nonvolatile memory element MC10, the following bias conditions can be used. The bias conditions are, for example, that the potential of the bit line BL0 is 0 [V], the potential of the bit line BL1 is 3 [V], the potential of the source line SL0 is 0 [V], the potential of the source line SL1 is 5 [V], It is preferable to set the potential of the word line WL0 to 7 [V] and the potential of the word line WL1 to 0 [V].

  Hereinafter, the potential applied to each of the nonvolatile memory elements MC00, MC01, MC10, and MC11 when this bias condition is used and the operation by applying the potential will be described.

  Since the non-volatile memory element MC00 is given a potential of 0 [V] to the drain D00, 0 [V] to the source S00, and 0 [V] to the gate G00, writing or erasing is not performed.

  In the nonvolatile memory element MC01, a potential of 0 [V] is applied to the drain D01, 3 [V] to the source S01, and 0 [V] to the gate G01. Since the potential of the source S01 is 3 [V], hot carriers are not generated and writing or erasing is not performed.

  In the nonvolatile memory element MC11, a potential of 5 [V] is applied to the drain D11, 3 [V] to the source S11, and 7 [V] to the gate G11. Since the potential difference applied between the potential of the drain D11 and the source S11 is 2 [V], hot carriers are not generated and writing and erasing are not performed.

  The nonvolatile memory element MC10 is supplied with a potential of 5 [V] at the drain D10, 0 [V] at the source S10, and 7 [V] at the gate G10. Therefore, writing by hot carriers is performed.

  Further, as a bias condition for reading the presence / absence of charges in the charge storage layer on the drain D10 side of the nonvolatile memory elements MC10 and MC11, the following bias condition can be used. For example, the potential of the source line SL0 is set to 0 [V], the potential of the source line SL1 is set to 1 [V], the potential of the word line WL0 is set to 2 [V], and the potential of the word line WL1 is set to 0 [V]. Is preferred.

  Hereinafter, the potential applied to each of the nonvolatile memory elements MC00, MC01, MC10, and MC11 when this bias condition is used and the operation by applying the potential will be described.

  Since the non-volatile memory element MC00 is given a potential of 0 [V] to the drain D00 and 0 [V] to the gate G00, the non-volatile memory element MC00 is cut off. Therefore, the source S00 is in a float state.

  Since the non-volatile memory element MC01 is given a potential of 0 [V] to the drain D01 and 0 [V] to the gate G01, the non-volatile memory element MC01 is cut off. Therefore, the source S01 is in a float state.

  In the nonvolatile memory element MC11, a potential of 1 [V] is applied to the drain D11 and 2 [V] is applied to the gate G11. Even when a large number of nonvolatile memory elements are connected, the nonvolatile memory element MC11 can be selected by setting the gate potential other than the gate G11 to 0 [V]. This output is output to the bit line BL1. Since the output of the nonvolatile memory element MC11 varies depending on the charge state of the nonvolatile memory element MC11, the charge state of the nonvolatile memory element MC11 can be detected from the signal of the bit line BL1.

  In the nonvolatile memory element MC10, a potential of 1 [V] is applied to the drain D10 and 2 [V] is applied to the gate G10. Even when a large number of nonvolatile memory elements are connected, the nonvolatile memory element MC10 can be selected by setting the gate potential other than the gate G10 to 0 [V]. This output is output to the bit line BL0. Since the output of the nonvolatile memory element MC10 varies depending on the charged state of the nonvolatile memory element MC10, the charged state of MC10 can be detected from the signal of the bit line BL0. That is, the information selected by the word line (WL0 in this embodiment) can be read for one word line.

  Further, by sector erasing, the charges on the drain D00, drain D10, drain D01, and drain D11 side in the charge storage layer of the nonvolatile memory element MC00, nonvolatile memory element MC10, nonvolatile memory element MC01, and nonvolatile memory element MC11 are reduced. As bias conditions for erasing, the following bias conditions can be used. For example, the potential of the source line SL0 is 5 [V], the potential of the source line SL1 is 5 [V], the potential of the bit line BL0 is 0 [V], the potential of the bit line BL1 is 0 [V], and the potential of the word line WL0 It is preferable to set the potential to 0 [V] and the potential of the word line WL1 to 0 [V].

  The nonvolatile memory element MC00 is supplied with a potential of 5 [V] at the drain D00, 0 [V] at the gate G00, and 0 [V] at the source S00. Therefore, erasure is performed by band-to-band tunneling hot holes (BTBTHH) due to a potential difference applied between the drain D00 and the gate G00.

  Similarly, the non-volatile memory element MC10 has a potential of 5 [V] applied to the drain D10, 0 [V] applied to the gate G10, and 0 [V] applied to the source S10.

  Further, since the non-volatile memory element MC01 is given a potential of 5 [V] to the drain D01, 0 [V] to the gate G01, and 0 [V] to the source S01, the charge is erased.

  Further, since the nonvolatile memory element MC11 is supplied with a potential of 5 [V] at the drain D11, 0 [V] at the gate G11, and 0 [V] at the source S11, the charge is erased.

  The basic operations of the nonvolatile memory device 100 such as writing, reading, and erasing have been described above. From these, it is shown that the basic operation is not hindered even when the negative potential is not used. Therefore, it is possible to avoid a wiring pattern restriction that occurs due to the use of a negative potential. Further, since it is not necessary to incorporate a negative power generation circuit for supplying negative power in the nonvolatile memory device 100, the nonvolatile memory device 100 can take a large memory area of the nonvolatile memory device in accordance with the area, and is nonvolatile. It is possible to reduce the cost per unit bit of the memory device.

  In this embodiment, the case where an N-type nonvolatile memory element is used has been described. However, this can be easily applied to a nonvolatile memory device using a P-type nonvolatile memory element by switching the polarity. Is possible. In that case, it is possible to cope with this by applying a negative voltage in which the absolute values of the voltages described above are aligned. Note that there is a difference in electric field strength for making hot carriers between electrons and holes, and holes are less likely to become hot carriers. Therefore, it is also preferable to compensate by increasing the absolute value of the applied voltage.

(Second Embodiment: Structure of Nonvolatile Memory Element Used in Nonvolatile Memory Device)
Hereinafter, the structure of the nonvolatile memory element constituting the nonvolatile memory device according to the present embodiment will be described with reference to the drawings. FIG. 2 is a cross-sectional view of the nonvolatile memory element. The nonvolatile memory element MC10 includes a substrate 200 as a semiconductor layer, a shallow trench isolation (hereinafter referred to as STI) region 201, a drain contact region 202D, a source contact region 202S, a drain region 203D, a source region 203S, an oxidation region The first insulating layer 204A using silicon, the charge storage layer 204B using silicon nitride, the second insulating layer 204C using silicon oxide, the gate insulating layer 204 that combines them, the depletion suppression region 205, and polysilicon are used. Gate electrode 206, sidewall 207, and channel region 208.

  As the substrate 200, for example, a single crystal silicon substrate is preferably used. In addition, it is preferable that an impurity for forming a P-type is added so that an undepleted region can be left between the drain contact region 202D and the source contact region 202S. The substrate 200 functions as a support for the elements described above.

  The STI region 201 has a function of electrically separating adjacent elements (element isolation). By performing element isolation using the STI region 201, the element isolation region can be made narrower than in the case where a LOCOS region or a semi-recessed LOCOS region is used. Therefore, element isolation suitable for high integration can be performed.

  The drain contact region 202D and the source contact region 202S are provided in order to suppress an increase in electrical resistance caused by shallowing a junction position between a drain region 203D and a source region 203S described later. The drain contact region 202 </ b> D and the source contact region 202 </ b> S are formed in regions that do not contact the gate electrode 206 in plan view on the substrate 200. In the present embodiment, the drain contact region 202D and the source contact region 202S have a deeper junction position than the drain region 203D and the source region 203S. In this case, it is possible to enlarge the region where current flows in the depth direction. The electrical resistance is reduced by widening the current flowing region, and the drain contact region 202D and the source contact region 202S are arranged in parallel with the drain region 203D and the source region 203S, so that the drain region 203D and the source region 203S are arranged. Therefore, it is possible to supply a potential with a small voltage drop.

  The gate insulating layer 204 includes a first insulating layer 204A using silicon oxide, a charge storage layer 204B using silicon nitride, and a second insulating layer 204C using silicon oxide. The first insulating layer 204A has a function of suppressing the outflow of charges from the charge storage layer 204B to a region formed of a semiconductor and a Young's modulus lower than that of silicon nitride. Therefore, the charge storage layer 204B using silicon nitride and the substrate 200 are used. It has a function to relieve stress generated between the two. Since the charge storage layer 204B has an appropriate intermediate level, the injected charge can be efficiently stored and released. The second insulating layer 204C has a function of preventing the charge of the charge storage layer 204B from escaping upward.

  The depletion suppression region 205 is arranged to prevent punch-through between the drain contact region 202D and the source contact region 202S and punch-through between the drain region 203D and the source region 203S. The gate electrode 206 has a function of inducing and removing carriers in the channel region 208 located on the surface of the substrate 200 based on the potential applied to the gate electrode 206. The role played by the sidewall 207 will be described later.

  In the present embodiment, the drain contact region 202D and the source contact region 202S and the drain region 203D and the source region 203S of the nonvolatile memory element MC10 are illustrated as having a symmetric configuration, but this is a symmetric configuration. For example, the source region 203S may have a gentle impurity distribution. In this case, carriers are hardly injected into the gate insulating layer 204 from the source region 203S side, unnecessary charges can be prevented from entering the gate insulating layer 204, and reliability can be improved. It becomes.

  Next, each component will be described. In the STI region 201, a groove is formed in the substrate 200 at a depth of, for example, about 300 nm, silicon oxide is filled into the groove using a chemical vapor deposition (CVD) method, and then planarized by a chemical mechanical polishing (CMP) method. It is formed by doing.

The junction depth between the drain region 203 </ b> D and the source region 203 </ b> S is preferably 10 nm or more and 500 nm or less in a region overlapping with the end of the gate electrode 206 in plan view in the substrate 200. By providing a junction depth of 10 nm or more, an increase in electrical resistance of the source region 203S and the drain region 203D can be suppressed, and reading can be performed at a high speed. In addition, by setting the junction depth to 500 nm or less, punch-through between the source region 203S and the drain region 203D can be suppressed. The impurity concentration is preferably in the range of 7 × 10 ²⁰ cm ⁻³ or more and about 1 × 10 ²² cm ⁻³ . As a manufacturing condition for satisfying this condition, for example, a condition for performing ion implantation with the gate electrode 206 as a mask and a dose amount of 2 × 10 ¹⁵ cm ⁻² and an acceleration energy of about 5 to 10 KeV is selected. Can do. The depletion suppression region 205 can also be formed by performing ion implantation using boron, decaborane, boron fluoride, or the like while tilting about 10 ° to 30 ° using the gate electrode 206 as a mask.

By including an impurity generating N-type conductivity of 7 × 10 ²⁰ cm ⁻³ or more, a strong drain electric field can be generated at the end of the gate electrode 206. For this reason, band-to-band tunneling hot holes (BTTBTHH) are generated even when a small potential difference is used. Specifically, by grounding the source region 203S and the gate electrode 206 and applying a potential of about 5 [V] only to the drain region 203D, BTBTHH is generated, and the charge stored in the charge storage layer is offset, It can be erased. In addition, by controlling to 1 × 10 ²² cm ⁻³ or less, the properties of the semiconductor can be maintained. In addition, with such a shallow junction, channel hot carriers are efficiently generated at the end of the drain region 203D on the gate electrode 206 side, and charge injection into the charge storage layer 204B is efficiently performed. Is possible.

  The sidewall 207 is formed by forming a silicon oxide layer using a CVD method and performing anisotropic etching, and functions as a spacer formed in a self-aligned manner on the side surface of the gate electrode 206. The drain contact region 202D and the source contact region 202S are formed by ion implantation using the gate electrode 206 and the sidewall 207 as a mask. Therefore, the drain contact region 202D and the source contact region 202S can be formed so as to be located in a region not in contact with the gate electrode 206 in a plan view of the substrate 200. In addition, a depletion suppression region 205 is sandwiched between the drain contact region 202D and the source contact region 202S, and a region having a reverse conductivity type that is not depleted is formed. Therefore, even if the drain contact region 202D and the source contact region 202S are formed deeper than the junction depth of the drain region 203D and the source region 203S, the junction depth is shallow on the gate electrode 206 end side of the drain region 203D. BTBTHH can be generated efficiently and an erasing operation can be performed with a low voltage. Furthermore, it is possible to suppress the occurrence of a short channel effect that generates a leakage current.

  Here, the thickness of the gate insulating layer 204 is preferably 10 nm or more and 16 nm or less. If the gate insulating layer 204 has a thickness of 10 nm or more, it can withstand a potential difference of, for example, about 7 [V] applied during writing. If the thickness is 16 nm or less, it is possible to suppress an increase in leakage current between the drain region 203D and the source region 203S due to the short channel effect. The thickness of the first insulating layer 204A is preferably 2 nm or more and 5 nm or less. By securing the layer thickness of 2 nm or more, the charge storage layer 204B is transferred to the substrate 200 (channel region 208). It is possible to suppress the outflow of electric charges. By using a layer thickness of 5 nm or less, the current control efficiency of the channel region 208 can be increased by the charges accumulated in the charge accumulation layer 204B, and read errors can be prevented.

  In the present embodiment, the structure of the N-type nonvolatile memory element has been described. However, this structure can be easily applied to a P-type nonvolatile memory element. In this case, boron can be used for a region using arsenic as an impurity, and arsenic or phosphorus can be used for a region using boron. In this case, considering the difference in atomic weight, when boron is used, the acceleration energy is increased 11/75 times (mass ratio) when ion implantation is performed, and conversely, 75/11 times when arsenic is used. This can be done. When decaborane, boron fluoride or the like is used, it can be dealt with by using acceleration energy corresponding to these molecular weights. Since the thermal diffusion coefficient of boron is larger than that of arsenic, it is also preferable to adjust the acceleration energy of ion implantation so as to correct this thermal diffusion coefficient difference depending on the annealing conditions performed after ion implantation.

(Modification: Second Embodiment)
In the second embodiment, the example in which silicon oxide is used for the second insulating layer 204C as shown in FIG. 2 has been described, but silicon nitride may be used for this. In this case, it is possible to form a layer that serves as both the charge storage layer and the second insulating layer, and it is possible to reduce the number of components of the nonvolatile memory device and reduce variations and the like. In addition, it is possible to provide a non-volatile memory device that can shorten the manufacturing process and reduce the cost.

  In the second embodiment, the case where the substrate itself is used as the semiconductor layer has been described. However, this is not a case where the substrate itself is used as the semiconductor layer, but a single crystal as a semiconductor layer covering at least a part of the insulating layer. When an SOI (Silicon On Insulator) substrate having a silicon layer is used, element isolation can be performed without forming the STI region described above. FIG. 3 is a cross-sectional view of the structure showing the nonvolatile memory element MC10_SOI when an SOI substrate is used. The element isolation is realized by separating the semiconductor layer 300 into an island shape.

  A semiconductor layer 300 using a single crystal silicon layer is provided over a substrate 301 provided with a silicon oxide layer 301B over the silicon layer 301A. The drain region 203D, the source region 203S, the drain contact region 202D, and the source contact region 202S are formed with a depth equal to or less than the thickness of the semiconductor layer 300. In this case, since there is no conductor or semiconductor that forms a capacitance in the depth direction with the drain contact region 202D and the source contact region 202S, it becomes possible to reduce the parasitic capacitance, reduce power consumption, and increase the speed. Operation is possible. The other configuration is in accordance with the second embodiment.

  The semiconductor layer is not limited to a single crystal silicon layer, and a polycrystalline silicon layer can also be used. FIG. 4 is a cross-sectional view when the nonvolatile memory element MC10_POLY is formed using the semiconductor layer 400 using the polycrystalline silicon layer disposed on the glass substrate 401. The mobility of the polycrystalline silicon layer is slightly lower than the mobility of the single crystal silicon layer, but it is possible to generate hot carriers sufficiently. In this case, the upper limit of the thickness is the layer thickness at which laser annealing for modifying the amorphous silicon layer into the polycrystalline silicon layer is possible, and for example, a value of about 100 nm is the upper limit. Therefore, as in the case of using the SOI substrate described above, the drain contact region 202D, the source contact region 202S, the drain region 203D, and the source region 203S are formed with a depth equal to or less than the thickness of the semiconductor layer 400.

  Even in this case, since there is no conductor or semiconductor that forms capacitance in the depth direction with the drain contact region 202D and the source contact region 202S, parasitic capacitance can be reduced, power consumption can be reduced, and higher speed can be achieved. It becomes possible to operate with. In addition, since the semiconductor layer 400 using a polycrystalline silicon layer can use a larger area substrate than a single crystal silicon substrate, a large number of nonvolatile memory devices can be formed from a single substrate. Thus, a nonvolatile memory device that is advantageous in terms of cost can be obtained.

  MC00 ... nonvolatile memory element, MC01 ... nonvolatile memory element, MC10 ... nonvolatile memory element, MC11 ... nonvolatile memory element, MC10_SOI ... nonvolatile memory element, MC10_POLY ... nonvolatile memory element, SL0 ... source line, SL1 ... source Line, WL0 ... Word line, WL1 ... Word line, BL0 ... Bit line, BL1 ... Bit line, G00 ... Gate as gate electrode, G01 ... Gate as gate electrode, G10 ... Gate as gate electrode, G11 ... Gate electrode S00 ... source as source region, S01 ... source as source region, S10 ... source as source region, S11 ... source as source region, D00 ... drain as drain region, D01 ... as drain region drain, DESCRIPTION OF SYMBOLS 10 ... Drain as drain region, D11 ... Drain as drain region, 100 ... Nonvolatile memory device, 200 ... Substrate, 201 ... STI region, 202D ... Drain contact region, 202S ... Source contact region, 203D ... Drain region, 203S ... Source region, 204 ... Gate insulating layer, 204A ... First insulating layer, 204B ... Charge storage layer, 204C ... Second insulating layer, 205 ... Depletion suppression region, 206 ... Gate electrode, 207 ... Side wall, 208 ... Channel region 300 ... Semiconductor layer, 301 ... Substrate, 301A ... Silicon layer, 301B ... Silicon oxide layer, 400 ... Semiconductor layer, 401 ... Glass substrate.

Claims (10)

A semiconductor layer;
A gate including a first insulating layer provided on the semiconductor layer, a charge storage layer provided on the first insulating layer, and a second insulating layer provided on the charge storage layer An insulating layer;
A gate electrode disposed on the gate insulating layer,
The semiconductor layer includes a source region including an impurity that generates an N-type conductivity type;
A drain region containing impurities that generate N-type conductivity,
A channel region disposed under the gate electrode via the gate insulating layer, and sandwiched between the source region and the drain region in a plan view of the semiconductor layer;
The drain region is an N type at a concentration of 7 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less at a position where the gate electrode and the drain region overlap in a plan view of the semiconductor layer. A non-volatile memory device comprising a non-volatile memory element containing an impurity that generates a conductivity type. A semiconductor layer;
A gate including a first insulating layer provided on the semiconductor layer, a charge storage layer provided on the first insulating layer, and a second insulating layer provided on the charge storage layer An insulating layer;
A gate electrode disposed on the gate insulating layer,
The semiconductor layer includes a source region including an impurity that generates a P-type conductivity type;
A drain region containing an impurity that generates a P-type conductivity type;
A channel region sandwiched between the source region and the drain region in a plan view of the semiconductor layer on the surface of the semiconductor layer;
The gate insulating layer and the gate electrode are disposed on the channel region,
The drain region has a P-type conductivity at a concentration of 7 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less at a position overlapping the gate electrode and the drain region in plan view of the semiconductor layer. A non-volatile memory device comprising a non-volatile memory element containing an impurity that generates oxygen.   3. The nonvolatile memory device according to claim 1, wherein a charge is injected into the charge storage layer using channel hot carriers as a method of writing to the nonvolatile memory element. .   4. The nonvolatile memory device according to claim 1, wherein the gate insulating layer has a thickness of 10 nm or more and 16 nm or less. 5. The non-volatile memory device according to claim 1,
The non-volatile memory device, wherein the source region and the drain region have a junction depth of 10 nm or more and 500 nm or less at a gate electrode end in a plan view of the semiconductor layer. 6. The nonvolatile memory device according to claim 1, wherein the source is located in a region of the source region that is not in contact with the gate electrode in a plan view of the semiconductor layer. A source contact region that exhibits the same conductivity type as the region and reduces the sheet resistance of the source region;
A drain contact region located in a region not in contact with the gate electrode in plan view of the semiconductor layer in the drain region and having the same conductivity type as the drain region, and reducing a sheet resistance of the drain region; Including,
A non-volatile memory device, wherein a non-depleted region having a reverse conductivity type is sandwiched between the source contact region and the drain contact region. The non-volatile memory device according to claim 1,
The concentration of the first impurity constituting the opposite conductivity type to the drain region is higher than the concentration of the first impurity contained in the channel region, and higher than the concentration of the second impurity constituting the same conductivity type as the drain region. With a low depletion suppression region,
The non-volatile memory device is characterized in that the depletion suppression region covers the drain region inside the gate electrode in a plan view of the semiconductor layer.   The nonvolatile memory device according to claim 1, wherein the first insulating layer and the second insulating layer are made of silicon oxide, and the charge storage layer is made of silicon nitride. A non-volatile memory device.   8. The nonvolatile memory device according to claim 1, wherein silicon nitride is used for the second insulating layer.   10. The nonvolatile memory device according to claim 1, wherein the silicon oxide layer serving as the first insulating layer has a thickness of 2 nm or more and 5 nm or less. Memory device.

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