JP2010182713A - Nonvolatile semiconductor memory device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that has a small select gate threshold shift, and to provide a method of manufacturing the same. <P>SOLUTION: A tunnel insulating film and a charge film are formed on a silicon substrate 11, and two or more elements separating and insulating films 12 are formed to mark off the upper layer of the silicon substrate 11 as semiconductor parts 13 that extend in the direction of a memory string. Next, the charge film and tunnel insulating film are removed from the select gate region Rsg, and the upper surface 12a of the elements separating and insulating films 12 and the upper surface 13a of the semiconductor parts 13 are made into a continuous flat surface or the upper surface 12a is located higher than the upper surface 13a. After that, the CVD method is used to form a deposition film 18 in the memory cell region Rmc and select gate region Rsg, remove the deposition film 18 from the memory cell region Rmc, form a block insulating film 16 on the charge film and deposition film 18, and form a word electrode WL and a select gate electrode SG on the block insulating film 16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  A NAND flash memory has been developed as a nonvolatile semiconductor memory device. In a NAND flash memory, an upper layer portion of a silicon substrate is partitioned into active areas extending in one direction by an element isolation insulating film, and a plurality of memory cells are formed along each active area. Select gate transistors are formed on both sides of a memory string made up of cells. Each memory cell is provided with a tunnel insulating film through which a tunnel current can be passed and a charge film having a charge storage capability (see, for example, Patent Document 1).

  Conventionally, in such a NAND flash memory, the gate insulating film of the select gate transistor is configured using the same film as the tunnel insulating film and the charge film formed in the memory cell. However, if a charge film is included in the gate insulating film of the select gate transistor, charges are accumulated in the charge film of the select gate transistor along with the writing / reading operation of the flash memory. The threshold fluctuates.

  Therefore, a technique for forming a dedicated insulating film not including a charge film as a gate insulating film of the select gate transistor has been proposed. That is, after forming a tunnel insulating film and a charge film on the entire surface of the silicon substrate, the tunnel insulating film and the charge film are removed from the select gate region, and a part of the active area in the select gate region is oxidized again by a thermal oxidation method. Then, a gate insulating film is formed. Thereafter, a block insulating film is formed so as to cover the charge film remaining in the memory cell region and the thermal oxide film formed in the select gate region, and an electrode is formed thereon.

  However, in this technique, when the upper layer portion of the active area made of silicon is thermally oxidized, the upper surface of the thermal oxide film protrudes from the upper surface of the surrounding element isolation insulating film due to volume expansion accompanying the oxidation. As a result, in the select gate region, the lower surface of the electrode is curved to reflect the shape of the thermal oxide film, and a convex shape is formed near the boundary between the region directly above the active area and the region immediately above the element isolation insulating film on the lower surface of the electrode. Are formed. As a result, during the operation of the select gate transistor, the electric field is concentrated on this corner, and charges are accumulated in the charge traps existing at the interface between the thermal oxide film and the block insulating film, and the threshold of the select gate Will fluctuate.

  In addition to this problem, in the memory cell region, oxidized species are diffused by the heat of thermal oxidation, and bird's beaks are formed in the tunnel insulating film. As a result, the effective film thickness of the tunnel insulating film of the memory cell is increased. As a result, there is a problem that the writing / erasing speed of the memory cell is lowered and the resistance against repeated writing / erasing stress (Endurance) is deteriorated.

JP 2005-116551 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device with a small change in threshold value of a select gate and a method for manufacturing the same.

  According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device in which a memory cell region and a select gate region are set, the semiconductor substrate being embedded in an upper layer portion of the semiconductor substrate, and the select from the memory cell region. A plurality of element isolation insulating films extending in a first direction toward the gate region and partitioning the upper layer portion into semiconductor portions extending in the first direction; and a tunnel insulating film provided on the semiconductor portion in the memory cell region; And both the charge film provided on the tunnel insulating film and the region directly above the semiconductor portion and the region directly above the element isolation film in the select gate region extending in a second direction intersecting the first direction. An insulating deposited film continuously provided on the memory cell region, and on the charge film and the element isolation insulating film in the memory cell region along the second direction. And a block insulating film provided on the deposited film in the select gate region, and an electrode provided on the block insulating film, and a lower surface of the electrode in the select gate region is A non-volatile semiconductor memory device is provided, which is flat or has a shape in which a region directly above the element isolation insulating film is located above a region directly above the semiconductor portion.

  According to another aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device in which a memory cell region and a select gate region are set, wherein both the memory cell region and the select gate region are formed on a semiconductor substrate. Forming a tunnel insulating film; forming a charge film on the tunnel insulating film; forming a plurality of element isolation insulating films on an upper layer portion of the charge film, the tunnel insulating film, and the semiconductor substrate; Partitioning the charge film and the tunnel insulating film into a portion extending in a first direction from the memory cell region toward the select gate region, and partitioning an upper layer portion of the semiconductor substrate into a semiconductor portion extending in the first direction. And removing the charge film and the tunnel insulating film from the select gate region and the element isolation insulation And the upper surface of the element isolation insulating film and the upper surface of the semiconductor portion are made to be a continuous flat surface, or the upper surface of the semiconductor portion is positioned below the upper surface of the element isolation insulating film. A step of depositing an insulating material in the memory cell region and the select gate region; and removing the insulating material from the memory cell region to directly above the semiconductor portion in the select gate region and the element isolation Forming a continuous deposited film immediately above the film; forming a block insulating film on the charge film and on the deposited film; forming an electrode film on the block insulating film; and the electrode By selectively removing the film, the block insulating film, the deposited film, the charge film, and the tunnel insulating film, the film intersects the first direction. A step of processing the pattern extending in the second direction, a method of manufacturing a nonvolatile semiconductor memory device characterized by comprising a are provided that.

  According to the present invention, it is possible to realize a non-volatile semiconductor memory device and a method for manufacturing the non-volatile semiconductor memory device in which the threshold value variation of the select gate is small.

1 is a plan view illustrating a nonvolatile semiconductor memory device according to an embodiment of the invention. It is sectional drawing by the A-A 'line | wire shown in FIG. It is sectional drawing by the B-B 'line shown in FIG. It is sectional drawing by the C-C 'line | wire shown in FIG. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. It is sectional drawing which illustrates the non-volatile semiconductor memory device which concerns on the modification of this embodiment. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this modification. FIGS. 5A to 5C are process cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to a comparative example of this embodiment. FIGS. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this comparative example. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this comparative example. (A)-(c) is process sectional drawing which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on this comparative example.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view illustrating a nonvolatile semiconductor memory device according to this embodiment.
2 is a cross-sectional view taken along line AA ′ shown in FIG.
3 is a cross-sectional view taken along line BB ′ shown in FIG.
4 is a cross-sectional view taken along line CC ′ shown in FIG.
In FIG. 1, for convenience of illustration, some members are selectively shown.

  As shown in FIGS. 1 and 2, in the nonvolatile semiconductor memory device 1 according to this embodiment, a silicon substrate 11 is provided. Further, when viewed from a direction perpendicular to the upper surface of the silicon substrate 11 (hereinafter referred to as a “height direction”), a memory cell region Rmc and a select gate region Rsg are set in the silicon substrate 11. The select gate region Rsg is arranged at a position sandwiching the memory cell region Rmc. Hereinafter, the direction from the memory cell region Rmc to the select gate region Rsg is referred to as “memory string direction”.

  In the upper layer portion of the silicon substrate 11, a plurality of stripe-shaped element isolation insulating films 12 extending in the memory string direction are embedded in parallel and spaced apart from each other. Thus, the element isolation insulating film 12 partitions the upper layer portion of the silicon substrate 11 into a plurality of semiconductor portions 13. The element isolation insulating film 12 is made of, for example, silicon oxide. Each semiconductor portion 13 is a portion that becomes an active area of a memory cell and a select gate transistor, which will be described later, and the shape thereof is a stripe shape extending in the memory string direction, and an impurity that becomes a donor or an acceptor is introduced.

  As shown in FIG. 2, the upper surface 13a of the semiconductor portion 13 has a step D at the boundary between the select gate region Rsg and the memory cell region Rmc, and the position of the upper surface 13a in the select gate region Rsg is the memory cell region Rmc. Is below the position S of the upper surface 13a.

  As shown in FIG. 3, in the memory cell region Rmc, the position of the upper surface 12 a of the element isolation insulating film 12 is higher than the position S of the upper surface 13 a of the semiconductor portion 13. On the other hand, as shown in FIG. 4, in the select gate region Rsg, the position of the upper surface 12 a of the element isolation insulating film 12 is substantially equal to the position of the upper surface 13 a of the semiconductor portion 13. That is, in the select gate region Rsg, the upper surface 12a of the element isolation insulating film 12 and the upper surface 13a of the semiconductor portion 13 constitute a substantially continuous flat surface.

  As shown in FIGS. 2 and 3, a tunnel insulating film 14 is provided on the semiconductor portion 13 in the memory cell region Rmc. The tunnel insulating film 14 is normally an insulating film, but is a film through which a tunnel current flows when a predetermined driving voltage is applied, and is, for example, a silicon oxide film. The film thickness of the tunnel insulating film 14 is, for example, 0.5 to 10 nm (nanometer) in terms of EOT (Equivalent Oxide Thickness).

  The tunnel insulating film 14 is intermittently formed along the memory string direction only in the region directly above the semiconductor portion 13, and is not formed in the region directly above the element isolation insulating film 12. That is, when viewed from the height direction, the tunnel insulating films 14 are arranged in a matrix. Further, the thickness of the tunnel insulating film 14 is uniform.

As the tunnel insulating film 14, instead of a single layer silicon oxide film, an ONO film (Oxide-Nitride-Oxide film) having an equivalent film thickness in terms of EOT, that is, a silicon oxide film, a silicon nitride film, a silicon oxide film May be used, and a two-layer film (hereinafter referred to as (SiN film / SiO ₂ film)) in which a silicon oxide film and a silicon nitride film are stacked in this order from the lower layer side may be used. Alternatively, a three-layer film of (SiO ₂ film / high dielectric constant insulating film / SiO ₂ film) may be used, or a two-layer film of (high dielectric constant insulating film / SiO ₂ film) may be used. . The high dielectric constant insulating film refers to an insulating film having a higher dielectric constant than that of the silicon oxide film. Alternatively, a single layer film or a stacked film having a structure other than the above may be used.

  A charge film 15 is formed immediately above the tunnel insulating film 14. The charge film 15 is a film having charge storage capability. The charge film 15 is made of, for example, silicon nitride and has a thickness of 3 to 50 nm. The upper surface of the charge film 15 is above the upper surface of the element isolation insulating film 12.

The charge film 15 may be an HfAlO film instead of the silicon nitride film. Alternatively, the charge film 15 may be a laminated film including a high dielectric constant insulating film. Examples of the high dielectric constant insulating film include an Al ₂ O ₃ film, MgO film, SrO film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, Y _{There are 2} O ₃ film, ZrSiO film, HSiO film, LaAlO film and the like. In this case, the structure of the laminated film including the high dielectric constant insulating film is, for example, (SiN film / high dielectric constant insulating film / SiN film), (HfAlO film / high dielectric constant insulating film / SiN film), (SiN film / High dielectric constant insulating film / HfAlO film) and (HfAlO film / high dielectric constant insulating film / HfAlO film).

A block insulating film 16 is provided in the memory cell region Rmc. The block insulating film 16 is a film that substantially does not allow charges to pass even when a voltage is applied within the range of the driving voltage of the nonvolatile semiconductor device 1, and is composed of, for example, a high dielectric constant insulating film. For example, the block insulating film 16 is made of alumina (Al ₂ O ₃ ) and has a film thickness of 5 to 30 nm.

  As shown in FIGS. 1 to 3, the block insulating film 16 stripes along a direction (hereinafter referred to as “electrode direction”) orthogonal to the memory string direction among the directions parallel to the upper surface of the silicon substrate 11. It extends in a shape and passes directly above the plurality of charge films 15. On the other hand, the block insulating film 16 is not provided in the region between the charge films 15 in the memory string direction. As described above, since the upper surface of the charge film 15 protrudes from the upper surface of the element isolation insulating film 12, the upper surface of the block film 16 also reflects the protrusion of the charge film 15 in the region immediately above the charge film 15. It protrudes.

As the block insulating film 16, a high dielectric constant insulating film or a laminated film thereof can be used instead of the alumina film. As the high dielectric constant insulating film, for example, MgO film, SrO film, SiN film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, Y ₂ O ₃ film A film, a ZrSiO film, a HfSiO film, a LaAlO film, or the like can be used. The laminated film including these high dielectric constant insulating films includes (Al ₂ O ₃ film / high dielectric constant insulating film), (high dielectric constant insulating film / Al ₂ O ₃ film), (SiO ₂ film / high Dielectric constant insulating film / SiO ₂ film), (SiO ₂ film / high dielectric constant insulating film), (high dielectric constant insulating film / SiO ₂ film), (high dielectric constant insulating film / SiO ₂ film / high dielectric constant insulating film) ) Etc. can be used.

Further, a word electrode WL is provided on the block insulating film 16. The word electrode WL is formed of a conductive material, for example, polysilicon into which a metal or an impurity is introduced. For example, a P ⁺ -type polycrystalline silicon film into which an impurity serving as an acceptor is introduced at a high concentration, a metal silicide film, It is comprised by the laminated film of. The film thickness of the block insulating film 16 is, for example, 10 to 500 nm.

  Similarly to the block insulating film 16, the word electrode WL has a stripe shape extending in the electrode direction. Concavities and convexities corresponding to the upper surface of the block insulating film 16 are formed on the lower surface of the word electrode WL, and the region directly above the charge film 15 on the lower surface of the word electrode WL is higher than the region directly above the element isolation insulating film 12. It is in.

In the word electrode WL, a single layer P ⁺ -type polycrystalline silicon film or an impurity serving as a donor is introduced at a high concentration instead of the above-described laminated film of the P ⁺ -type polycrystalline silicon film and the metal silicide film. A single layer N ⁺ type polycrystalline silicon film may be used. Alternatively, it may be composed of a (metal film / polycrystalline silicon) laminated film, a (metal film / metal nitride film) laminated film, or the like. In these cases, for example, CoSi, NiSi, WSi, MoSi, TiSi or the like can be used for the metal silicide, tungsten (W) or the like can be used for the metal, and WN, TaN, TiN or the like can be used for the metal nitride. TaC or the like can be used as the metal carbide.

  On the other hand, as shown in FIGS. 2 and 4, the tunnel insulating film 14 and the charge film 15 are not provided in the select gate region Rsg, and the deposited film 18 is provided on the silicon substrate 11. The deposited film 18 extends in a stripe shape along the electrode direction. The deposited film 18 is an insulating film formed by a deposition technique, for example, a silicon oxide film deposited by a CVD (Chemical Vapor Deposition) method, for example, an ALD (Atomic Layer Deposition) atom. It is a film formed by a layer deposition method or an HTO film (high temperature oxide film) formed by a thermal CVD method.

Since the deposited film 18 is formed by a deposition technique such as a CVD method, the composition is different from that of the thermal oxide film formed by the thermal oxidation method, and hydrogen atoms (H) of 1 × 10 ²⁰ cm ⁻³ or more, 1 × 10 ¹⁹ cm ^-3 or more nitrogen atoms (N), and, among the 1 × ¹⁰ 19 ^{cm -3} or more chlorine atoms (Cl), contains at least one. The content of these elements is analyzed, for example, by analyzing the deposited film 18 using TEM (transmission electron microscopy) -EDX (energy dispersive X-ray spectroscopy). Can be confirmed. Further, since the deposited film 18 is formed by a deposition technique, the thickness is uniform throughout the deposited film 18.

  A block insulating film 16 is formed on the deposited film 18. The block insulating film 16 is also formed in a stripe shape along the electrode direction, and its thickness is uniform throughout. A select gate electrode SG is formed on the block insulating film 16. The select gate electrodes SG are also formed in stripes along the electrode direction, and are formed to the same thickness by the same material as the word electrodes WL.

  As described above, in the select gate region Rsg, the upper surface 12a of the element isolation insulating film 12 is at the same height as the upper surface 13a of the semiconductor portion 13, and constitutes a continuous flat surface. A deposited film 18 is deposited on the flat surface with a uniform thickness, and a block insulating film 16 is formed on the flat surface with a uniform thickness. For this reason, the lower surface SGa of the select gate electrode SG is substantially flat.

  In the nonvolatile semiconductor memory device 1, an interlayer insulating film (not shown) is provided so as to bury the word electrode WL and the select gate electrode SG, and a contact is formed in the interlayer insulating film. A wiring (not shown) or the like is provided on the interlayer insulating film.

  In the nonvolatile semiconductor memory device 1 according to the present embodiment, as viewed from the height direction, the tunnel insulating film 14, at each intersection between the semiconductor portion 13 extending in the memory string direction and the word electrode WL extending in the electrode direction, A laminated film made up of a charge film 15 and a block insulating film 16 is interposed, the semiconductor portion 13 functions as an active area, and the word electrode WL functions as a gate electrode, so that MANOS (Metal-Alumina-Nitride-Oxide- Silicon) type memory cells are formed. A plurality of memory cells sharing the semiconductor portion 13 are connected in series to form a memory string.

  On the other hand, as viewed from the height direction, the deposited film 18 and the block insulating film 16 are interposed at the intersection between the semiconductor portion 13 and the select gate electrode SG. The semiconductor portion 13 functions as a channel, and the deposited film 18 The stacked film composed of the block insulating film 16 functions as a gate insulating film, and the select gate electrode SG functions as a gate electrode, thereby forming a select gate transistor. Thus, select gate transistors are connected to both ends of the memory string.

Next, a method for manufacturing the nonvolatile semiconductor memory device according to this embodiment will be described.
5 to 11 are process cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to this embodiment. FIG. 5A corresponds to a cross-sectional view taken along line AA ′ shown in FIG. (B) in each figure corresponds to a cross-sectional view taken along line BB ′ shown in FIG. 1, and (c) in each figure corresponds to a cross-sectional view taken along line CC ′ in FIG.

  First, as shown in FIGS. 5A to 5C, a silicon substrate 11 is prepared. A memory cell region Rmc is set in the silicon substrate 11, and a select gate region Rsg is set at a position sandwiching the memory cell region Rmc. At this time, the position in the height direction of the upper surface of the silicon substrate 11 is defined as a position S.

  Then, the tunnel insulating film 14 is formed on the silicon substrate 11 in both the memory cell region Rmc and the select gate region Rsg. The tunnel insulating film 14 is formed by thermal oxidation.

  Next, the charge film 15 is formed on the entire surface of the tunnel insulating film 14. The charge film 15 is formed, for example, by depositing silicon nitride. Thereafter, a pad oxide film 51 made of silicon oxide is formed on the charge film 15, and then a stopper film 52 made of silicon nitride is formed. The charge film 15, the pad oxide film 51, and the stopper film 52 are formed in both the memory cell region Rmc and the select gate region Rsg.

  Next, as shown in FIGS. 6A to 6C, a resist film 53 is formed on the stopper film 52 and patterned by lithography to form the element isolation insulating film 12 (see FIGS. 1 to 4). Open the area to be planned. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the patterned resist film 53 as a mask, and the charge film 15 and the tunnel insulating film 14 are selectively removed, and silicon The upper layer portion of the substrate 11 is selectively removed to form a groove 54 extending in the memory string direction. Thereafter, the resist film 53 is removed. Thereby, the charge film 15, the tunnel insulating film 14, and the upper layer portion of the silicon substrate 11 are divided along the electrode direction by the element isolation insulating film 12.

  Next, as shown in FIGS. 7A to 7C, the inner surface of the groove 54 is washed to remove deposits (deposits) during processing. Then, the element isolation insulating film 12 is formed by embedding an insulating material such as silicon oxide in the trench 54. As a result, the upper layer portion of the silicon substrate 11 is partitioned by the element isolation insulating film 12 into a plurality of semiconductor portions 13 extending in the memory string direction. The material for forming the element isolation insulating film 12 is not limited to silicon oxide. Next, CMP (Chemical Mechanical Polishing) is performed using the stopper film 52 as a stopper, the insulating material on the stopper film 52 is removed, and the upper surface is planarized.

  Next, as shown in FIGS. 8A to 8C, wet etching with hot phosphoric acid is performed to peel off the stopper film 52 (see FIG. 7). Thereafter, the element isolation insulating film 12 is etched from the upper surface side, and the upper surface of the element isolation insulating film 12 is dropped to a position below the upper surface of the pad oxide film 51 and above the upper surface of the charge film 15. This etching may be wet etching or dry etching.

  Next, as shown in FIGS. 9A to 9C, a resist film 55 is formed on the entire surface. Then, the resist film 55 is removed from the select gate region Rsg by lithography to remain in the memory cell region Rmc. As a result, the element isolation insulating film 12 and the pad oxide film 51 are exposed in the select gate region Rsg.

  Next, etching is performed using the resist film 55 as a mask. This etching may also be wet etching or dry etching. Thereby, in the select gate region Rsg, the upper layer portion of the element isolation insulating film 12 is removed, the pad oxide film 51, the charge film 15, and the tunnel insulating film 14 are removed, and further, the upper layer portion of the semiconductor portion 13 is removed. . At this time, in the height direction, the position of the upper surface 12a of the element isolation insulating film 12 and the position of the upper surface 13a of the semiconductor portion 13 are made substantially equal to form a continuous flat surface. The positions of the upper surfaces 12a and 13a in the select gate region Rsg are set lower than the position S of the upper surface 13a of the semiconductor portion 13 in the memory cell region Rmc. Thereby, a step D is formed in the boundary region between the memory cell region Rmc and the select gate region Rsg on the upper surface 13a. Thereafter, the resist film 55 is peeled off.

Next, as shown in FIGS. 10A to 10C, silicon oxide is deposited by a deposition technique such as thermal CVD or ALD to form a deposited film 18 in both the memory cell region Rmc and the select gate electrode Rsg. To do. When a silicon oxide film is formed by a deposition technique such as CVD, silicon hydride, silicon chloride, or a silicon-containing organic gas is used as the silicon source gas, and oxygen gas, ozone, Steam, nitrous oxide, or the like is used. For this reason, the deposited film 18 contains hydrogen atoms of 1 × 10 ²⁰ cm ⁻³ or more, or chlorine atoms or nitrogen atoms of 1 × 10 ¹⁹ cm ⁻³ or more. Thereafter, a resist film 56 is formed on the entire surface, selectively removed by lithography, and opened in the memory cell region Rmc and the boundary region between the memory cell region Rmc and the select gate region Rsg. Here, the resist film 56 only needs to remain in the region where the gate insulating film of the select gate transistor is to be formed.

Next, as shown in FIGS. 11A to 11C, using the resist film 56 (see FIG. 10) as a mask, wet etching using, for example, BHF (buffered hydrofluoric acid) is performed, and the memory The deposited film 18 is removed from the cell region Rmc and the boundary region. Thereafter, the resist film 56 is removed. Next, for example, alumina is deposited on the entire surface to form the block insulating film 16. As a result, the block insulating film 16 is continuously formed on the upper surface of the charge film 15 and the upper surface 12a of the element isolation insulating film 12 in the memory cell region Rmc, and the deposited film 18 is formed in the select gate region Rsg. It will be formed on the top surface. Next, an electrode film 57 is formed by depositing a conductive material such as P ⁺ -type polycrystalline silicon on the entire surface.

  Next, as shown in FIGS. 1 to 4, a resist film (not shown) is formed on the entire surface and patterned by lithography to remain in a region where the word electrode WL and the select gate electrode SG are to be formed. Let Etching is performed using the resist film as a mask, and the electrode film 57, the block insulating film 16, the deposited film 18, the charge film 15, and the tunnel insulating film 14 are selectively removed, so that these films extend in the electrode direction. Process into a pattern. Thus, the electrode film 57 is divided along the memory string direction, and the word electrode WL and the select gate electrode SG extending in the electrode direction are formed.

  At this time, in the memory cell region Rmc, the block insulating film 16, the charge film 15, and the tunnel insulating film 14 remain only in the region immediately below the word electrode WL, thereby forming a memory cell. On the other hand, in the select gate region Rsg, the block gate insulating film 16 and the deposited film 18 remain only in the region immediately below the select gate electrode SG to form a select gate transistor. In the select gate region Rsg, the upper surface 13a of the semiconductor portion 13 and the upper surface 12a of the element isolation insulating film 12 form a continuous flat surface, and the deposited film 18 and the block insulating film 16 have a uniform thickness. Since it is deposited, the lower surface SGa of the select gate electrode SG becomes flat.

  Next, an interlayer insulating film (not shown) is formed so as to bury the word electrode WL and the select gate electrode SG, a contact is formed in the interlayer insulating film, and a wiring (not shown) is formed on the interlayer insulating film. Etc. Thereby, the nonvolatile semiconductor memory device 1 according to this embodiment is manufactured.

Next, the effect of this embodiment is demonstrated.
As shown in FIGS. 2 and 4, in the nonvolatile semiconductor memory device 1 according to this embodiment, the charge film 15 is not provided in the select gate region Rsg. Therefore, no charge is accumulated in the charge film 15 with the operation of the select gate transistor, and the threshold value of the select gate transistor does not fluctuate. As a result, malfunction of the select gate transistor can be prevented.

  Further, as described above, in the select gate region Rsg, the upper surface 13a of the semiconductor portion 13 and the upper surface 12a of the element isolation insulating film 12 constitute a continuous flat surface, and the deposited film 18 and the block insulating film 16 are uniform. Since the film is formed with a sufficient thickness, the lower surface SGa of the select gate electrode SG is substantially flat. For this reason, the electric field does not concentrate in the part between the semiconductor portion 13 and the select gate electrode SG, particularly in the vicinity of the boundary with the element isolation insulating film, with the operation of the select gate transistor, and the deposited film 18 and the block insulating film It is possible to suppress the accumulation of electric charges at the trap sites existing at the interface with 16 or the like. As a result, the threshold value of the select gate transistor can be prevented from fluctuating, and malfunction of the select gate transistor can be prevented.

  Furthermore, in this embodiment, the deposited film 18 and the block insulating film 16 are formed by a deposition technique such as a CVD method. For this reason, it is not necessary to perform thermal oxidation after forming the tunnel insulating film 14. Accordingly, no bird's beak is formed in the tunnel insulating film 14 in the thermal oxidation process. The “bird's beak” is an oxide film having a shape similar to a bird's beak. For example, oxygen enters the interface between the silicon film and the silicon oxide film, and the silicon film is oxidized from the edge side. Formed by volume expansion. In this embodiment, since no bird's beak is formed, the thickness of the tunnel insulating film 14 does not become non-uniform, and the characteristics of the memory cell do not fluctuate.

Next, a modification of this embodiment will be described.
FIG. 12 is a cross-sectional view illustrating a nonvolatile semiconductor memory device according to this variation.
FIG. 12 shows a cross section corresponding to FIG.

  As shown in FIG. 12, in the nonvolatile semiconductor memory device 2 according to this modification, the upper surface 12a of the element isolation insulating film 12 is positioned above the upper surface 13a of the semiconductor portion 13 in the select gate region Rsg. . Thereby, the upper surface 12a of the element isolation insulating film 12 and the upper surface 13a of the semiconductor portion 13 constitute a continuous uneven surface in which the upper surface 12a protrudes upward and the upper surface 13a is recessed downward. The distance (height difference) between the upper surface 12 a and the upper surface 13 a in the height direction is equal to or less than the film thickness of the charge film 15.

  On the uneven surface, the deposited film 18 and the block insulating film 16 are formed with a substantially uniform film thickness, and the select gate electrode SG is provided thereon. Therefore, the lower surface SGa of the select gate electrode SG is formed with unevenness reflecting the unevenness of the upper surfaces 12a and 13a. That is, the lower surface SGa of the select gate electrode SG is an uneven surface in which the region directly above the element isolation insulating film 12 is positioned relatively upward and the region directly above the semiconductor portion 13 is positioned relatively below. The configuration other than the above in the present modification is the same as that of the above-described embodiment.

Next, a method for manufacturing the nonvolatile semiconductor memory device 2 according to this modification will be described.
13A to 13C are process cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to this variation.
FIGS. 13A to 13C correspond to the cross-sectional view taken along the line AA ′, the cross-sectional view taken along the line BB ′, and the cross-sectional view taken along the line CC ′ shown in FIG. 1, respectively.

  First, similarly to the above-described embodiment, the steps shown in FIGS. Next, as shown in FIGS. 13A to 13C, after a resist film 55 is formed on the entire surface, the resist film 55 is removed from the select gate region Rsg by lithography and is left in the memory cell region Rmc. As a result, the element isolation insulating film 12 and the pad oxide film 51 are exposed in the select gate region Rsg.

  Next, etching is performed using the resist film 55 as a mask to remove the upper layer portion of the element isolation insulating film 12 and the pad oxide film 51, the charge film 15 and the tunnel insulating film 14 in the select gate region Rsg. Then, the upper layer portion of the semiconductor portion 13 is removed. At this time, in the height direction, the position of the upper surface 13a of the semiconductor portion 13 is set lower than the position of the upper surface 12a of the element isolation insulating film 12, and an uneven surface is formed in which the upper surface 12a protrudes upward from the upper surface 13a.

  The subsequent steps are the same as those in the above-described embodiment. That is, as shown in FIGS. 10 and 11, silicon oxide or the like is deposited on the entire surface by a CVD method or the like to form a deposited film 18, and the deposited film 18 is removed from regions other than the select gate region Rsg. Thereafter, a block insulating film 16 made of alumina or the like is formed on the entire surface, and an electrode film 57 made of a conductive material is formed. Next, in the memory cell region Rmc, the electrode film 57, the block insulating film 16, the charge film 15 and the tunnel insulating film 14 are patterned to form a pattern of the word electrode WL extending in the electrode direction and a laminated film immediately therebelow. In the select gate electrode Rsg, the electrode film 57, the block insulating film 16 and the deposited film 18 are patterned to form a pattern of the select gate electrode SG extending in the electrode direction and a laminated film immediately below the select gate electrode SG. Thereby, the nonvolatile semiconductor memory device 2 according to this modification is manufactured. The manufacturing method other than the above in this modification is the same as that of the above-described embodiment.

Next, the effect of this modification is demonstrated.
As shown in FIG. 12, in the nonvolatile semiconductor memory device 2 according to this modification, the upper surface 12a of the element isolation insulating film 12 protrudes upward from the upper surface 13a of the semiconductor portion 13 in the select gate region Rsg. The uneven surfaces are formed by the upper surfaces 12a and 13a. Then, the deposited film 18 and the block insulating film 16 are deposited on the concavo-convex surface to a substantially uniform thickness, so that the lower surface SGa of the select gate electrode SG has a region directly above the element isolation insulating film 12 as a semiconductor portion. 13 is an uneven surface located above the region directly above 13. For this reason, corners sharpened toward the semiconductor portion 13 are not formed on the lower surface SGa of the select gate electrode SG, and the electric field can be prevented from being concentrated. The operational effects other than those described above in the present modification are the same as those in the above-described embodiment.

Next, a comparative example of this embodiment will be described.
14 to 17 are process cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to this comparative example. FIG. 14A corresponds to a cross-sectional view taken along line AA ′ shown in FIG. (B) in each figure corresponds to a cross-sectional view taken along line BB ′ shown in FIG. 1, and (c) in each figure corresponds to a cross-sectional view taken along line CC ′ in FIG.

  First, the steps shown in FIGS. 5 to 9 are performed. Thereafter, as shown in FIGS. 14A to 14C, the pad oxide film 51 (see FIG. 9) is removed using BHF or the like. As a result, the element isolation insulating film 12 and the charge film 15 are exposed in the memory cell region Rmc, and the element isolation insulating film 12 and the semiconductor portion 13 are exposed in the select gate region Rsg. That is, the semiconductor portion 13 made of silicon is exposed in the select gate region Rsg.

  In the memory cell region Rmc, the upper surface of the charge film 15 is located above the upper surface 12 a of the element isolation insulating film 12. In the select gate region Rsg, the upper surface 12a of the element isolation insulating film 12 and the upper surface 13a of the semiconductor portion 13 are at the same height and constitute a continuous flat surface, or the upper surface 12a is higher than the upper surface 13a. Also constitutes an uneven surface located below. The positions of these surfaces in the height direction are lower than the position S of the upper surface 13a of the semiconductor portion 13 in the memory cell region Rmc.

  Next, as shown in FIGS. 15A to 15C, thermal oxidation treatment is performed. As a result, the upper layer portion of the semiconductor portion 13 exposed in the select gate region Rsg is thermally oxidized, and a thermal oxide film 61 is formed. At this time, the volume of the thermal oxide film 61 expands as compared with the upper layer portion of the semiconductor portion 13 before oxidation, so that the upper surface 61 a of the thermal oxide film 61 is above the upper surface 12 a of the surrounding element isolation insulating film 12. Protrusively.

  At this time, in the memory cell region Rmc, oxidized species enter the interface between the semiconductor portion 13 and the tunnel insulating film 14 from the surrounding element isolation insulating film 12 side by diffusion, and the upper surface of the semiconductor portion 13 extends from the edge side. By being oxidized, a wedge-shaped bird's beak 62 is formed in the tunnel insulating film 14.

  The subsequent manufacturing method is the same as that of the above-mentioned embodiment. That is, as shown in FIGS. 16A to 16C, the block insulating film 16 is formed on the entire surface, and then the electrode film 57 is formed. 17A to 17C, the electrode film 57 (see FIG. 16), the block insulating film 16, the charge film 15, the tunnel insulating film 14, and the thermal oxide film 61 are arranged along the memory string direction. The memory cell and the select gate transistor are formed. Thereby, the nonvolatile semiconductor memory device 101 according to this comparative example is manufactured.

  As shown in FIG. 17C, in this comparative example, since the thermal oxide film 61 protrudes upward with respect to the surrounding element isolation insulating film 12, the lower surface SGa of the select gate electrode SG is formed of the thermal oxide film 61. Curves reflecting the shape. That is, the region immediately above the element isolation insulating film 12 on the lower surface SGa of the select gate electrode SG is displaced downward compared to the region directly above the semiconductor portion 13. Thereby, the corner | angular part 63 is formed in lower surface SGa. As a result, with the operation of the select gate transistor, the electric field concentrates on the corner 63, and a strong electric field is applied to the trap site existing at the interface between the thermal oxide film 61 and the block insulating film 16 to accumulate charges. . For this reason, the threshold value fluctuates with the operation of the select gate transistor, and the select gate transistor is likely to malfunction.

  Further, along with the thermal oxidation treatment shown in FIGS. 15A to 15C, bird's beaks 62 are formed in the tunnel insulating film 14 in the memory cell region Rmc. As a result, the effective thickness of the tunnel insulating film increases, and the characteristics of the memory cell change. As a result, a malfunction of the memory cell is likely to occur.

  On the other hand, as described above, according to the present embodiment, the gate insulating film of the select gate transistor is formed by the deposition method, so that the gate insulating film is uniformly formed on the semiconductor portion 13 and the element isolation insulating film 12. The lower surface SGa of the select gate electrode SG can be flat or can have a shape in which the region directly above the element isolation insulating film 12 is located above the region directly above the semiconductor portion 13. Thereby, unlike the corner 63 shown in FIG. 17C, the corner toward the semiconductor portion 13 is not formed on the lower surface SGa of the select gate electrode SG. Therefore, the electric field does not concentrate on a specific portion, charge accumulation can be prevented, and variation in the threshold value of the select gate can be suppressed. Further, since thermal oxidation is not performed, bird's beaks are not formed, and the reliability of the memory cell is high.

  The present invention has been described above with reference to the embodiment. However, the present invention is not limited to this embodiment. That is, those in which the person skilled in the art appropriately added, deleted, or changed the design of the above-described embodiment, or those in which a process was added, omitted, or changed in conditions also included the gist of the present invention. As long as it is provided, it falls within the scope of the present invention. For example, in the above-described embodiment and its modification, the example in which the gate insulating film of the select gate transistor is configured by the laminated film of the deposited film 18 and the block insulating film 16 has been shown, but the present invention is not limited to this. For example, the gate insulating film of the select gate transistor may be constituted by only the deposited film 18 or may be constituted by a laminated film of the deposited film 18 and another insulating film other than the block insulating film 16.

DESCRIPTION OF SYMBOLS 1, 2 Nonvolatile semiconductor memory device, 11 Silicon substrate, 12 Element isolation insulating film, 12a upper surface, 13 Semiconductor part, 13a upper surface, 14 Tunnel insulating film, 15 Charge film, 16 Block insulating film, 18 Deposition film, 51 Pad oxidation Film, 52 stopper film, 53 resist film, 54 groove, 55 resist film, 56 resist film, 57 electrode film, 61 thermal oxide film, 62 bird's beak, 63 corner, 101 nonvolatile semiconductor memory device, D step, Rmc memory cell Region, Rsg select gate region, S position, SG select gate electrode, SGa bottom surface, WL word electrode

Claims (5)

A nonvolatile semiconductor memory device in which a memory cell region and a select gate region are set,
A semiconductor substrate;
A plurality of element isolation insulating films embedded in an upper layer portion of the semiconductor substrate, extending in a first direction from the memory cell region toward the select gate region, and partitioning the upper layer portion into a semiconductor portion extending in the first direction;
A tunnel insulating film provided on the semiconductor portion in the memory cell region;
A charge film provided on the tunnel insulating film;
An insulating deposition film extending in a second direction intersecting the first direction and continuously provided in both the region directly above the semiconductor portion and the region immediately above the element isolation film in the select gate region;
A block insulating film provided continuously on the charge film in the memory cell region and on the element isolation insulating film along the second direction, and provided on the deposited film in the select gate region;
An electrode provided on the block insulating film;
With
The nonvolatile semiconductor memory device according to claim 1, wherein the lower surface of the electrode in the select gate region is flat or has a shape in which a region directly above the element isolation insulating film is located above a region directly above the semiconductor portion.   The nonvolatile semiconductor memory device according to claim 1, wherein no bird's beak is formed in the tunnel insulating film. A method for manufacturing a nonvolatile semiconductor memory device in which a memory cell region and a select gate region are set,
Forming a tunnel insulating film on a semiconductor substrate in both the memory cell region and the select gate region;
Forming a charge film on the tunnel insulating film;
A plurality of element isolation insulating films are formed on upper portions of the charge film, the tunnel insulating film, and the semiconductor substrate, and the charge film and the tunnel insulating film are directed from the memory cell region to the select gate region in a first direction. Dividing the upper layer portion of the semiconductor substrate into a semiconductor portion extending in the first direction;
The charge film and the tunnel insulating film are removed from the select gate region, and the upper layer portion of the element isolation insulating film is removed, so that the upper surface of the element isolation insulating film and the upper surface of the semiconductor portion are continuous flat surfaces. Or the step of positioning the upper surface of the semiconductor portion below the upper surface of the element isolation insulating film;
Depositing an insulating material in the memory cell region and the select gate region;
Removing the insulating material from the memory cell region to form a continuous deposited film in a region directly above the semiconductor portion and a region directly above the element isolation film in the select gate region;
Forming a block insulating film on the charge film and the deposited film;
Forming an electrode film on the block insulating film;
Processing into a pattern extending in a second direction intersecting the first direction by selectively removing the electrode film, the block insulating film, the deposited film, the charge film, and the tunnel insulating film; ,
A method for manufacturing a nonvolatile semiconductor memory device, comprising:   4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the step of forming the deposited film includes a step of depositing silicon oxide by chemical vapor deposition.   5. The method of manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein an atomic layer deposition method or a thermal chemical vapor deposition method is used as the chemical vapor deposition method.

Images