JP2010158117A - Inverter apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter apparatus which can reduce the capacity of a capacitor, even if when a switch element on the low side is not driven is long. <P>SOLUTION: The apparatus includes bootstrap capacitors 41-43, which are charged with electricity by the switch operation on the low side and supply switch drive circuits 31-33 on the high side with drive power; voltage detectors OP1-OP3, which detect the voltages of the bootstrap capacitors 41-43; a controller 2, which controls the switch driving circuits 31-36; and a reference value comparator 21 and a PWM frequency controller 22, which are provided in the controller 2 and change PWM frequency into a lower frequency, based on the detected voltages of the bootstrap capacitors 41-43. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention belongs to the technical field of inverter devices.

Conventionally, a bootstrap capacitor is provided on the high side for a switch element that is provided and driven in an inverter device to drive an AC motor, and the bootstrap capacitor is charged when the low side is energized. The drive circuit of the element is driven by this charging voltage (see, for example, Patent Document 1).
JP 2003-348880 A (page 2-5, full view)

  However, conventionally, when the time during which the low-side switch element is not driven becomes long, the drive voltage of the high-side switch element is lowered, so that the capacitor capacity has to be increased.

  The present invention has been made paying attention to the above-mentioned problems, and an object of the present invention is to provide an inverter device capable of reducing the capacitor capacity even when the low-side switch element is not driven for a long time. It is in.

  In order to achieve the above object, the present invention provides a high-side and low-side bridge circuit in an inverter device that performs a PWM switching operation on at least the high side and drives a load by a high-side and low-side bridge configuration. Switch element, switch drive means for driving the switch element, a bootstrap capacitor that is charged by a low-side switch operation and supplies drive power for the high-side switch drive means, and a voltage for detecting the voltage of the bootstrap capacitor Detecting means, control means for controlling the switch driving means, and frequency changing means provided in the control means for changing the PWM frequency to a lower frequency based on the detection voltage of the bootstrap capacitor. Features.

  Therefore, in the present invention, the capacitor capacity can be reduced even when there is a long time when the low-side switch element is not driven.

  Embodiments for realizing the inverter device according to the present invention will be described below as a first embodiment corresponding to the invention according to claim 1, a second embodiment corresponding to the invention according to claims 1 and 2, and a first and second embodiments. , 3 will be described based on the third embodiment corresponding to the invention.

First, the configuration will be described.
FIG. 1 is a diagram illustrating a circuit configuration of the inverter device according to the first embodiment.
The inverter device 1 according to the first embodiment includes a control unit 2, switch drive circuits 31 to 36, switch elements Qu1 to Qw2, diodes Du1 to Dw2, bootstrap capacitors 41 to 43, voltage detectors OP1 to OP3, a capacitor 6, and a diode 71. ˜73, a capacitor 8, a power source 9, and resistors 10˜12, and drives and controls the motor 5.

  The control unit 2 connects the input terminal between the emitters (or drains) of the switching elements Qu2, Qv2, and Qw2 on the low side and the resistors 10 to 12, and detects the current of each phase. Further, the voltages of the bootstrap capacitors 41 to 43 of the high side phases are detected by the inputs from the voltage detectors OP1 to OP3. Based on the current of each phase and the voltage of the bootstrap capacitors 41 to 43, the PWM drive pulse command values to the high side and low side switch drive circuits 31 to 36 are calculated and output. An output terminal of the control unit 2 is connected to the switch drive circuits 31 to 36.

The switch drive circuits 31 to 36 have their input terminals connected to the output from the control unit 2 and their output terminals connected to the bases (or gates) of the switch elements Qu1 to Qw2. Further, the positive terminal and the negative terminal which are power inputs are connected to the upstream and downstream of the bootstrap capacitors 41 to 43 in the high side switch drive circuits 31 to 33, and the capacitor 6 is connected to the low side switch drive circuits 34 to 36. Connect upstream and downstream. Then, according to the PWM drive pulse command value from the control unit 2, the PWM drive pulse or the drive pulse is shaped and output to the switch elements Qu1 to Qw2.
As a specific example of the switch drive circuits 31 to 36, a PWM pulse signal from the control unit 2 or a combination of a shift circuit that performs level shift of the pulse signal and a buffer is given.

The switch elements Qu1 to Qw2 have the collectors (or sources) of the high-side switch elements Qu1, Qv1, and Qw1 connected to the positive terminal of the capacitor 8, and the emitters (or drains) connected to the low-side switch elements Qu2, Qv2, and Qw2, respectively. To the collector (or source) of The emitters (or drains) of the low-side switch elements Qu2, Qv2, Qw2 are connected to the negative terminal of the capacitor 8 via resistors 10-12, respectively. This constitutes a half bridge. Then, between the high side and the low side, each phase of the motor 5 is connected. Each base (or gate) of the switch elements Qu1 to Qw2 has a circuit configuration that is connected to the outputs of the switch drive circuits 31 to 36, respectively. Then, the switch elements Qu1 to Qw2 drive the motor 5 with a PWM drive pulse.
The diodes Du1 to Dw2 are composed of diodes Du1, Dv1, Dw1, Du2, Dv2, and Dw2, each having a cathode connected to a collector (or source) of each switch element Qu1 to Qw2, and an anode connected to an emitter (or drain). . And it functions as a flywheel diode which circulates the current between the collectors (or sources) and emitters (or drains) of the switch elements Qu1 to Qw2.

  The bootstrap capacitors 41 to 43 are provided corresponding to the high-side switch elements Qu1, Qv1, and Qw1, and their plus terminals are connected to the cathodes of the diodes 71 to 73, respectively. The plus terminals are also connected to the plus terminals of the switch drive circuits 31 to 33, respectively. The minus terminal is connected to the emitters (or drains) of the switch elements Qu1, Qv1, Qw1. The minus terminal is also connected to the minus terminals of the switch drive circuits 31-33. The bootstrap capacitors 41 to 43 supply power to the high side switch drive circuits 31 to 33.

  The voltage detectors OP <b> 1 to OP <b> 3 have input terminals connected to the positive and negative terminals of the bootstrap capacitors 41 to 43, and output terminals connected to the control unit 2. Then, the voltage of the bootstrap capacitors 41 to 43 is detected.

The capacitor 6 has a plus terminal connected to the anodes of the diodes 71 to 73 and a minus terminal connected to the minus terminal of the capacitor 8. The plus terminal and the minus terminal are also connected to the plus terminal and the minus terminal of the low-side switch driving circuits 34 to 36. The capacitor 6 supplies power to the low-side switch drive circuits 34 to 36.
The diodes 71 to 73 have cathodes connected to the positive terminals of the bootstrap capacitors 41 to 43 and the positive terminals of the high-side switch drive circuits 31 to 33, and anodes connected to the positive terminal of the capacitor 6 and the low-side switch drive circuits 34 to 36. Connect to the positive terminal. Then, the flow of current is rectified from the capacitor 6 to the positive terminals of the bootstrap capacitors 41 to 43 and the positive terminals of the high-side switch drive circuits 31 to 33.

The capacitor 8 has a positive terminal connected to the positive terminal of the power source 9 and the collectors (or sources) of the high-side switch elements Qu1, Qv1, and Qw1, and a negative terminal connected to the low-side through the negative terminal of the power source 9 and the resistors 10-12. Connect to the emitters (or drains) of the switch elements Qu2, Qv2, Qw2. The capacitor 8 is charged by the power source 9 to supply a voltage between the collector and the emitter (or between the source and the drain) to the switch elements Qu1 to Qw2.
The power source 9 connects the plus terminal to the plus terminal of the capacitor 8 and connects the minus terminal to the minus terminal of the capacitor 8 to supply power for charging the capacitor 8.
In the first embodiment, the motor 5 driven by the inverter device 1 is a three-phase AC brushless motor in which the coils 5u, 5v, and 5w are star-connected.

Next, a part of the PWM frequency control of the control unit 2 included in the inverter device 1 according to the first embodiment will be described.
FIG. 2 is an explanatory diagram illustrating a partial block configuration of the control unit 2 of the inverter device 1 according to the first embodiment. For the sake of explanation, FIG. 2 shows a part of the circuit portion of one phase and the voltage detector OP1, but the processing is performed on the input of each of the three phases.
The control unit 2 includes a reference value comparison unit 21, a PWM frequency control unit 22, and a drive pulse calculation unit 23.

The reference value comparison unit 21 compares a preset reference value with the detection voltages of the bootstrap capacitors 41 to 43 input from the voltage detectors OP1 to OP3, and determines whether or not the detection voltage is lower than the reference value. The determination result is output to the PWM frequency control unit 22. The reference value is set within a range in which the high-side switch drive circuits 31 to 33 using the voltage of the bootstrap capacitors 41 to 43 as a power source can sufficiently drive the switch elements Qu1, Qv1, and Qw1.
When the detected voltage falls below the reference value, the PWM frequency control unit 22 outputs a command to lower the frequency of the PWM pulse. Note that the reference value and the frequency to be lowered are set in advance. When the detected voltage is equal to or higher than the reference value, a command for maintaining a high PWM pulse frequency is output.
The drive pulse calculation unit 23 calculates a drive pulse command value at the drive frequency based on the command from the PWM frequency control unit 22 according to the control of the control unit 2, and outputs it to the switch drive circuits 31 to 36.

The operation will be described.
[PWM frequency change processing]
FIG. 3 is a flowchart showing a flow of a PWM frequency changing process executed by the control unit 2 of the inverter device 1 according to the first embodiment. Each step will be described below.

  In step S1, the reference value comparison unit 21 inputs detection voltages of the bootstrap capacitors 41 to 43 from the voltage detectors OP1 to OP3.

  In step S2, the reference value comparison unit 21 compares the detected voltage with the reference voltage. If the detected voltage is equal to or higher than the reference voltage, the process proceeds to step S3. If the detected voltage is lower than the reference voltage, the process proceeds to step S4.

  In step S3, the PWM frequency control unit 22 maintains a high PWM pulse frequency.

  In step S4, the PWM frequency control unit 22 changes the frequency of the PWM pulse to be low.

  In step S5, the drive pulse calculator 23 calculates and outputs a drive pulse command value at the frequency set in step S3 or step S4.

[Capacitor suppression]
FIG. 4 is a diagram for explaining an energization pattern of the inverter device according to the first embodiment.
In the inverter device 1, as shown in FIG. 4, the high-side switch elements Qu1, Qv1, and Qw1 are pulse-driven, and the low-side switch elements Qu2, Qv2, and Qw2 are pulse-driven.
For example, when the U-phase high side is PWM pulse driven, the W-phase low side is pulse-driven a little later, and the coils 5u and 5w are energized, and then the V-phase high side is pulse-driven. The U-phase low side is pulse driven with a delay, and the coils 5v and 5u are energized. Thus, the motor 5 is driven so as to switch the energization pattern every 120 degrees.

Next, the charging state of the bootstrap capacitors 41 to 43 will be described.
The U phase will be described as an example. In the inverter device of the first embodiment, when the U-phase low-side switch element Qu2 is turned on in the energization pattern as described above, the current path indicated by reference numeral 100 in FIG. Charge the battery. That is, it is a path from the capacitor 6 to the diode 71, the bootstrap capacitor 41, the switch element Qu2, and the resistor 10.
When the low-side switch element Qu2 is turned off, the bootstrap capacitor 41 voltage starts to drop. This is due to the quiescent current of the switch drive circuit 31.

When the high-side switch element Qu1 is turned on by switching the energization pattern and PWM driving is performed, the charge stored in the bootstrap capacitor 41 is consumed. If the amount of charge consumed when the high-side switch element Qu1 is turned on / off is q1, the amount of charge discharged by n-time switching is n × q1. Since n is proportional to the PWM modulation frequency, the amount of charge consumed is also proportional to the PWM modulation frequency. The current consumption at this time is sufficiently larger than the quiescent current. For this reason, it is mostly the current consumption during switching that contributes to the voltage drop of the bootstrap capacitor 41 shown in FIG. Similarly, the voltages of the bootstrap capacitors 42 and 43 are also lowered with the switching operation on the high side of the V phase and the W phase.
In the bootstrap capacitors 41 to 43, charging and discharging are repeated in this way.

In the first embodiment, there are the following two periods in which the low-side switch elements Qu2, Qv2, and Qw2 are off. The first period is a period during which only the high side performs the PWM operation, and the second period is a period during which both the high side and the low side are turned off for detecting the winding voltage of the motor 5.
FIG. 5 is a diagram illustrating a state where the energization pattern of the inverter device according to the first embodiment is changed.
In the first embodiment, the voltage detectors OP1 to OP3 detect the decrease in the charge amount of the bootstrap capacitors 41 to 43 as the voltage of the bootstrap capacitors 41 to 43 due to the influence of such a period (step S1). ). Then, it is determined in step S2 of the reference value comparison unit 21 whether or not the detection voltage has decreased below the reference value. When the detection voltage falls below the reference value, the PWM frequency control unit 22 decreases the PWM frequency (FIG. 5). (See the portion denoted by reference numeral 101). Note that if there is even one phase drop from the reference value, the entire PWM frequency is reduced.

  Then, as shown in FIG.5 (c), the voltage drop of the bootstrap capacitors 41-43 is suppressed (refer the part shown with the code | symbol 102 of FIG. 5). Thus, even if the bootstrap capacitors 41 to 43 are not increased in capacity, it is possible to cope with a case where the low-side switch-off period is long, and the cost is suppressed. Further, such a function of ensuring a reliable operation is useful for ensuring a normal operation of the inverter device 1.

In order to clarify the operation of the first embodiment, the following description is added.
FIG. 6 is an explanatory diagram showing a circuit configuration example of the inverter device. FIG. 6 shows a portion of one phase, but the other phases have the same configuration. For the sake of explanation, the same reference numerals as those in the first embodiment are shown in FIG.
In order to supply the high-side drive power by the low-side switching operation, it is possible to adopt a configuration as shown in FIG.
In such a configuration, when the high-side drive power is supplied by the bootstrap capacitor, the drive power supply voltage decreases with the high-side operation.
Even when the low-side switch-off period as described above is long, the bootstrap capacitor has to be increased in capacity to prevent the high-side switching from being disabled. Further, since the switch-off period becomes long at the lowest frequency in the inverter device 1, the capacity of the bootstrap capacitor must be further increased. Such an increase in capacity causes an increase in cost and an increase in circuit size.
On the other hand, the first embodiment is advantageous in that it does not increase the capacity of the bootstrap capacitor and copes with the case where the low-side switch-off period is long, thereby reducing the cost, downsizing the circuit, and improving the reliability.

Next, the effect will be described.
In the inverter device of the first embodiment, the effects listed below can be obtained.

  (1) Switching elements Qu1 to Qw2 provided to form a high-side and low-side bridge circuit in the inverter device 1 that performs PWM switching operation at least on the high-side by a bridge configuration of the high-side and low-side and drives the load A switch drive circuit 31 to 36 for driving the switch elements Qu1 to Qw2, a bootstrap capacitor 41 to 43 that is charged by a low-side switch operation and supplies drive power to the high-side switch drive circuits 31 to 33, and a boot Voltage detectors OP1 to OP3 that detect the voltages of the strap capacitors 41 to 43, the control unit 2 that controls the switch drive circuits 31 to 36, and the control unit 2, based on the detection voltages of the bootstrap capacitors 41 to 43 The reference value comparison unit 21 for changing the PWM frequency to a lower frequency Because having a fine PWM frequency control unit 22, even if the time does not drive the low-side switching element is long, it is possible to reduce the capacitance.

The second embodiment is an example in which the frequency change is performed by predicting the voltage drop of the bootstrap capacitor.
The configuration will be described.
FIG. 7 is an explanatory diagram illustrating a partial block configuration of the control unit 2 of the inverter device 1 according to the second embodiment.
The control unit 2 according to the second embodiment includes a voltage drop rate calculation unit 24, a voltage prediction unit 25, and a reference value comparison unit 26.
The voltage decrease rate calculation unit 24 receives the detection voltage of the bootstrap capacitors 41 to 43 as an input, and calculates the voltage decrease rate per unit time as the voltage decrease rate. And the thing of the earliest fall rate is memorize | stored, and it outputs to the voltage estimation part 25. FIG.

The voltage prediction unit 25 receives the voltage decrease rate from the voltage decrease rate calculation unit 24 and the drive command value from the drive pulse calculation unit 23, and the low-side switch elements Qu2, Qv2, Qw2 included in the drive command value are turned off. The value at which the voltage of the bootstrap capacitors 41 to 43 is lowest, that is, the value immediately before the low side is turned on is calculated from the time and the voltage drop rate, and output to the reference value comparison unit 26.
The reference value comparison unit 26 compares the reference value set in advance with the predicted value from the voltage prediction unit 25 and outputs the comparison result to the PWM frequency control unit 22.
Since other configurations are the same as those of the first embodiment, description thereof is omitted.

The operation will be described.
[Voltage drop rate calculation process]
FIG. 8 is a flowchart showing the flow of the voltage drop rate calculation process executed by the control unit 2 of the inverter device 1 according to the second embodiment. Each step will be described below.

  In step S11, the voltage drop rate calculation unit 24 inputs detection voltages of the voltage detectors OP1 to OP3.

  In step S12, the voltage drop rate calculation unit 24 calculates the voltage drop rate from the change in the detected voltage per unit time. In this process, the voltage drop rate for each phase and each time is calculated, and the calculation is performed using the fastest drop rate. Alternatively, the calculation is performed for each phase, and the calculation is performed with the fastest reduction rate of each phase.

In step S13, the voltage drop rate calculation unit 24 stores and updates the calculated voltage drop rate. By updating, it responds to changes over time.
[PWM frequency change processing]
FIG. 9 is a flowchart showing a flow of a PWM frequency changing process executed by the control unit 2 of the inverter device 1 according to the second embodiment. Each step will be described below.
In addition, about the process similar to the flowchart shown in FIG. 3, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In step S <b> 14, the voltage prediction unit 25 inputs the detection voltages of the voltage detectors OP <b> 1 to OP <b> 3 and the drive pulse command value output from the drive pulse calculation unit 23.

  In step S <b> 15, the voltage prediction unit 25 inputs the voltage decrease rate from the voltage decrease rate calculation unit 24.

  In step S <b> 16, the voltage predicting unit 25 determines the bootstrap capacitors 41 to 43 immediately before the time when the low-side switch is turned on from the low-side switch-off time and the voltage drop rate included in the detected voltage and the drive pulse command value. Calculate the predicted voltage value.

  In step S17, the reference value comparison unit 26 compares the voltage predicted value with a preset reference voltage. If the voltage predicted value is equal to or higher than the reference voltage, the process proceeds to step S3. If the voltage predicted value is lower than the reference voltage, step S4 is performed. Proceed to

[Capacitor suppression]
In the second embodiment, the voltage across the bootstrap capacitors 41 to 43 is detected by the voltage detectors OP1 to OP3, and the voltage reduction rate (voltage reduction rate per unit) is calculated (steps S11 to S11 by the voltage reduction rate calculation unit 24). Process of S13). Using this voltage drop rate and the low-side off period, the lowest value at which the bootstrap capacitors 41 to 43 are lowered, that is, the voltage of the bootstrap capacitors 41 to 43 immediately before the low-side switch is turned on is predicted (voltage prediction). Steps S14 to S16 by the unit 25).

As described above, in the second embodiment, when the predicted value becomes lower than the reference value, the PWM frequency is decreased when the prediction is performed. For this reason, the driving power source of the high-side switch driving circuits 31 to 33 can be ensured sufficiently by performing the operation from a faster time. Therefore, the capacitor capacity is suppressed.
It should be noted that the time during which the low-side switch elements Qu2, Qv2, Qw2 included in the drive command value from the drive pulse calculation unit 23 are turned off may be detected by edge extraction or the like of this pulse signal.

Explain the effect.
The inverter device according to the second embodiment has the following effects in addition to the above (1).
(2) In the above (1), the means for changing the frequency includes a voltage drop rate calculation unit 24 for calculating the voltage drop rate of the bootstrap capacitors 41 to 43 from a change in the detection voltage of the bootstrap capacitors 41 to 43, and a control. Bootstrap capacitors 41 to 41 that are most lowered based on the low-side switch-off time, the voltage drop rate, and the detected voltage of the bootstrap capacitors 41 to 43 that are extracted from the control commands to the switch drive circuits 31 to 36 that are calculated by the unit 2 A voltage prediction unit 25 that calculates the predicted voltage value of 43, and a reference value comparison unit 26 that compares a preset reference value with the predicted voltage value of the bootstrap capacitors 41 to 43, and predicts the voltage of the bootstrap capacitors 41 to 43. When the value is lower than the reference value, the PWM frequency is changed to a lower frequency. Without Kusuru, it is possible to perform a sufficient power supply to the actuation of the switch driver circuits 31 to 33.
Since other functions and effects are the same as those of the first embodiment, description thereof is omitted.

The third embodiment is an example in which an upper limit value and a lower limit value are set when the PWM frequency is changed.
The configuration will be described.
FIG. 10 is an explanatory diagram illustrating a partial block configuration of the control unit 2 of the inverter device 1 according to the third embodiment.
The upper limit value output unit 221 stores and outputs a preset upper limit value of the PWM frequency. The upper limit value of the PWM frequency is determined by conditions such as the processing capability of the control unit 2, switch heat generation, and EMC (electromagnetic compatibility).

The lower limit output unit 222 stores and outputs a preset lower limit value of the PWM frequency. The lower limit value of the PWM frequency is determined by the lowest frequency (for example, a range in which the motor 5 is not stopped) at which deterioration of output control to the motor 5 of the inverter device 1 is allowed.
In the third embodiment, when changing the PWM frequency, the PWM frequency control unit 22 sets a high PWM frequency for performing a normal operation as an upper limit value and a value when the PWM frequency is lowered as a lower limit value.
Since other configurations are the same as those of the second embodiment, description thereof is omitted.

The operation will be described.
[Operation to ensure control accuracy]
In the third embodiment, when the PWM frequency control unit 22 changes the PWM frequency, the normal state is set as the upper limit value, and the frequency when changing to a lower frequency is set as the lower limit value.
Then, for example, the reference value to be compared with the predicted voltage value of the bootstrap capacitors 41 to 43 is set in two stages so that the margin is large or small due to the expected amount of variation to be considered. If the control content of the control unit 2 allows the control to become coarser if the PWM frequency is reduced, the lower limit value is set. If the control content is highly demanded to be finely controlled, the lower limit value is set. Set the frequency slightly higher than the value.
In this way, consideration is given so that lowering the PWM frequency does not affect the motor control of the control unit 2.

Explain the effect. The inverter device according to the third embodiment has the following effects in addition to the above (1) and (2).
(3) In the above (1) or (2), an upper limit output unit 221 that stores and outputs an upper limit value of a preset PWM frequency, and a lower limit value output unit that stores and outputs a lower limit value of a preset PWM frequency 222 is provided, and the PWM frequency control unit 22 changes the PWM frequency to a lower frequency between the preset upper limit value of the PWM frequency and the lower limit value of the PWM frequency. Consideration can be made so as not to affect the motor control of the control unit 2.
Other functions and effects are the same as those of the second embodiment, and thus description thereof is omitted.

  As mentioned above, although the inverter apparatus of this invention has been demonstrated based on Example 1-Example 3, it is not restricted to these Examples about a concrete structure, It concerns on each claim of a claim Design changes and additions are allowed without departing from the scope of the invention.

For example, in the first embodiment, the motor is described as the load. However, for example, LED lighting may be used.
Further, in the third embodiment, the description has been given of the case where the lower limit value and the frequency that is slightly higher than the lower limit value are changed. However, another control may be performed between the upper limit value and the lower limit value. For example, if a frequency slightly lower than the upper limit frequency is used based on information obtained from the control unit 2, the power consumption of the switch drive circuits 31 to 33 is reduced, and switching to the lower limit value is less likely to occur. it can.

It is a figure which shows the circuit structure of the inverter apparatus of Example 1. FIG. It is explanatory drawing which shows the one part block structure of the control part of the inverter apparatus of Example 1. FIG. 3 is a flowchart illustrating a flow of a PWM frequency change process executed by a control unit of the inverter device according to the first embodiment. It is a figure explaining the electricity supply pattern of the inverter apparatus of Example 1. FIG. It is a figure explaining the state which changed the electricity supply pattern of the inverter apparatus of Example 1. FIG. It is explanatory drawing which shows the circuit structural example of an inverter apparatus. It is explanatory drawing which shows the one part block structure of the control part of the inverter apparatus of Example 2. FIG. It is a flowchart which shows the flow of the voltage fall rate calculation process performed in the control part of the inverter apparatus of Example 2. FIG. It is a flowchart which shows the flow of the PWM frequency change process performed in the control part 2 of the inverter apparatus 1 of Example 2. FIG. It is explanatory drawing which shows the one part block structure of the control part of the inverter apparatus of Example 3. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inverter apparatus 2 Control part 21 Reference value comparison part 22 Frequency control part 221 Upper limit value output part 222 Lower limit value output part 23 Drive pulse calculation part 24 Voltage drop rate calculation part 25 Voltage prediction part 26 Reference value comparison parts 31-36 Switch drive Circuits 41 to 43 Bootstrap capacitor 5 Motor 5u, 5v, 5w Coil 6 Capacitor 71 to 73 Diode 8 Capacitor 9 Power source 10 to 12 Resistor Du1 to Dw2 Diode Qu1 to Qw2 Switch element
OP1 to OP3 Voltage detector

Claims (3)

In the inverter device that drives the load by performing PWM switching operation at least on the high side by the bridge configuration by the high side and the low side,
A switch element provided to form a high-side and low-side bridge circuit;
Switch driving means for driving the switch element;
A bootstrap capacitor that is charged by the low-side switch operation and supplies the drive power for the high-side switch drive means;
Voltage detection means for detecting the voltage of the bootstrap capacitor;
Control means for controlling the switch driving means;
A frequency changing means provided in the control means, for changing the PWM frequency to a lower frequency based on the detection voltage of the bootstrap capacitor;
With
An inverter device characterized by that. The inverter device according to claim 1,
The frequency changing means is
A voltage drop rate calculating means for calculating a voltage drop rate of the bootstrap capacitor from a change in a detection voltage of the bootstrap capacitor;
The voltage prediction of the bootstrap capacitor that is most reduced based on the low-side switch-off time extracted from the control command to the switch driver calculated by the controller, the voltage reduction rate, and the detected voltage of the bootstrap capacitor Voltage predicting means for calculating a value;
A reference value comparison means for comparing a preset reference value with a predicted voltage value of the bootstrap capacitor;
An inverter device comprising: changing a PWM frequency to a lower frequency when a predicted voltage value of the bootstrap capacitor is lower than the reference value. In the inverter device according to claim 1 or 2,
The inverter device characterized in that the frequency changing means changes the PWM frequency to a lower frequency between a preset upper limit value of the PWM frequency and a lower limit value of the PWM frequency.

Images